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cd12f615 WG |
1 | /* |
2 | * (C) Copyright 2006 | |
3 | * MicroSys GmbH | |
4 | * | |
5 | * (C) Copyright 2009 | |
6 | * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de. | |
7 | * | |
3765b3e7 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
cd12f615 WG |
9 | */ |
10 | ||
11 | #ifndef __CONFIG_H | |
12 | #define __CONFIG_H | |
13 | ||
14 | /* | |
15 | * High Level Configuration Options | |
16 | */ | |
17 | ||
18 | #define CONFIG_MPC5200 | |
b2a6dfe4 MY |
19 | #define CONFIG_MPX5200 1 /* MPX5200 board */ |
20 | #define CONFIG_MPC5200_DDR 1 /* use DDR RAM */ | |
cd12f615 WG |
21 | #define CONFIG_IPEK01 /* Motherboard is ipek01 */ |
22 | ||
2ae18241 WD |
23 | #define CONFIG_SYS_TEXT_BASE 0xfc000000 |
24 | ||
cd12f615 WG |
25 | #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */ |
26 | ||
27 | #define CONFIG_MISC_INIT_R | |
28 | ||
cd12f615 WG |
29 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
30 | #ifdef CONFIG_CMD_KGDB | |
31 | #define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ | |
32 | #endif | |
33 | ||
34 | /* | |
35 | * Serial console configuration | |
36 | */ | |
37 | #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ | |
38 | #define CONFIG_BAUDRATE 115200 /* ... at 9600 bps */ | |
39 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } | |
40 | ||
41 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
42 | ||
43 | /* | |
44 | * Video configuration for LIME GDC | |
45 | */ | |
46 | #define CONFIG_VIDEO | |
47 | #ifdef CONFIG_VIDEO | |
48 | #define CONFIG_VIDEO_MB862xx | |
49 | #define CONFIG_VIDEO_MB862xx_ACCEL | |
50 | #define VIDEO_FB_16BPP_WORD_SWAP | |
51 | #define CONFIG_CFB_CONSOLE | |
52 | #define CONFIG_VIDEO_LOGO | |
53 | #define CONFIG_VIDEO_BMP_LOGO | |
54 | #define CONFIG_CONSOLE_EXTRA_INFO | |
55 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
56 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV | |
57 | #define CONFIG_VIDEO_SW_CURSOR | |
58 | #define CONFIG_SPLASH_SCREEN | |
59 | #define CONFIG_VIDEO_BMP_GZIP | |
60 | #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */ | |
61 | /* Lime clock frequency */ | |
62 | #define CONFIG_SYS_MB862xx_CCF 0x90000 /* geo 166MHz other 133MHz */ | |
63 | /* SDRAM parameter */ | |
64 | #define CONFIG_SYS_MB862xx_MMR 0x41c767e3 | |
65 | #endif | |
66 | ||
67 | /* | |
68 | * PCI Mapping: | |
69 | * 0x40000000 - 0x4fffffff - PCI Memory | |
70 | * 0x50000000 - 0x50ffffff - PCI IO Space | |
71 | */ | |
72 | #define CONFIG_PCI 1 | |
73 | #define CONFIG_PCI_PNP 1 | |
74 | #define CONFIG_PCI_SCAN_SHOW 1 | |
75 | ||
76 | #define CONFIG_PCI_MEM_BUS 0x40000000 | |
77 | #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS | |
78 | #define CONFIG_PCI_MEM_SIZE 0x10000000 | |
79 | ||
80 | #define CONFIG_PCI_IO_BUS 0x50000000 | |
81 | #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS | |
82 | #define CONFIG_PCI_IO_SIZE 0x01000000 | |
83 | ||
cd12f615 WG |
84 | #define CONFIG_MII 1 |
85 | #define CONFIG_EEPRO100 1 | |
86 | #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ | |
87 | ||
88 | /* Partitions */ | |
89 | #define CONFIG_DOS_PARTITION | |
90 | ||
91 | /* USB */ | |
92 | #define CONFIG_USB_OHCI_NEW | |
93 | #define CONFIG_SYS_OHCI_BE_CONTROLLER | |
cd12f615 WG |
94 | |
95 | #define CONFIG_SYS_USB_OHCI_CPU_INIT | |
96 | #define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB | |
97 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200" | |
98 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 | |
99 | ||
100 | /* | |
101 | * Command line configuration. | |
102 | */ | |
cd12f615 WG |
103 | #ifdef CONFIG_VIDEO |
104 | #define CONFIG_CMD_BMP /* BMP support */ | |
105 | #endif | |
106 | #define CONFIG_CMD_DATE /* support for RTC, date/time...*/ | |
cd12f615 WG |
107 | #define CONFIG_CMD_IDE /* IDE harddisk support */ |
108 | #define CONFIG_CMD_IRQ /* irqinfo */ | |
cd12f615 | 109 | #define CONFIG_CMD_PCI /* pciinfo */ |
cd12f615 WG |
110 | |
111 | #define CONFIG_SYS_LOWBOOT 1 | |
112 | ||
113 | /* | |
114 | * Autobooting | |
115 | */ | |
cd12f615 WG |
116 | |
117 | #define CONFIG_PREBOOT "echo;" \ | |
118 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ | |
119 | "echo" | |
120 | ||
121 | #undef CONFIG_BOOTARGS | |
122 | ||
123 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
124 | "netdev=eth0\0" \ | |
125 | "consoledev=ttyPSC0\0" \ | |
126 | "hostname=ipek01\0" \ | |
127 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
128 | "nfsroot=${serverip}:${rootpath}\0" \ | |
129 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
130 | "addip=setenv bootargs ${bootargs} " \ | |
131 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
132 | ":${hostname}:${netdev}:off panic=1\0" \ | |
133 | "addtty=setenv bootargs ${bootargs} " \ | |
134 | "console=${consoledev},${baudrate}\0" \ | |
135 | "flash_nfs=run nfsargs addip addtty;" \ | |
136 | "bootm ${kernel_addr} - ${fdtaddr}\0" \ | |
137 | "flash_self=run ramargs addip addtty;" \ | |
138 | "bootm ${kernel_addr} ${ramdisk_addr} ${fdtaddr}\0" \ | |
139 | "net_nfs=tftp 200000 ${bootfile}; tftp ${fdtaddr} ${fdtfile};" \ | |
140 | "run nfsargs addip addtty;" \ | |
141 | "bootm ${loadaddr} - ${fdtaddr}\0" \ | |
142 | "rootpath=/opt/eldk/ppc_6xx\0" \ | |
143 | "bootfile=ipek01/uImage\0" \ | |
144 | "load=tftp 100000 ipek01/u-boot.bin\0" \ | |
145 | "update=protect off FC000000 +60000; era FC000000 +60000; " \ | |
146 | "cp.b 100000 FC000000 ${filesize}\0" \ | |
147 | "upd=run load;run update\0" \ | |
148 | "fdtaddr=800000\0" \ | |
149 | "loadaddr=400000\0" \ | |
150 | "fdtfile=ipek01/ipek01.dtb\0" \ | |
151 | "" | |
152 | ||
153 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
154 | ||
155 | /* | |
156 | * IPB Bus clocking configuration. | |
157 | */ | |
158 | #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* for 133MHz */ | |
159 | /* PCI clock must be 33, because board will not boot */ | |
160 | #undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* for 66MHz */ | |
161 | ||
162 | /* | |
163 | * Open firmware flat tree support | |
164 | */ | |
cd12f615 WG |
165 | #define OF_CPU "PowerPC,5200@0" |
166 | #define OF_SOC "soc5200@f0000000" | |
167 | #define OF_TBCLK (bd->bi_busfreq / 4) | |
168 | ||
169 | /* | |
170 | * I2C configuration | |
171 | */ | |
172 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
173 | #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ | |
174 | ||
175 | #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ | |
176 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
177 | ||
178 | /* | |
179 | * EEPROM configuration | |
180 | */ | |
181 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 | |
182 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
183 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 | |
184 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
185 | ||
186 | /* | |
187 | * RTC configuration | |
188 | */ | |
189 | #define CONFIG_RTC_PCF8563 | |
190 | #define CONFIG_SYS_I2C_RTC_ADDR 0x51 | |
191 | ||
192 | #define CONFIG_SYS_FLASH_BASE 0xFC000000 | |
193 | #define CONFIG_SYS_FLASH_SIZE 0x01000000 | |
194 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \ | |
195 | CONFIG_SYS_MONITOR_LEN) | |
196 | ||
197 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ | |
198 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */ | |
199 | #define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ | |
200 | ||
201 | /* use CFI flash driver */ | |
202 | #define CONFIG_FLASH_CFI_DRIVER | |
203 | #define CONFIG_SYS_FLASH_CFI | |
204 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
205 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 | |
206 | ||
207 | /* | |
208 | * Environment settings | |
209 | */ | |
210 | #define CONFIG_ENV_IS_IN_FLASH 1 | |
211 | #define CONFIG_ENV_SIZE 0x10000 | |
212 | #define CONFIG_ENV_SECT_SIZE 0x20000 | |
213 | #define CONFIG_ENV_OVERWRITE 1 | |
214 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) | |
215 | #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE | |
216 | ||
217 | /* | |
218 | * Memory map | |
219 | */ | |
220 | #define CONFIG_SYS_MBAR 0xf0000000 | |
221 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 | |
222 | #define CONFIG_SYS_DEFAULT_MBAR 0x80000000 | |
223 | #define CONFIG_SYS_SRAM_BASE 0xF1000000 | |
224 | #define CONFIG_SYS_SRAM_SIZE 0x00200000 | |
225 | #define CONFIG_SYS_LIME_BASE 0xE4000000 | |
226 | #define CONFIG_SYS_LIME_SIZE 0x04000000 | |
227 | #define CONFIG_SYS_FPGA_BASE 0xC0000000 | |
228 | #define CONFIG_SYS_FPGA_SIZE 0x10000000 | |
229 | #define CONFIG_SYS_MPEG_BASE 0xe2000000 | |
230 | #define CONFIG_SYS_MPEG_SIZE 0x01000000 | |
231 | #define CONFIG_SYS_CF_BASE 0xe1000000 | |
232 | #define CONFIG_SYS_CF_SIZE 0x01000000 | |
233 | ||
234 | /* Use SRAM until RAM will be available */ | |
235 | #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM | |
236 | /* End of used area in DPRAM */ | |
553f0982 | 237 | #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE |
cd12f615 | 238 | |
553f0982 | 239 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ |
25ddd1fb | 240 | GENERATED_GBL_DATA_SIZE) |
cd12f615 WG |
241 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
242 | ||
14d0a02a | 243 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
cd12f615 WG |
244 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
245 | # define CONFIG_SYS_RAMBOOT 1 | |
246 | #endif | |
247 | ||
248 | #define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ | |
249 | #define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 128 kB for malloc() */ | |
250 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
251 | ||
252 | /* | |
253 | * Ethernet configuration | |
254 | */ | |
255 | #define CONFIG_MPC5xxx_FEC 1 | |
256 | #define CONFIG_MPC5xxx_FEC_MII100 | |
257 | #define CONFIG_PHY_ADDR 0x00 | |
258 | ||
259 | /* | |
260 | * GPIO configuration | |
261 | */ | |
262 | #define CONFIG_SYS_GPS_PORT_CONFIG 0x1d556624 | |
263 | ||
264 | /* | |
265 | * Miscellaneous configurable options | |
266 | */ | |
267 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
cd12f615 WG |
268 | #ifdef CONFIG_CMD_KGDB |
269 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
270 | #else | |
271 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
272 | #endif | |
273 | /* Print Buffer Size */ | |
274 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
275 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
276 | /* max number of command args */ | |
277 | #define CONFIG_SYS_MAXARGS 16 | |
278 | /* Boot Argument Buffer Size */ | |
279 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
280 | ||
cd12f615 WG |
281 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
282 | #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1...15 MB in DRAM */ | |
283 | ||
284 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ | |
285 | ||
cd12f615 WG |
286 | /* |
287 | * Various low-level settings | |
288 | */ | |
cd12f615 WG |
289 | #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI |
290 | #define CONFIG_SYS_HID0_FINAL HID0_ICE | |
cd12f615 WG |
291 | |
292 | #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE | |
293 | #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE | |
294 | #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE | |
295 | #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE | |
296 | #define CONFIG_SYS_CS1_START CONFIG_SYS_SRAM_BASE | |
297 | #define CONFIG_SYS_CS1_SIZE CONFIG_SYS_SRAM_SIZE | |
298 | #define CONFIG_SYS_CS3_START CONFIG_SYS_LIME_BASE | |
299 | #define CONFIG_SYS_CS3_SIZE CONFIG_SYS_LIME_SIZE | |
300 | #define CONFIG_SYS_CS6_START CONFIG_SYS_FPGA_BASE | |
301 | #define CONFIG_SYS_CS6_SIZE CONFIG_SYS_FPGA_SIZE | |
302 | #define CONFIG_SYS_CS5_START CONFIG_SYS_CF_BASE | |
303 | #define CONFIG_SYS_CS5_SIZE CONFIG_SYS_CF_SIZE | |
304 | #define CONFIG_SYS_CS7_START CONFIG_SYS_MPEG_BASE | |
305 | #define CONFIG_SYS_CS7_SIZE CONFIG_SYS_MPEG_SIZE | |
306 | ||
307 | #ifdef CONFIG_SYS_PCISPEED_66 | |
308 | #define CONFIG_SYS_BOOTCS_CFG 0x0006F900 | |
309 | #define CONFIG_SYS_CS1_CFG 0x0004FB00 | |
310 | #define CONFIG_SYS_CS2_CFG 0x0006F900 | |
311 | #else | |
312 | #define CONFIG_SYS_BOOTCS_CFG 0x0002F900 | |
313 | #define CONFIG_SYS_CS1_CFG 0x0001FB00 | |
314 | #define CONFIG_SYS_CS2_CFG 0x0002F90C | |
315 | #endif | |
316 | ||
317 | /* | |
318 | * Ack active, Muxed mode, AS=24 bit address, DS=32 bit data, 0 | |
319 | * waitstates, writeswap and readswap enabled | |
320 | */ | |
321 | #define CONFIG_SYS_CS3_CFG 0x00FFFB0C | |
322 | #define CONFIG_SYS_CS6_CFG 0x00FFFB0C | |
323 | #define CONFIG_SYS_CS7_CFG 0x4040751C | |
324 | ||
325 | #define CONFIG_SYS_CS_BURST 0x00000000 | |
326 | #define CONFIG_SYS_CS_DEADCYCLE 0x33330000 | |
327 | ||
328 | #define CONFIG_SYS_RESET_ADDRESS 0xff000000 | |
329 | ||
330 | /*----------------------------------------------------------------------- | |
331 | * USB stuff | |
332 | *----------------------------------------------------------------------- | |
333 | */ | |
334 | #define CONFIG_USB_CLOCK 0x0001BBBB | |
335 | #define CONFIG_USB_CONFIG 0x00005000 | |
336 | ||
337 | /*----------------------------------------------------------------------- | |
338 | * IDE/ATA stuff Supports IDE harddisk | |
339 | *----------------------------------------------------------------------- | |
340 | */ | |
341 | #define CONFIG_IDE_PREINIT | |
342 | ||
343 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ | |
344 | #define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ | |
345 | ||
346 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 | |
347 | ||
348 | #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA | |
349 | ||
350 | /* Offset for data I/O */ | |
351 | #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) | |
352 | ||
353 | /* Offset for normal register accesses */ | |
354 | #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) | |
355 | ||
356 | /* Offset for alternate registers */ | |
357 | #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) | |
358 | ||
359 | /* Interval between registers */ | |
360 | #define CONFIG_SYS_ATA_STRIDE 4 | |
361 | ||
362 | #endif /* __CONFIG_H */ |