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4745acaa SR |
1 | /* |
2 | * (C) Copyright 2007 | |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
4 | * | |
5 | * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com> | |
6 | * | |
1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
4745acaa SR |
8 | */ |
9 | ||
10 | /************************************************************************ | |
11 | * katmai.h - configuration for AMCC Katmai (440SPe) | |
12 | ***********************************************************************/ | |
13 | ||
14 | #ifndef __CONFIG_H | |
15 | #define __CONFIG_H | |
83b4cfa3 | 16 | |
4745acaa SR |
17 | /*----------------------------------------------------------------------- |
18 | * High Level Configuration Options | |
19 | *----------------------------------------------------------------------*/ | |
20 | #define CONFIG_KATMAI 1 /* Board is Katmai */ | |
4745acaa SR |
21 | #define CONFIG_440 1 /* ... PPC440 family */ |
22 | #define CONFIG_440SPE 1 /* Specifc SPe support */ | |
2a72e9ed | 23 | #define CONFIG_440SPE_REVA 1 /* Support old Rev A. */ |
4745acaa | 24 | #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ |
6d0f6bcf | 25 | #define CONFIG_SYS_4xx_RESET_TYPE 0x2 /* use chip reset on this board */ |
490f2040 | 26 | |
2ae18241 WD |
27 | #define CONFIG_SYS_TEXT_BASE 0xFFFA0000 |
28 | ||
5d812b8b SR |
29 | /* |
30 | * Enable this board for more than 2GB of SDRAM | |
31 | */ | |
5d812b8b | 32 | #define CONFIG_VERY_BIG_RAM |
5d812b8b | 33 | |
490f2040 SR |
34 | /* |
35 | * Include common defines/options for all AMCC eval boards | |
36 | */ | |
37 | #define CONFIG_HOSTNAME katmai | |
38 | #include "amcc-common.h" | |
4745acaa | 39 | |
4745acaa SR |
40 | #undef CONFIG_SHOW_BOOT_PROGRESS |
41 | ||
42 | /*----------------------------------------------------------------------- | |
43 | * Base addresses -- Note these are effective addresses where the | |
44 | * actual resources get mapped (not physical addresses) | |
45 | *----------------------------------------------------------------------*/ | |
6d0f6bcf | 46 | #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH */ |
6d0f6bcf | 47 | #define CONFIG_SYS_ISRAM_BASE 0x90000000 /* internal SRAM */ |
4745acaa | 48 | |
6d0f6bcf JCPV |
49 | #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory */ |
50 | #define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ | |
51 | #define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE | |
4745acaa | 52 | |
6d0f6bcf JCPV |
53 | #define CONFIG_SYS_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */ |
54 | #define CONFIG_SYS_PCIE_MEMSIZE 0x08000000 /* smallest incr for PCIe port */ | |
55 | #define CONFIG_SYS_PCIE_BASE 0xe0000000 /* PCIe UTL regs */ | |
4745acaa | 56 | |
6d0f6bcf JCPV |
57 | #define CONFIG_SYS_PCIE0_CFGBASE 0xc0000000 |
58 | #define CONFIG_SYS_PCIE1_CFGBASE 0xc1000000 | |
59 | #define CONFIG_SYS_PCIE2_CFGBASE 0xc2000000 | |
60 | #define CONFIG_SYS_PCIE0_XCFGBASE 0xc3000000 | |
61 | #define CONFIG_SYS_PCIE1_XCFGBASE 0xc3001000 | |
62 | #define CONFIG_SYS_PCIE2_XCFGBASE 0xc3002000 | |
4745acaa | 63 | |
97923770 | 64 | /* base address of inbound PCIe window */ |
6d0f6bcf | 65 | #define CONFIG_SYS_PCIE_INBOUND_BASE 0x0000000000000000ULL |
97923770 | 66 | |
4745acaa | 67 | /* System RAM mapped to PCI space */ |
6d0f6bcf JCPV |
68 | #define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE |
69 | #define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE | |
4745acaa SR |
70 | #define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024) |
71 | ||
6d0f6bcf | 72 | #define CONFIG_SYS_ACE_BASE 0xfe000000 /* Xilinx ACE controller - Compact Flash */ |
4745acaa SR |
73 | |
74 | /*----------------------------------------------------------------------- | |
75 | * Initial RAM & stack pointer (placed in internal SRAM) | |
76 | *----------------------------------------------------------------------*/ | |
6d0f6bcf JCPV |
77 | #define CONFIG_SYS_TEMP_STACK_OCM 1 |
78 | #define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE | |
79 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */ | |
553f0982 | 80 | #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */ |
4745acaa | 81 | |
25ddd1fb | 82 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
800eb096 | 83 | #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) |
4745acaa SR |
84 | |
85 | /*----------------------------------------------------------------------- | |
86 | * Serial Port | |
87 | *----------------------------------------------------------------------*/ | |
550650dd | 88 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
6d0f6bcf | 89 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK |
4745acaa SR |
90 | |
91 | /*----------------------------------------------------------------------- | |
92 | * DDR SDRAM | |
93 | *----------------------------------------------------------------------*/ | |
94 | #define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ | |
ba58e4c9 | 95 | #define SPD_EEPROM_ADDRESS {0x51, 0x52} /* SPD i2c spd addresses*/ |
2721a68a | 96 | #define CONFIG_DDR_ECC 1 /* with ECC support */ |
845c6c95 | 97 | #define CONFIG_DDR_RQDC_FIXED 0x80000038 /* optimal value found by GDA*/ |
4745acaa | 98 | #undef CONFIG_STRESS |
4745acaa SR |
99 | |
100 | /*----------------------------------------------------------------------- | |
101 | * I2C | |
102 | *----------------------------------------------------------------------*/ | |
880540de | 103 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000 |
4745acaa | 104 | |
6d0f6bcf | 105 | #define CONFIG_SYS_SPD_BUS_NUM 0 /* The I2C bus for SPD */ |
4745acaa SR |
106 | |
107 | #define IIC0_BOOTPROM_ADDR 0x50 | |
108 | #define IIC0_ALT_BOOTPROM_ADDR 0x54 | |
109 | ||
6d0f6bcf JCPV |
110 | #define CONFIG_SYS_I2C_EEPROM_ADDR (0x50) |
111 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
112 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
113 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
4745acaa | 114 | |
efe12bce SR |
115 | /* I2C bootstrap EEPROM */ |
116 | #define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x50 | |
117 | #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0 | |
118 | #define CONFIG_4xx_CONFIG_BLOCKSIZE 8 | |
119 | ||
4745acaa SR |
120 | /* I2C RTC */ |
121 | #define CONFIG_RTC_M41T11 1 | |
6d0f6bcf JCPV |
122 | #define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */ |
123 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
124 | #define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with linux */ | |
4745acaa SR |
125 | |
126 | /* I2C DTT */ | |
127 | #define CONFIG_DTT_ADM1021 1 /* ADM1021 temp sensor support */ | |
6d0f6bcf | 128 | #define CONFIG_SYS_DTT_BUS_NUM 1 /* The I2C bus for DTT */ |
4745acaa SR |
129 | /* |
130 | * standard dtt sensor configuration - bottom bit will determine local or | |
131 | * remote sensor of the ADM1021, the rest determines index into | |
6d0f6bcf | 132 | * CONFIG_SYS_DTT_ADM1021 array below. |
4745acaa SR |
133 | */ |
134 | #define CONFIG_DTT_SENSORS { 0, 1 } | |
135 | ||
136 | /* | |
137 | * ADM1021 temp sensor configuration (see dtt/adm1021.c for details). | |
138 | * there will be one entry in this array for each two (dummy) sensors in | |
139 | * CONFIG_DTT_SENSORS. | |
140 | * | |
141 | * For Katmai board: | |
142 | * - only one ADM1021 | |
143 | * - i2c addr 0x18 | |
144 | * - conversion rate 0x02 = 0.25 conversions/second | |
145 | * - ALERT ouput disabled | |
146 | * - local temp sensor enabled, min set to 0 deg, max set to 85 deg | |
147 | * - remote temp sensor enabled, min set to 0 deg, max set to 85 deg | |
148 | */ | |
6d0f6bcf | 149 | #define CONFIG_SYS_DTT_ADM1021 { { 0x18, 0x02, 0, 1, 0, 85, 1, 0, 58} } |
4745acaa SR |
150 | |
151 | /*----------------------------------------------------------------------- | |
152 | * Environment | |
153 | *----------------------------------------------------------------------*/ | |
5a1aceb0 | 154 | #define CONFIG_ENV_IS_IN_FLASH 1 /* Environment uses flash */ |
4745acaa | 155 | |
490f2040 SR |
156 | /* |
157 | * Default environment variables | |
158 | */ | |
4745acaa | 159 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
490f2040 SR |
160 | CONFIG_AMCC_DEF_ENV \ |
161 | CONFIG_AMCC_DEF_ENV_POWERPC \ | |
490f2040 | 162 | CONFIG_AMCC_DEF_ENV_NOR_UPD \ |
fc21cd55 SR |
163 | "kernel_addr=ff000000\0" \ |
164 | "fdt_addr=ff1e0000\0" \ | |
165 | "ramdisk_addr=ff200000\0" \ | |
6efc1fc0 | 166 | "pciconfighost=1\0" \ |
d4cb2d17 | 167 | "pcie_mode=RP:RP:RP\0" \ |
4745acaa | 168 | "" |
079a136c | 169 | |
bc234c12 | 170 | /* |
490f2040 | 171 | * Commands additional to the ones defined in amcc-common.h |
bc234c12 | 172 | */ |
efe12bce | 173 | #define CONFIG_CMD_CHIP_CONFIG |
bc234c12 | 174 | #define CONFIG_CMD_DATE |
e3722860 | 175 | #define CONFIG_CMD_ECCTEST |
bc234c12 | 176 | #define CONFIG_CMD_PCI |
bc234c12 | 177 | #define CONFIG_CMD_SDRAM |
4745acaa SR |
178 | |
179 | #define CONFIG_IBM_EMAC4_V4 1 /* 440SPe has this EMAC version */ | |
4745acaa SR |
180 | #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ |
181 | #define CONFIG_HAS_ETH0 | |
182 | #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ | |
183 | #define CONFIG_PHY_RESET_DELAY 1000 | |
184 | #define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */ | |
185 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
4745acaa SR |
186 | |
187 | /*----------------------------------------------------------------------- | |
188 | * FLASH related | |
189 | *----------------------------------------------------------------------*/ | |
6d0f6bcf | 190 | #define CONFIG_SYS_FLASH_CFI |
00b1883a | 191 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
192 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
193 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ | |
4745acaa | 194 | |
6d0f6bcf JCPV |
195 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} |
196 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
197 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
4745acaa | 198 | |
6d0f6bcf JCPV |
199 | #undef CONFIG_SYS_FLASH_CHECKSUM |
200 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ | |
201 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
4745acaa | 202 | |
0e8d1586 | 203 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ |
6d0f6bcf | 204 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) |
0e8d1586 | 205 | #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ |
4745acaa SR |
206 | |
207 | /* Address and size of Redundant Environment Sector */ | |
0e8d1586 JCPV |
208 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) |
209 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
4745acaa SR |
210 | |
211 | /*----------------------------------------------------------------------- | |
212 | * PCI stuff | |
213 | *----------------------------------------------------------------------- | |
214 | */ | |
215 | /* General PCI */ | |
842033e6 | 216 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
4745acaa | 217 | #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ |
6efc1fc0 | 218 | #define CONFIG_PCI_CONFIG_HOST_BRIDGE |
4745acaa SR |
219 | |
220 | /* Board-specific PCI */ | |
6d0f6bcf JCPV |
221 | #define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */ |
222 | #undef CONFIG_SYS_PCI_MASTER_INIT | |
4745acaa | 223 | |
6d0f6bcf JCPV |
224 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ |
225 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ | |
226 | /* #define CONFIG_SYS_PCI_SUBSYS_ID CONFIG_SYS_PCI_SUBSYS_DEVICEID */ | |
4745acaa SR |
227 | |
228 | /* | |
229 | * NETWORK Support (PCI): | |
230 | */ | |
231 | /* Support for Intel 82557/82559/82559ER chips. */ | |
232 | #define CONFIG_EEPRO100 | |
233 | ||
234 | /*----------------------------------------------------------------------- | |
235 | * Xilinx System ACE support | |
236 | *----------------------------------------------------------------------*/ | |
237 | #define CONFIG_SYSTEMACE 1 /* Enable SystemACE support */ | |
6d0f6bcf JCPV |
238 | #define CONFIG_SYS_SYSTEMACE_WIDTH 16 /* Data bus width is 16 */ |
239 | #define CONFIG_SYS_SYSTEMACE_BASE CONFIG_SYS_ACE_BASE | |
4745acaa SR |
240 | #define CONFIG_DOS_PARTITION 1 |
241 | ||
242 | /*----------------------------------------------------------------------- | |
243 | * External Bus Controller (EBC) Setup | |
244 | *----------------------------------------------------------------------*/ | |
245 | ||
246 | /* Memory Bank 0 (Flash) initialization */ | |
6d0f6bcf | 247 | #define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \ |
4745acaa SR |
248 | EBC_BXAP_TWT_ENCODE(7) | \ |
249 | EBC_BXAP_BCE_DISABLE | \ | |
250 | EBC_BXAP_BCT_2TRANS | \ | |
251 | EBC_BXAP_CSN_ENCODE(0) | \ | |
252 | EBC_BXAP_OEN_ENCODE(0) | \ | |
253 | EBC_BXAP_WBN_ENCODE(0) | \ | |
254 | EBC_BXAP_WBF_ENCODE(0) | \ | |
255 | EBC_BXAP_TH_ENCODE(0) | \ | |
256 | EBC_BXAP_RE_DISABLED | \ | |
257 | EBC_BXAP_SOR_DELAYED | \ | |
258 | EBC_BXAP_BEM_WRITEONLY | \ | |
259 | EBC_BXAP_PEN_DISABLED) | |
6d0f6bcf | 260 | #define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \ |
4745acaa SR |
261 | EBC_BXCR_BS_16MB | \ |
262 | EBC_BXCR_BU_RW | \ | |
263 | EBC_BXCR_BW_16BIT) | |
264 | ||
265 | /* Memory Bank 1 (Xilinx System ACE controller) initialization */ | |
6d0f6bcf | 266 | #define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \ |
d2168626 SR |
267 | EBC_BXAP_TWT_ENCODE(4) | \ |
268 | EBC_BXAP_BCE_DISABLE | \ | |
269 | EBC_BXAP_BCT_2TRANS | \ | |
270 | EBC_BXAP_CSN_ENCODE(0) | \ | |
271 | EBC_BXAP_OEN_ENCODE(0) | \ | |
272 | EBC_BXAP_WBN_ENCODE(0) | \ | |
273 | EBC_BXAP_WBF_ENCODE(0) | \ | |
274 | EBC_BXAP_TH_ENCODE(0) | \ | |
275 | EBC_BXAP_RE_DISABLED | \ | |
276 | EBC_BXAP_SOR_NONDELAYED | \ | |
277 | EBC_BXAP_BEM_WRITEONLY | \ | |
278 | EBC_BXAP_PEN_DISABLED) | |
6d0f6bcf | 279 | #define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_ACE_BASE) | \ |
4745acaa SR |
280 | EBC_BXCR_BS_1MB | \ |
281 | EBC_BXCR_BU_RW | \ | |
282 | EBC_BXCR_BW_16BIT) | |
283 | ||
284 | /*------------------------------------------------------------------------- | |
285 | * Initialize EBC CONFIG - | |
286 | * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC | |
287 | * default value : 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000 | |
288 | *-------------------------------------------------------------------------*/ | |
6d0f6bcf | 289 | #define CONFIG_SYS_EBC_CFG (EBC_CFG_LE_UNLOCK | \ |
4745acaa SR |
290 | EBC_CFG_PTD_ENABLE | \ |
291 | EBC_CFG_RTC_16PERCLK | \ | |
292 | EBC_CFG_ATC_PREVIOUS | \ | |
293 | EBC_CFG_DTC_PREVIOUS | \ | |
294 | EBC_CFG_CTC_PREVIOUS | \ | |
295 | EBC_CFG_OEO_PREVIOUS | \ | |
296 | EBC_CFG_EMC_DEFAULT | \ | |
297 | EBC_CFG_PME_DISABLE | \ | |
298 | EBC_CFG_PR_16) | |
299 | ||
ba58e4c9 SR |
300 | /*----------------------------------------------------------------------- |
301 | * GPIO Setup | |
302 | *----------------------------------------------------------------------*/ | |
6d0f6bcf JCPV |
303 | #define CONFIG_SYS_GPIO_PCIE_PRESENT0 17 |
304 | #define CONFIG_SYS_GPIO_PCIE_PRESENT1 21 | |
305 | #define CONFIG_SYS_GPIO_PCIE_PRESENT2 23 | |
306 | #define CONFIG_SYS_GPIO_RS232_FORCEOFF 30 | |
307 | ||
308 | #define CONFIG_SYS_PFC0 (GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT0) | \ | |
309 | GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT1) | \ | |
310 | GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT2) | \ | |
311 | GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)) | |
312 | #define CONFIG_SYS_GPIO_OR GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF) | |
313 | #define CONFIG_SYS_GPIO_TCR GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF) | |
314 | #define CONFIG_SYS_GPIO_ODR 0 | |
ba58e4c9 | 315 | |
4745acaa | 316 | #endif /* __CONFIG_H */ |