projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| f3a8e2b7 MH |
1 | /* |
| 2 | * Copyright (C) 2015 Freescale Semiconductor | |
| 3 | * | |
| 4 | * SPDX-License-Identifier: GPL-2.0+ | |
| 5 | */ | |
| 6 | ||
| 7 | #ifndef __LS1043A_COMMON_H | |
| 8 | #define __LS1043A_COMMON_H | |
| 9 | ||
| 10 | #define CONFIG_REMAKE_ELF | |
| 11 | #define CONFIG_FSL_LAYERSCAPE | |
| 12 | #define CONFIG_FSL_LSCH2 | |
| 13 | #define CONFIG_LS1043A | |
| 831c068f | 14 | #define CONFIG_MP |
| f3a8e2b7 MH |
15 | #define CONFIG_SYS_FSL_CLK |
| 16 | #define CONFIG_GICV2 | |
| 17 | ||
| 18 | #include <asm/arch/config.h> | |
| 19 | #ifdef CONFIG_SYS_FSL_SRDS_1 | |
| 20 | #define CONFIG_SYS_HAS_SERDES | |
| 21 | #endif | |
| 22 | ||
| 23 | /* Link Definitions */ | |
| 24 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) | |
| 25 | ||
| 26 | #define CONFIG_SUPPORT_RAW_INITRD | |
| 27 | ||
| 28 | #define CONFIG_SKIP_LOWLEVEL_INIT | |
| 29 | #define CONFIG_BOARD_EARLY_INIT_F 1 | |
| 30 | ||
| 31 | /* Flat Device Tree Definitions */ | |
| f3a8e2b7 MH |
32 | #define CONFIG_OF_BOARD_SETUP |
| 33 | ||
| 34 | /* new uImage format support */ | |
| 35 | #define CONFIG_FIT | |
| 36 | #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ | |
| 37 | ||
| 38 | #ifndef CONFIG_SYS_FSL_DDR4 | |
| 39 | #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ | |
| 40 | #endif | |
| 41 | ||
| 42 | #define CONFIG_VERY_BIG_RAM | |
| 43 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 | |
| 44 | #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 | |
| 45 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
| e994dddb | 46 | #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL |
| f3a8e2b7 | 47 | |
| 831c068f HZ |
48 | #define CPU_RELEASE_ADDR secondary_boot_func |
| 49 | ||
| f3a8e2b7 MH |
50 | /* Generic Timer Definitions */ |
| 51 | #define COUNTER_FREQUENCY 25000000 /* 25MHz */ | |
| 52 | ||
| 53 | /* Size of malloc() pool */ | |
| 54 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) | |
| 55 | ||
| 56 | /* Serial Port */ | |
| 57 | #define CONFIG_CONS_INDEX 1 | |
| f3a8e2b7 MH |
58 | #define CONFIG_SYS_NS16550_SERIAL |
| 59 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
| 60 | #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)) | |
| 61 | ||
| 62 | #define CONFIG_BAUDRATE 115200 | |
| 63 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } | |
| 64 | ||
| c7ca8b07 GQ |
65 | /* SD boot SPL */ |
| 66 | #ifdef CONFIG_SD_BOOT | |
| 67 | #define CONFIG_SPL_FRAMEWORK | |
| 68 | #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" | |
| 69 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
| 70 | #define CONFIG_SPL_LIBCOMMON_SUPPORT | |
| 71 | #define CONFIG_SPL_LIBGENERIC_SUPPORT | |
| 72 | #define CONFIG_SPL_ENV_SUPPORT | |
| 73 | #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT | |
| 74 | #define CONFIG_SPL_WATCHDOG_SUPPORT | |
| 75 | #define CONFIG_SPL_I2C_SUPPORT | |
| 76 | #define CONFIG_SPL_SERIAL_SUPPORT | |
| 77 | #define CONFIG_SPL_DRIVERS_MISC_SUPPORT | |
| 78 | #define CONFIG_SPL_MMC_SUPPORT | |
| 79 | #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xf0 | |
| 80 | #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x500 | |
| 81 | ||
| 82 | #define CONFIG_SPL_TEXT_BASE 0x10000000 | |
| 83 | #define CONFIG_SPL_MAX_SIZE 0x1d000 | |
| 84 | #define CONFIG_SPL_STACK 0x1001e000 | |
| 85 | #define CONFIG_SPL_PAD_TO 0x1d000 | |
| 86 | ||
| 87 | #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ | |
| 88 | CONFIG_SYS_MONITOR_LEN) | |
| 89 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 | |
| 90 | #define CONFIG_SPL_BSS_START_ADDR 0x80100000 | |
| 91 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 | |
| 92 | #define CONFIG_SYS_MONITOR_LEN 0xa0000 | |
| 93 | #endif | |
| 94 | ||
| 3ad44729 GQ |
95 | /* NAND SPL */ |
| 96 | #ifdef CONFIG_NAND_BOOT | |
| 97 | #define CONFIG_SPL_PBL_PAD | |
| 98 | #define CONFIG_SPL_FRAMEWORK | |
| 99 | #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" | |
| 100 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
| 101 | #define CONFIG_SPL_LIBCOMMON_SUPPORT | |
| 102 | #define CONFIG_SPL_LIBGENERIC_SUPPORT | |
| 103 | #define CONFIG_SPL_ENV_SUPPORT | |
| 104 | #define CONFIG_SPL_WATCHDOG_SUPPORT | |
| 105 | #define CONFIG_SPL_I2C_SUPPORT | |
| 106 | #define CONFIG_SPL_SERIAL_SUPPORT | |
| 107 | #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT | |
| 108 | #define CONFIG_SPL_NAND_SUPPORT | |
| 109 | #define CONFIG_SPL_DRIVERS_MISC_SUPPORT | |
| 110 | #define CONFIG_SPL_TEXT_BASE 0x10000000 | |
| 111 | #define CONFIG_SPL_MAX_SIZE 0x1a000 | |
| 112 | #define CONFIG_SPL_STACK 0x1001d000 | |
| 113 | #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE | |
| 114 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE | |
| 115 | #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 | |
| 116 | #define CONFIG_SPL_BSS_START_ADDR 0x80100000 | |
| 117 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 | |
| 118 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 | |
| 119 | #define CONFIG_SYS_MONITOR_LEN 0xa0000 | |
| 120 | #endif | |
| 121 | ||
| f3a8e2b7 | 122 | /* IFC */ |
| b0f20caf | 123 | #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) |
| f3a8e2b7 MH |
124 | #define CONFIG_FSL_IFC |
| 125 | /* | |
| 126 | * CONFIG_SYS_FLASH_BASE has the final address (core view) | |
| 127 | * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) | |
| 128 | * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address | |
| 129 | * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting | |
| 130 | */ | |
| 131 | #define CONFIG_SYS_FLASH_BASE 0x60000000 | |
| 132 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE | |
| 133 | #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 | |
| 134 | ||
| 135 | #ifndef CONFIG_SYS_NO_FLASH | |
| 136 | #define CONFIG_FLASH_CFI_DRIVER | |
| 137 | #define CONFIG_SYS_FLASH_CFI | |
| 138 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
| 139 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
| 140 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
| 141 | #endif | |
| 166ef1e9 | 142 | #endif |
| f3a8e2b7 MH |
143 | |
| 144 | /* I2C */ | |
| 145 | #define CONFIG_CMD_I2C | |
| 146 | #define CONFIG_SYS_I2C | |
| 147 | #define CONFIG_SYS_I2C_MXC | |
| 148 | #define CONFIG_SYS_I2C_MXC_I2C1 | |
| 149 | #define CONFIG_SYS_I2C_MXC_I2C2 | |
| 150 | #define CONFIG_SYS_I2C_MXC_I2C3 | |
| 151 | #define CONFIG_SYS_I2C_MXC_I2C4 | |
| 152 | ||
| 153 | /* PCIe */ | |
| 154 | #define CONFIG_PCI /* Enable PCI/PCIE */ | |
| 155 | #define CONFIG_PCIE1 /* PCIE controller 1 */ | |
| 156 | #define CONFIG_PCIE2 /* PCIE controller 2 */ | |
| 157 | #define CONFIG_PCIE3 /* PCIE controller 3 */ | |
| 158 | #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ | |
| 159 | #define FSL_PCIE_COMPAT "fsl,ls1043a-pcie" | |
| 160 | ||
| 161 | #define CONFIG_SYS_PCI_64BIT | |
| 162 | ||
| 163 | #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 | |
| 164 | #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ | |
| 165 | #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 | |
| 166 | #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ | |
| 167 | ||
| 168 | #define CONFIG_SYS_PCIE_IO_BUS 0x00000000 | |
| 169 | #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 | |
| 170 | #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ | |
| 171 | ||
| 172 | #define CONFIG_SYS_PCIE_MEM_BUS 0x40000000 | |
| 173 | #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x40000000 | |
| 174 | #define CONFIG_SYS_PCIE_MEM_SIZE 0x40000000 /* 1G */ | |
| 175 | ||
| 176 | #ifdef CONFIG_PCI | |
| 177 | #define CONFIG_NET_MULTI | |
| 178 | #define CONFIG_PCI_PNP | |
| 179 | #define CONFIG_E1000 | |
| 180 | #define CONFIG_PCI_SCAN_SHOW | |
| 181 | #define CONFIG_CMD_PCI | |
| 182 | #endif | |
| 183 | ||
| 184 | /* Command line configuration */ | |
| 185 | #define CONFIG_CMD_CACHE | |
| 186 | #define CONFIG_CMD_DHCP | |
| 187 | #define CONFIG_CMD_ENV | |
| 188 | #define CONFIG_CMD_PING | |
| 189 | ||
| 8ef0d5c4 YL |
190 | /* MMC */ |
| 191 | #define CONFIG_MMC | |
| 192 | #ifdef CONFIG_MMC | |
| 193 | #define CONFIG_CMD_MMC | |
| 194 | #define CONFIG_CMD_FAT | |
| 195 | #define CONFIG_FSL_ESDHC | |
| 196 | #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 | |
| 197 | #define CONFIG_GENERIC_MMC | |
| 198 | #define CONFIG_DOS_PARTITION | |
| 199 | #endif | |
| 200 | ||
| e0579a58 GQ |
201 | /* DSPI */ |
| 202 | #define CONFIG_FSL_DSPI | |
| 203 | #ifdef CONFIG_FSL_DSPI | |
| 204 | #define CONFIG_CMD_SF | |
| 205 | #define CONFIG_DM_SPI_FLASH | |
| 206 | #define CONFIG_SPI_FLASH_STMICRO /* cs0 */ | |
| 207 | #define CONFIG_SPI_FLASH_SST /* cs1 */ | |
| 208 | #define CONFIG_SPI_FLASH_EON /* cs2 */ | |
| b0f20caf | 209 | #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) |
| e0579a58 GQ |
210 | #define CONFIG_SF_DEFAULT_BUS 1 |
| 211 | #define CONFIG_SF_DEFAULT_CS 0 | |
| 212 | #endif | |
| 166ef1e9 | 213 | #endif |
| e0579a58 | 214 | |
| ef6c55a2 AB |
215 | #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ |
| 216 | ||
| e8297341 SX |
217 | /* FMan ucode */ |
| 218 | #define CONFIG_SYS_DPAA_FMAN | |
| 219 | #ifdef CONFIG_SYS_DPAA_FMAN | |
| 220 | #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 | |
| 221 | ||
| b0f20caf | 222 | #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) |
| 166ef1e9 GQ |
223 | #define CONFIG_SYS_QE_FW_IN_SPIFLASH |
| 224 | #define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000 | |
| 225 | #define CONFIG_ENV_SPI_BUS 0 | |
| 226 | #define CONFIG_ENV_SPI_CS 0 | |
| 227 | #define CONFIG_ENV_SPI_MAX_HZ 1000000 | |
| 228 | #define CONFIG_ENV_SPI_MODE 0x03 | |
| 229 | #else | |
| e8297341 SX |
230 | #define CONFIG_SYS_QE_FMAN_FW_IN_NOR |
| 231 | /* FMan fireware Pre-load address */ | |
| 232 | #define CONFIG_SYS_FMAN_FW_ADDR 0x60300000 | |
| 166ef1e9 | 233 | #endif |
| e8297341 SX |
234 | #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 |
| 235 | #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) | |
| 236 | #endif | |
| 237 | ||
| f3a8e2b7 MH |
238 | /* Miscellaneous configurable options */ |
| 239 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) | |
| 240 | #define CONFIG_ARCH_EARLY_INIT_R | |
| 241 | #define CONFIG_BOARD_LATE_INIT | |
| 242 | ||
| 243 | #define CONFIG_HWCONFIG | |
| 244 | #define HWCONFIG_BUFFER_SIZE 128 | |
| 245 | ||
| 246 | /* Initial environment variables */ | |
| 247 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 248 | "hwconfig=fsl_ddr:bank_intlv=auto\0" \ | |
| 249 | "loadaddr=0x80100000\0" \ | |
| 250 | "kernel_addr=0x100000\0" \ | |
| 251 | "ramdisk_addr=0x800000\0" \ | |
| 252 | "ramdisk_size=0x2000000\0" \ | |
| 253 | "fdt_high=0xffffffffffffffff\0" \ | |
| 254 | "initrd_high=0xffffffffffffffff\0" \ | |
| 255 | "kernel_start=0x61200000\0" \ | |
| 256 | "kernel_load=0x807f0000\0" \ | |
| 257 | "kernel_size=0x1000000\0" \ | |
| 258 | "console=ttyAMA0,38400n8\0" | |
| 259 | ||
| 260 | #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ | |
| 261 | "earlycon=uart8250,0x21c0500,115200" | |
| 262 | #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ | |
| 263 | "$kernel_size && bootm $kernel_load" | |
| 264 | #define CONFIG_BOOTDELAY 10 | |
| 265 | ||
| 266 | /* Monitor Command Prompt */ | |
| 267 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ | |
| 268 | #define CONFIG_SYS_PROMPT "=> " | |
| 269 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
| 270 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
| 271 | #define CONFIG_SYS_HUSH_PARSER | |
| 272 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
| 273 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ | |
| 274 | #define CONFIG_SYS_LONGHELP | |
| 275 | #define CONFIG_CMDLINE_EDITING 1 | |
| 276 | #define CONFIG_AUTO_COMPLETE | |
| 277 | #define CONFIG_SYS_MAXARGS 64 /* max command args */ | |
| 278 | ||
| 279 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
| 280 | ||
| ef6c55a2 AB |
281 | /* Hash command with SHA acceleration supported in hardware */ |
| 282 | #ifdef CONFIG_FSL_CAAM | |
| 283 | #define CONFIG_CMD_HASH | |
| 284 | #define CONFIG_SHA_HW_ACCEL | |
| 285 | #endif | |
| 286 | ||
| f3a8e2b7 | 287 | #endif /* __LS1043A_COMMON_H */ |