[people/ms/u-boot.git] / include / configs / ls1043a_common.h

/*
 * Copyright (C) 2015 Freescale Semiconductor
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __LS1043A_COMMON_H
#define __LS1043A_COMMON_H

/* SPL build */
#ifdef CONFIG_SPL_BUILD
#define SPL_NO_FMAN
#define SPL_NO_DSPI
#define SPL_NO_PCIE
#define SPL_NO_ENV
#define SPL_NO_MISC
#define SPL_NO_USB
#define SPL_NO_SATA
#define SPL_NO_QE
#define SPL_NO_EEPROM
#endif
#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT))
#define SPL_NO_MMC
#endif
#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT_QSPI))
#define SPL_NO_IFC
#endif

#define CONFIG_REMAKE_ELF
#define CONFIG_FSL_LAYERSCAPE
#define CONFIG_MP
#define CONFIG_GICV2

#include <asm/arch/stream_id_lsch2.h>
#include <asm/arch/config.h>

/* Link Definitions */
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)

#define CONFIG_SUPPORT_RAW_INITRD

#define CONFIG_SKIP_LOWLEVEL_INIT

#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000
#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE      0x880000000ULL

#define CPU_RELEASE_ADDR               secondary_boot_func

/* Generic Timer Definitions */
#define COUNTER_FREQUENCY		25000000	/* 25MHz */

/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 1024 * 1024)

/* Serial Port */
#define CONFIG_CONS_INDEX		1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK          (get_serial_clock())

#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/* SD boot SPL */
#ifdef CONFIG_SD_BOOT
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"

#define CONFIG_SPL_TEXT_BASE		0x10000000
#define CONFIG_SPL_MAX_SIZE		0x17000
#define CONFIG_SPL_STACK		0x1001e000
#define CONFIG_SPL_PAD_TO		0x1d000

#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SPL_BSS_START_ADDR + \
					CONFIG_SPL_BSS_MAX_SIZE)
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
#define CONFIG_SPL_BSS_START_ADDR	0x8f000000
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000

#ifdef CONFIG_SECURE_BOOT
#define CONFIG_U_BOOT_HDR_SIZE				(16 << 10)
/*
 * HDR would be appended at end of image and copied to DDR along
 * with U-Boot image. Here u-boot max. size is 512K. So if binary
 * size increases then increase this size in case of secure boot as
 * it uses raw u-boot image instead of fit image.
 */
#define CONFIG_SYS_MONITOR_LEN		(0x100000 + CONFIG_U_BOOT_HDR_SIZE)
#else
#define CONFIG_SYS_MONITOR_LEN		0x100000
#endif /* ifdef CONFIG_SECURE_BOOT */
#endif

/* NAND SPL */
#ifdef CONFIG_NAND_BOOT
#define CONFIG_SPL_PBL_PAD
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
#define CONFIG_SPL_TEXT_BASE		0x10000000
#define CONFIG_SPL_MAX_SIZE		0x1a000
#define CONFIG_SPL_STACK		0x1001d000
#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_SPL_MALLOC_START	0x80200000
#define CONFIG_SPL_BSS_START_ADDR	0x80100000
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000

#ifdef CONFIG_SECURE_BOOT
#define CONFIG_U_BOOT_HDR_SIZE				(16 << 10)
#endif /* ifdef CONFIG_SECURE_BOOT */

#ifdef CONFIG_U_BOOT_HDR_SIZE
/*
 * HDR would be appended at end of image and copied to DDR along
 * with U-Boot image. Here u-boot max. size is 512K. So if binary
 * size increases then increase this size in case of secure boot as
 * it uses raw u-boot image instead of fit image.
 */
#define CONFIG_SYS_MONITOR_LEN		(0x100000 + CONFIG_U_BOOT_HDR_SIZE)
#else
#define CONFIG_SYS_MONITOR_LEN		0x100000
#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */

#endif

/* IFC */
#ifndef SPL_NO_IFC
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_FSL_IFC
/*
 * CONFIG_SYS_FLASH_BASE has the final address (core view)
 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
 */
#define CONFIG_SYS_FLASH_BASE			0x60000000
#define CONFIG_SYS_FLASH_BASE_PHYS		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY	0x00000000

#ifdef CONFIG_MTD_NOR_FLASH
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS	45	/* count down from 45/5: 9..1 */
#endif
#endif
#endif

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1
#define CONFIG_SYS_I2C_MXC_I2C2
#define CONFIG_SYS_I2C_MXC_I2C3
#define CONFIG_SYS_I2C_MXC_I2C4

/* PCIe */
#ifndef SPL_NO_PCIE
#define CONFIG_PCIE1		/* PCIE controller 1 */
#define CONFIG_PCIE2		/* PCIE controller 2 */
#define CONFIG_PCIE3		/* PCIE controller 3 */

#ifdef CONFIG_PCI
#define CONFIG_NET_MULTI
#define CONFIG_PCI_SCAN_SHOW
#endif
#endif

/* Command line configuration */

/*  MMC  */
#ifndef SPL_NO_MMC
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
#endif

/*  DSPI  */
#ifndef SPL_NO_DSPI
#define CONFIG_FSL_DSPI
#ifdef CONFIG_FSL_DSPI
#define CONFIG_DM_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO	/* cs0 */
#define CONFIG_SPI_FLASH_SST		/* cs1 */
#define CONFIG_SPI_FLASH_EON		/* cs2 */
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_SF_DEFAULT_BUS		1
#define CONFIG_SF_DEFAULT_CS		0
#endif
#endif
#endif

/* FMan ucode */
#ifndef SPL_NO_FMAN
#define CONFIG_SYS_DPAA_FMAN
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_FM_MURAM_SIZE	0x60000

#ifdef CONFIG_NAND_BOOT
/* Store Fman ucode at offeset 0x900000(72 blocks). */
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
#define CONFIG_SYS_FMAN_FW_ADDR		(72 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SD_BOOT)
/*
 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 * about 1MB (2040 blocks), Env is stored after the image, and the env size is
 * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 18432(0x4800).
 */
#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
#define CONFIG_SYS_FMAN_FW_ADDR		(512 * 0x4800)
#define CONFIG_SYS_QE_FW_ADDR		(512 * 0x4a08)
#elif defined(CONFIG_QSPI_BOOT)
#define CONFIG_SYS_QE_FW_IN_SPIFLASH
#define CONFIG_SYS_FMAN_FW_ADDR		0x40900000
#define CONFIG_ENV_SPI_BUS		0
#define CONFIG_ENV_SPI_CS		0
#define CONFIG_ENV_SPI_MAX_HZ		1000000
#define CONFIG_ENV_SPI_MODE		0x03
#else
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
/* FMan fireware Pre-load address */
#define CONFIG_SYS_FMAN_FW_ADDR		0x60900000
#define CONFIG_SYS_QE_FW_ADDR		0x60940000
#endif
#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#endif
#endif

/* Miscellaneous configurable options */
#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)

#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE		128

#ifndef SPL_NO_MISC
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define MTDPARTS_DEFAULT "mtdparts=spi0.0:1m(uboot)," \
			"5m(kernel),1m(dtb),9m(file_system)"
#else
#define MTDPARTS_DEFAULT "mtdparts=60000000.nor:" \
			"2m@0x100000(nor_bank0_uboot),"\
			"40m@0x1100000(nor_bank0_fit)," \
			"7m(nor_bank0_user)," \
			"2m@0x4100000(nor_bank4_uboot)," \
			"40m@0x5100000(nor_bank4_fit),"\
			"-(nor_bank4_user);" \
			"7e800000.flash:" \
			"1m(nand_uboot),1m(nand_uboot_env)," \
			"20m(nand_fit);spi0.0:1m(uboot)," \
			"5m(kernel),1m(dtb),9m(file_system)"
#endif

#include <config_distro_defaults.h>
#ifndef CONFIG_SPL_BUILD
#define BOOT_TARGET_DEVICES(func) \
	func(MMC, mmc, 0) \
	func(USB, usb, 0)
#include <config_distro_bootcmd.h>
#endif

/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
	"fdt_high=0xffffffffffffffff\0"		\
	"initrd_high=0xffffffffffffffff\0"	\
	"fdt_addr=0x64f00000\0"		 	\
	"kernel_addr=0x65000000\0"		\
	"scriptaddr=0x80000000\0"		\
	"scripthdraddr=0x80080000\0"		\
	"fdtheader_addr_r=0x80100000\0"		\
	"kernelheader_addr_r=0x80200000\0"	\
	"kernel_addr_r=0x81000000\0"		\
	"fdt_addr_r=0x90000000\0"		\
	"load_addr=0xa0000000\0"		\
	"kernel_size=0x2800000\0"		\
	"console=ttyS0,115200\0"		\
	"boot_os=y\0"				\
	"mtdparts=" MTDPARTS_DEFAULT "\0"	\
	BOOTENV					\
	"boot_scripts=ls1043ardb_boot.scr\0"	\
	"boot_script_hdr=hdr_ls1043ardb_bs.out\0"	\
	"scan_dev_for_boot_part="		\
		"part list ${devtype} ${devnum} devplist; "	\
		"env exists devplist || setenv devplist 1; "	\
		"for distro_bootpart in ${devplist}; do "	\
			"if fstype ${devtype} "			\
				"${devnum}:${distro_bootpart} "	\
				"bootfstype; then "		\
				"run scan_dev_for_boot; "	\
			"fi; "					\
		"done\0"			\
	"scan_dev_for_boot="					\
		"echo Scanning ${devtype} "			\
			"${devnum}:${distro_bootpart}...; "	\
		"for prefix in ${boot_prefixes}; do "		\
			"run scan_dev_for_scripts; "		\
		"done;\0"					\
	"boot_a_script="					\
		"load ${devtype} ${devnum}:${distro_bootpart} "	\
			"${scriptaddr} ${prefix}${script}; "	\
		"env exists secureboot && load ${devtype} "	\
			"${devnum}:${distro_bootpart} "		\
			"${scripthdraddr} ${prefix}${boot_script_hdr} "	\
			"&& esbc_validate ${scripthdraddr};"	\
		"source ${scriptaddr}\0"			\
	"installer=load mmc 0:2 $load_addr "	\
		"/flex_installer_arm64.itb; "	\
		"bootm $load_addr#ls1043ardb\0"	\
	"qspi_bootcmd=echo Trying load from qspi..;"	\
		"sf probe && sf read $load_addr "	\
		"$kernel_addr $kernel_size && bootm $load_addr#$board\0" \
	"nor_bootcmd=echo Trying load from nor..;"	\
		"cp.b $kernel_addr $load_addr "	\
		"$kernel_size && bootm $load_addr#$board\0"

#undef CONFIG_BOOTCOMMAND
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_BOOTCOMMAND "run distro_bootcmd; env exists secureboot"	\
			   "&& esbc_halt; run qspi_bootcmd;"
#else
#define CONFIG_BOOTCOMMAND "run distro_bootcmd; env exists secureboot"	\
			   "&& esbc_halt; run nor_bootcmd;"
#endif
#endif

/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
#define CONFIG_SYS_LONGHELP

#ifndef SPL_NO_MISC
#ifndef CONFIG_CMDLINE_EDITING
#define CONFIG_CMDLINE_EDITING		1
#endif
#endif

#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_MAXARGS		64	/* max command args */

#define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */

#include <asm/arch/soc.h>

#endif /* __LS1043A_COMMON_H */
Commit	Line	Data
f3a8e2b7 MH	1	/*
	2	* Copyright (C) 2015 Freescale Semiconductor
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#ifndef __LS1043A_COMMON_H
	8	#define __LS1043A_COMMON_H
	9
4139b170 SG	10	/* SPL build */
	11	#ifdef CONFIG_SPL_BUILD
	12	#define SPL_NO_FMAN
	13	#define SPL_NO_DSPI
	14	#define SPL_NO_PCIE
	15	#define SPL_NO_ENV
	16	#define SPL_NO_MISC
	17	#define SPL_NO_USB
	18	#define SPL_NO_SATA
	19	#define SPL_NO_QE
	20	#define SPL_NO_EEPROM
	21	#endif
	22	#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT))
	23	#define SPL_NO_MMC
	24	#endif
3c7d647e	25	#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT_QSPI))
4139b170 SG	26	#define SPL_NO_IFC
	27	#endif
	28
f3a8e2b7 MH	29	#define CONFIG_REMAKE_ELF
f3a8e2b7 MH	30	#define CONFIG_FSL_LAYERSCAPE
831c068f	31	#define CONFIG_MP
f3a8e2b7 MH	32	#define CONFIG_GICV2
f3a8e2b7 MH	33
5344c7b7	34	#include <asm/arch/stream_id_lsch2.h>
f3a8e2b7	35	#include <asm/arch/config.h>
f3a8e2b7 MH	36
	37	/* Link Definitions */
	38	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
	39
	40	#define CONFIG_SUPPORT_RAW_INITRD
	41
	42	#define CONFIG_SKIP_LOWLEVEL_INIT
f3a8e2b7	43
f3a8e2b7 MH	44	#define CONFIG_VERY_BIG_RAM
	45	#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
	46	#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
	47	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
e994dddb	48	#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
f3a8e2b7	49
831c068f HZ	50	#define CPU_RELEASE_ADDR secondary_boot_func
831c068f HZ	51
f3a8e2b7 MH	52	/* Generic Timer Definitions */
	53	#define COUNTER_FREQUENCY 25000000 /* 25MHz */
	54
	55	/* Size of malloc() pool */
	56	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
	57
	58	/* Serial Port */
	59	#define CONFIG_CONS_INDEX 1
f3a8e2b7 MH	60	#define CONFIG_SYS_NS16550_SERIAL
f3a8e2b7 MH	61	#define CONFIG_SYS_NS16550_REG_SIZE 1
904110c7	62	#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
f3a8e2b7	63
f3a8e2b7 MH	64	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
f3a8e2b7 MH	65
c7ca8b07 GQ	66	/* SD boot SPL */
	67	#ifdef CONFIG_SD_BOOT
	68	#define CONFIG_SPL_FRAMEWORK
c7ca8b07	69	#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
c7ca8b07 GQ	70
c7ca8b07 GQ	71	#define CONFIG_SPL_TEXT_BASE 0x10000000
70f9661c	72	#define CONFIG_SPL_MAX_SIZE 0x17000
c7ca8b07 GQ	73	#define CONFIG_SPL_STACK 0x1001e000
	74	#define CONFIG_SPL_PAD_TO 0x1d000
	75
23af484b YS	76	#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
23af484b YS	77	CONFIG_SPL_BSS_MAX_SIZE)
c7ca8b07	78	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
23af484b	79	#define CONFIG_SPL_BSS_START_ADDR 0x8f000000
c7ca8b07	80	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
70f9661c RG	81
	82	#ifdef CONFIG_SECURE_BOOT
	83	#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
	84	/*
	85	* HDR would be appended at end of image and copied to DDR along
	86	* with U-Boot image. Here u-boot max. size is 512K. So if binary
	87	* size increases then increase this size in case of secure boot as
	88	* it uses raw u-boot image instead of fit image.
	89	*/
	90	#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
	91	#else
	92	#define CONFIG_SYS_MONITOR_LEN 0x100000
	93	#endif /* ifdef CONFIG_SECURE_BOOT */
c7ca8b07 GQ	94	#endif
c7ca8b07 GQ	95
3ad44729 GQ	96	/* NAND SPL */
	97	#ifdef CONFIG_NAND_BOOT
	98	#define CONFIG_SPL_PBL_PAD
	99	#define CONFIG_SPL_FRAMEWORK
3ad44729	100	#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
3ad44729 GQ	101	#define CONFIG_SPL_TEXT_BASE 0x10000000
	102	#define CONFIG_SPL_MAX_SIZE 0x1a000
	103	#define CONFIG_SPL_STACK 0x1001d000
	104	#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
	105	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
	106	#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
	107	#define CONFIG_SPL_BSS_START_ADDR 0x80100000
	108	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
	109	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
762f92a6 RG	110
	111	#ifdef CONFIG_SECURE_BOOT
	112	#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
	113	#endif /* ifdef CONFIG_SECURE_BOOT */
	114
	115	#ifdef CONFIG_U_BOOT_HDR_SIZE
	116	/*
	117	* HDR would be appended at end of image and copied to DDR along
	118	* with U-Boot image. Here u-boot max. size is 512K. So if binary
	119	* size increases then increase this size in case of secure boot as
	120	* it uses raw u-boot image instead of fit image.
	121	*/
	122	#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
	123	#else
	124	#define CONFIG_SYS_MONITOR_LEN 0x100000
	125	#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
	126
3ad44729 GQ	127	#endif
3ad44729 GQ	128
f3a8e2b7	129	/* IFC */
4139b170	130	#ifndef SPL_NO_IFC
b0f20caf	131	#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
f3a8e2b7 MH	132	#define CONFIG_FSL_IFC
	133	/*
	134	* CONFIG_SYS_FLASH_BASE has the final address (core view)
	135	* CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
	136	* CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
	137	* CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
	138	*/
	139	#define CONFIG_SYS_FLASH_BASE 0x60000000
	140	#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
	141	#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
	142
e856bdcf	143	#ifdef CONFIG_MTD_NOR_FLASH
f3a8e2b7 MH	144	#define CONFIG_FLASH_CFI_DRIVER
	145	#define CONFIG_SYS_FLASH_CFI
	146	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
	147	#define CONFIG_SYS_FLASH_QUIET_TEST
	148	#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
	149	#endif
166ef1e9	150	#endif
4139b170	151	#endif
f3a8e2b7 MH	152
f3a8e2b7 MH	153	/* I2C */
f3a8e2b7 MH	154	#define CONFIG_SYS_I2C
	155	#define CONFIG_SYS_I2C_MXC
	156	#define CONFIG_SYS_I2C_MXC_I2C1
	157	#define CONFIG_SYS_I2C_MXC_I2C2
	158	#define CONFIG_SYS_I2C_MXC_I2C3
	159	#define CONFIG_SYS_I2C_MXC_I2C4
	160
	161	/* PCIe */
4139b170	162	#ifndef SPL_NO_PCIE
f3a8e2b7 MH	163	#define CONFIG_PCIE1 /* PCIE controller 1 */
	164	#define CONFIG_PCIE2 /* PCIE controller 2 */
	165	#define CONFIG_PCIE3 /* PCIE controller 3 */
f3a8e2b7	166
f3a8e2b7 MH	167	#ifdef CONFIG_PCI
f3a8e2b7 MH	168	#define CONFIG_NET_MULTI
f3a8e2b7	169	#define CONFIG_PCI_SCAN_SHOW
f3a8e2b7	170	#endif
4139b170	171	#endif
f3a8e2b7 MH	172
f3a8e2b7 MH	173	/* Command line configuration */
f3a8e2b7	174
8ef0d5c4	175	/* MMC */
4139b170	176	#ifndef SPL_NO_MMC
8ef0d5c4	177	#ifdef CONFIG_MMC
8ef0d5c4 YL	178	#define CONFIG_FSL_ESDHC
8ef0d5c4 YL	179	#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
8ef0d5c4	180	#endif
4139b170	181	#endif
8ef0d5c4	182
e0579a58	183	/* DSPI */
4139b170	184	#ifndef SPL_NO_DSPI
e0579a58 GQ	185	#define CONFIG_FSL_DSPI
e0579a58 GQ	186	#ifdef CONFIG_FSL_DSPI
e0579a58 GQ	187	#define CONFIG_DM_SPI_FLASH
	188	#define CONFIG_SPI_FLASH_STMICRO /* cs0 */
	189	#define CONFIG_SPI_FLASH_SST /* cs1 */
	190	#define CONFIG_SPI_FLASH_EON /* cs2 */
b0f20caf	191	#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
e0579a58 GQ	192	#define CONFIG_SF_DEFAULT_BUS 1
	193	#define CONFIG_SF_DEFAULT_CS 0
	194	#endif
166ef1e9	195	#endif
4139b170	196	#endif
e0579a58	197
e8297341	198	/* FMan ucode */
4139b170	199	#ifndef SPL_NO_FMAN
e8297341 SX	200	#define CONFIG_SYS_DPAA_FMAN
	201	#ifdef CONFIG_SYS_DPAA_FMAN
	202	#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
	203
fd1b147c	204	#ifdef CONFIG_NAND_BOOT
a9a5cef3	205	/* Store Fman ucode at offeset 0x900000(72 blocks). */
fd1b147c	206	#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
a9a5cef3	207	#define CONFIG_SYS_FMAN_FW_ADDR (72 * CONFIG_SYS_NAND_BLOCK_SIZE)
2a555839 QG	208	#elif defined(CONFIG_SD_BOOT)
	209	/*
	210	* PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
	211	* about 1MB (2040 blocks), Env is stored after the image, and the env size is
a9a5cef3	212	* 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 18432(0x4800).
2a555839 QG	213	*/
2a555839 QG	214	#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
a9a5cef3	215	#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800)
5aa03ddd	216	#define CONFIG_SYS_QE_FW_ADDR (512 * 0x4a08)
2a555839	217	#elif defined(CONFIG_QSPI_BOOT)
166ef1e9	218	#define CONFIG_SYS_QE_FW_IN_SPIFLASH
a9a5cef3	219	#define CONFIG_SYS_FMAN_FW_ADDR 0x40900000
166ef1e9 GQ	220	#define CONFIG_ENV_SPI_BUS 0
	221	#define CONFIG_ENV_SPI_CS 0
	222	#define CONFIG_ENV_SPI_MAX_HZ 1000000
	223	#define CONFIG_ENV_SPI_MODE 0x03
	224	#else
e8297341 SX	225	#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
e8297341 SX	226	/* FMan fireware Pre-load address */
a9a5cef3	227	#define CONFIG_SYS_FMAN_FW_ADDR 0x60900000
5aa03ddd	228	#define CONFIG_SYS_QE_FW_ADDR 0x60940000
166ef1e9	229	#endif
e8297341 SX	230	#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
	231	#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
	232	#endif
4139b170	233	#endif
e8297341	234
f3a8e2b7 MH	235	/* Miscellaneous configurable options */
f3a8e2b7 MH	236	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
f3a8e2b7 MH	237
	238	#define CONFIG_HWCONFIG
	239	#define HWCONFIG_BUFFER_SIZE 128
	240
4139b170	241	#ifndef SPL_NO_MISC
dbe18f16 WS	242	#if defined(CONFIG_QSPI_BOOT) \|\| defined(CONFIG_SD_BOOT_QSPI)
	243	#define MTDPARTS_DEFAULT "mtdparts=spi0.0:1m(uboot)," \
	244	"5m(kernel),1m(dtb),9m(file_system)"
	245	#else
7f339632 WS	246	#define MTDPARTS_DEFAULT "mtdparts=60000000.nor:" \
	247	"2m@0x100000(nor_bank0_uboot),"\
	248	"40m@0x1100000(nor_bank0_fit)," \
	249	"7m(nor_bank0_user)," \
	250	"2m@0x4100000(nor_bank4_uboot)," \
	251	"40m@0x5100000(nor_bank4_fit),"\
	252	"-(nor_bank4_user);" \
	253	"7e800000.flash:" \
dbe18f16 WS	254	"1m(nand_uboot),1m(nand_uboot_env)," \
	255	"20m(nand_fit);spi0.0:1m(uboot)," \
	256	"5m(kernel),1m(dtb),9m(file_system)"
	257	#endif
	258
5ba909f4 SL	259	#include <config_distro_defaults.h>
	260	#ifndef CONFIG_SPL_BUILD
	261	#define BOOT_TARGET_DEVICES(func) \
	262	func(MMC, mmc, 0) \
	263	func(USB, usb, 0)
	264	#include <config_distro_bootcmd.h>
	265	#endif
	266
f3a8e2b7 MH	267	/* Initial environment variables */
	268	#define CONFIG_EXTRA_ENV_SETTINGS \
	269	"hwconfig=fsl_ddr:bank_intlv=auto\0" \
f3a8e2b7 MH	270	"fdt_high=0xffffffffffffffff\0" \
f3a8e2b7 MH	271	"initrd_high=0xffffffffffffffff\0" \
5ba909f4 SL	272	"fdt_addr=0x64f00000\0" \
	273	"kernel_addr=0x65000000\0" \
	274	"scriptaddr=0x80000000\0" \
76bbf1c6	275	"scripthdraddr=0x80080000\0" \
5ba909f4 SL	276	"fdtheader_addr_r=0x80100000\0" \
	277	"kernelheader_addr_r=0x80200000\0" \
	278	"kernel_addr_r=0x81000000\0" \
	279	"fdt_addr_r=0x90000000\0" \
	280	"load_addr=0xa0000000\0" \
ad6767b6	281	"kernel_size=0x2800000\0" \
5ba909f4	282	"console=ttyS0,115200\0" \
23af484b	283	"boot_os=y\0" \
5ba909f4 SL	284	"mtdparts=" MTDPARTS_DEFAULT "\0" \
	285	BOOTENV \
	286	"boot_scripts=ls1043ardb_boot.scr\0" \
76bbf1c6	287	"boot_script_hdr=hdr_ls1043ardb_bs.out\0" \
5ba909f4 SL	288	"scan_dev_for_boot_part=" \
	289	"part list ${devtype} ${devnum} devplist; " \
	290	"env exists devplist \|\| setenv devplist 1; " \
	291	"for distro_bootpart in ${devplist}; do " \
	292	"if fstype ${devtype} " \
	293	"${devnum}:${distro_bootpart} " \
	294	"bootfstype; then " \
	295	"run scan_dev_for_boot; " \
	296	"fi; " \
	297	"done\0" \
76bbf1c6 SG	298	"scan_dev_for_boot=" \
	299	"echo Scanning ${devtype} " \
	300	"${devnum}:${distro_bootpart}...; " \
	301	"for prefix in ${boot_prefixes}; do " \
	302	"run scan_dev_for_scripts; " \
	303	"done;\0" \
	304	"boot_a_script=" \
	305	"load ${devtype} ${devnum}:${distro_bootpart} " \
	306	"${scriptaddr} ${prefix}${script}; " \
	307	"env exists secureboot && load ${devtype} " \
	308	"${devnum}:${distro_bootpart} " \
	309	"${scripthdraddr} ${prefix}${boot_script_hdr} " \
	310	"&& esbc_validate ${scripthdraddr};" \
	311	"source ${scriptaddr}\0" \
5ba909f4 SL	312	"installer=load mmc 0:2 $load_addr " \
	313	"/flex_installer_arm64.itb; " \
	314	"bootm $load_addr#ls1043ardb\0" \
	315	"qspi_bootcmd=echo Trying load from qspi..;" \
	316	"sf probe && sf read $load_addr " \
	317	"$kernel_addr $kernel_size && bootm $load_addr#$board\0" \
	318	"nor_bootcmd=echo Trying load from nor..;" \
	319	"cp.b $kernel_addr $load_addr " \
	320	"$kernel_size && bootm $load_addr#$board\0"
	321
	322	#undef CONFIG_BOOTCOMMAND
	323	#if defined(CONFIG_QSPI_BOOT) \|\| defined(CONFIG_SD_BOOT_QSPI)
76bbf1c6 SG	324	#define CONFIG_BOOTCOMMAND "run distro_bootcmd; env exists secureboot" \
76bbf1c6 SG	325	"&& esbc_halt; run qspi_bootcmd;"
5ba909f4	326	#else
76bbf1c6 SG	327	#define CONFIG_BOOTCOMMAND "run distro_bootcmd; env exists secureboot" \
76bbf1c6 SG	328	"&& esbc_halt; run nor_bootcmd;"
5ba909f4	329	#endif
4139b170	330	#endif
f3a8e2b7 MH	331
	332	/* Monitor Command Prompt */
	333	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
f3a8e2b7	334	#define CONFIG_SYS_LONGHELP
4139b170 SG	335
4139b170 SG	336	#ifndef SPL_NO_MISC
5ba909f4	337	#ifndef CONFIG_CMDLINE_EDITING
f3a8e2b7	338	#define CONFIG_CMDLINE_EDITING 1
4139b170	339	#endif
5ba909f4	340	#endif
4139b170	341
f3a8e2b7 MH	342	#define CONFIG_AUTO_COMPLETE
	343	#define CONFIG_SYS_MAXARGS 64 /* max command args */
	344
	345	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
	346
457e51cf SG	347	#include <asm/arch/soc.h>
457e51cf SG	348
f3a8e2b7	349	#endif /* __LS1043A_COMMON_H */