[people/ms/u-boot.git] / include / configs / ls1043a_common.h

/*
 * Copyright (C) 2015 Freescale Semiconductor
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __LS1043A_COMMON_H
#define __LS1043A_COMMON_H

#define CONFIG_REMAKE_ELF
#define CONFIG_FSL_LAYERSCAPE
#define CONFIG_LS1043A
#define CONFIG_MP
#define CONFIG_GICV2

#include <asm/arch/stream_id_lsch2.h>
#include <asm/arch/config.h>

/* Link Definitions */
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)

#define CONFIG_SUPPORT_RAW_INITRD

#define CONFIG_SKIP_LOWLEVEL_INIT

#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000
#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE      0x880000000ULL

#define CPU_RELEASE_ADDR               secondary_boot_func

/* Generic Timer Definitions */
#define COUNTER_FREQUENCY		25000000	/* 25MHz */

/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 1024 * 1024)

/* Serial Port */
#define CONFIG_CONS_INDEX		1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK          (get_serial_clock())

#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/* SD boot SPL */
#ifdef CONFIG_SD_BOOT
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_LDSCRIPT		"arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"

#define CONFIG_SPL_TEXT_BASE		0x10000000
#define CONFIG_SPL_MAX_SIZE		0x1d000
#define CONFIG_SPL_STACK		0x1001e000
#define CONFIG_SPL_PAD_TO		0x1d000

#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_TEXT_BASE + \
					CONFIG_SYS_MONITOR_LEN)
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
#define CONFIG_SPL_BSS_START_ADDR	0x80100000
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
#define CONFIG_SYS_MONITOR_LEN		0xa0000
#endif

/* NAND SPL */
#ifdef CONFIG_NAND_BOOT
#define CONFIG_SPL_PBL_PAD
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_LDSCRIPT		"arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
#define CONFIG_SPL_TEXT_BASE		0x10000000
#define CONFIG_SPL_MAX_SIZE		0x1a000
#define CONFIG_SPL_STACK		0x1001d000
#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_SPL_MALLOC_START	0x80200000
#define CONFIG_SPL_BSS_START_ADDR	0x80100000
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
#define CONFIG_SYS_MONITOR_LEN		0xa0000
#endif

/* IFC */
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_FSL_IFC
/*
 * CONFIG_SYS_FLASH_BASE has the final address (core view)
 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
 */
#define CONFIG_SYS_FLASH_BASE			0x60000000
#define CONFIG_SYS_FLASH_BASE_PHYS		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY	0x00000000

#ifdef CONFIG_MTD_NOR_FLASH
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS	45	/* count down from 45/5: 9..1 */
#endif
#endif

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1
#define CONFIG_SYS_I2C_MXC_I2C2
#define CONFIG_SYS_I2C_MXC_I2C3
#define CONFIG_SYS_I2C_MXC_I2C4

/* PCIe */
#define CONFIG_PCIE1		/* PCIE controller 1 */
#define CONFIG_PCIE2		/* PCIE controller 2 */
#define CONFIG_PCIE3		/* PCIE controller 3 */

#ifdef CONFIG_PCI
#define CONFIG_NET_MULTI
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_CMD_PCI
#endif

/* Command line configuration */
#define CONFIG_CMD_ENV

/*  MMC  */
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif

/*  DSPI  */
#define CONFIG_FSL_DSPI
#ifdef CONFIG_FSL_DSPI
#define CONFIG_DM_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO	/* cs0 */
#define CONFIG_SPI_FLASH_SST		/* cs1 */
#define CONFIG_SPI_FLASH_EON		/* cs2 */
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_SF_DEFAULT_BUS		1
#define CONFIG_SF_DEFAULT_CS		0
#endif
#endif

/* FMan ucode */
#define CONFIG_SYS_DPAA_FMAN
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_FM_MURAM_SIZE	0x60000

#ifdef CONFIG_NAND_BOOT
/* Store Fman ucode at offeset 0x160000(11 blocks). */
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
#define CONFIG_SYS_FMAN_FW_ADDR		(11 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SD_BOOT)
/*
 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 * about 1MB (2040 blocks), Env is stored after the image, and the env size is
 * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 2080(0x820).
 */
#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
#define CONFIG_SYS_FMAN_FW_ADDR		(512 * 0x820)
#elif defined(CONFIG_QSPI_BOOT)
#define CONFIG_SYS_QE_FW_IN_SPIFLASH
#define CONFIG_SYS_FMAN_FW_ADDR		0x400d0000
#define CONFIG_ENV_SPI_BUS		0
#define CONFIG_ENV_SPI_CS		0
#define CONFIG_ENV_SPI_MAX_HZ		1000000
#define CONFIG_ENV_SPI_MODE		0x03
#else
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
/* FMan fireware Pre-load address */
#define CONFIG_SYS_FMAN_FW_ADDR		0x60300000
#endif
#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#endif

/* Miscellaneous configurable options */
#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)

#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE		128

#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define MTDPARTS_DEFAULT "mtdparts=spi0.0:1m(uboot)," \
			"5m(kernel),1m(dtb),9m(file_system)"
#else
#define MTDPARTS_DEFAULT "mtdparts=60000000.nor:" \
			"2m@0x100000(nor_bank0_uboot),"\
			"40m@0x1100000(nor_bank0_fit)," \
			"7m(nor_bank0_user)," \
			"2m@0x4100000(nor_bank4_uboot)," \
			"40m@0x5100000(nor_bank4_fit),"\
			"-(nor_bank4_user);" \
			"7e800000.flash:" \
			"1m(nand_uboot),1m(nand_uboot_env)," \
			"20m(nand_fit);spi0.0:1m(uboot)," \
			"5m(kernel),1m(dtb),9m(file_system)"
#endif

/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
	"loadaddr=0x80100000\0"			\
	"fdt_high=0xffffffffffffffff\0"		\
	"initrd_high=0xffffffffffffffff\0"	\
	"kernel_start=0x61100000\0"		\
	"kernel_load=0xa0000000\0"		\
	"kernel_size=0x2800000\0"		\
	"console=ttyS0,115200\0"                \
	"mtdparts=" MTDPARTS_DEFAULT "\0"

#define CONFIG_BOOTARGS			"console=ttyS0,115200 root=/dev/ram0 " \
					"earlycon=uart8250,mmio,0x21c0500 "    \
					MTDPARTS_DEFAULT

#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_BOOTCOMMAND		"sf probe && sf read $kernel_load "    \
					"e0000 f00000 && bootm $kernel_load"
#else
#define CONFIG_BOOTCOMMAND		"cp.b $kernel_start $kernel_load "     \
					"$kernel_size && bootm $kernel_load"
#endif

/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot args buffer */
#define CONFIG_SYS_LONGHELP
#define CONFIG_CMDLINE_EDITING		1
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_MAXARGS		64	/* max command args */

#define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */

/* Hash command with SHA acceleration supported in hardware */
#ifdef CONFIG_FSL_CAAM
#define CONFIG_CMD_HASH
#define CONFIG_SHA_HW_ACCEL
#endif

#endif /* __LS1043A_COMMON_H */
Commit	Line	Data
f3a8e2b7 MH	1	/*
	2	* Copyright (C) 2015 Freescale Semiconductor
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#ifndef __LS1043A_COMMON_H
	8	#define __LS1043A_COMMON_H
	9
	10	#define CONFIG_REMAKE_ELF
	11	#define CONFIG_FSL_LAYERSCAPE
f3a8e2b7	12	#define CONFIG_LS1043A
831c068f	13	#define CONFIG_MP
f3a8e2b7 MH	14	#define CONFIG_GICV2
f3a8e2b7 MH	15
5344c7b7	16	#include <asm/arch/stream_id_lsch2.h>
f3a8e2b7	17	#include <asm/arch/config.h>
f3a8e2b7 MH	18
	19	/* Link Definitions */
	20	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
	21
	22	#define CONFIG_SUPPORT_RAW_INITRD
	23
	24	#define CONFIG_SKIP_LOWLEVEL_INIT
f3a8e2b7	25
f3a8e2b7 MH	26	#define CONFIG_VERY_BIG_RAM
	27	#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
	28	#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
	29	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
e994dddb	30	#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
f3a8e2b7	31
831c068f HZ	32	#define CPU_RELEASE_ADDR secondary_boot_func
831c068f HZ	33
f3a8e2b7 MH	34	/* Generic Timer Definitions */
	35	#define COUNTER_FREQUENCY 25000000 /* 25MHz */
	36
	37	/* Size of malloc() pool */
	38	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
	39
	40	/* Serial Port */
	41	#define CONFIG_CONS_INDEX 1
f3a8e2b7 MH	42	#define CONFIG_SYS_NS16550_SERIAL
f3a8e2b7 MH	43	#define CONFIG_SYS_NS16550_REG_SIZE 1
904110c7	44	#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
f3a8e2b7	45
f3a8e2b7 MH	46	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
f3a8e2b7 MH	47
c7ca8b07 GQ	48	/* SD boot SPL */
	49	#ifdef CONFIG_SD_BOOT
	50	#define CONFIG_SPL_FRAMEWORK
	51	#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
	52	#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
c7ca8b07 GQ	53
	54	#define CONFIG_SPL_TEXT_BASE 0x10000000
	55	#define CONFIG_SPL_MAX_SIZE 0x1d000
	56	#define CONFIG_SPL_STACK 0x1001e000
	57	#define CONFIG_SPL_PAD_TO 0x1d000
	58
	59	#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
	60	CONFIG_SYS_MONITOR_LEN)
	61	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
	62	#define CONFIG_SPL_BSS_START_ADDR 0x80100000
	63	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
	64	#define CONFIG_SYS_MONITOR_LEN 0xa0000
	65	#endif
	66
3ad44729 GQ	67	/* NAND SPL */
	68	#ifdef CONFIG_NAND_BOOT
	69	#define CONFIG_SPL_PBL_PAD
	70	#define CONFIG_SPL_FRAMEWORK
	71	#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
	72	#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
3ad44729 GQ	73	#define CONFIG_SPL_TEXT_BASE 0x10000000
	74	#define CONFIG_SPL_MAX_SIZE 0x1a000
	75	#define CONFIG_SPL_STACK 0x1001d000
	76	#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
	77	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
	78	#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
	79	#define CONFIG_SPL_BSS_START_ADDR 0x80100000
	80	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
	81	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
	82	#define CONFIG_SYS_MONITOR_LEN 0xa0000
	83	#endif
	84
f3a8e2b7	85	/* IFC */
b0f20caf	86	#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
f3a8e2b7 MH	87	#define CONFIG_FSL_IFC
	88	/*
	89	* CONFIG_SYS_FLASH_BASE has the final address (core view)
	90	* CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
	91	* CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
	92	* CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
	93	*/
	94	#define CONFIG_SYS_FLASH_BASE 0x60000000
	95	#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
	96	#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
	97
e856bdcf	98	#ifdef CONFIG_MTD_NOR_FLASH
f3a8e2b7 MH	99	#define CONFIG_FLASH_CFI_DRIVER
	100	#define CONFIG_SYS_FLASH_CFI
	101	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
	102	#define CONFIG_SYS_FLASH_QUIET_TEST
	103	#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
	104	#endif
166ef1e9	105	#endif
f3a8e2b7 MH	106
f3a8e2b7 MH	107	/* I2C */
f3a8e2b7 MH	108	#define CONFIG_SYS_I2C
	109	#define CONFIG_SYS_I2C_MXC
	110	#define CONFIG_SYS_I2C_MXC_I2C1
	111	#define CONFIG_SYS_I2C_MXC_I2C2
	112	#define CONFIG_SYS_I2C_MXC_I2C3
	113	#define CONFIG_SYS_I2C_MXC_I2C4
	114
	115	/* PCIe */
f3a8e2b7 MH	116	#define CONFIG_PCIE1 /* PCIE controller 1 */
	117	#define CONFIG_PCIE2 /* PCIE controller 2 */
	118	#define CONFIG_PCIE3 /* PCIE controller 3 */
f3a8e2b7	119
f3a8e2b7 MH	120	#ifdef CONFIG_PCI
f3a8e2b7 MH	121	#define CONFIG_NET_MULTI
f3a8e2b7 MH	122	#define CONFIG_PCI_SCAN_SHOW
	123	#define CONFIG_CMD_PCI
	124	#endif
	125
	126	/* Command line configuration */
f3a8e2b7	127	#define CONFIG_CMD_ENV
f3a8e2b7	128
8ef0d5c4	129	/* MMC */
8ef0d5c4	130	#ifdef CONFIG_MMC
8ef0d5c4 YL	131	#define CONFIG_FSL_ESDHC
8ef0d5c4 YL	132	#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
8ef0d5c4 YL	133	#endif
8ef0d5c4 YL	134
e0579a58 GQ	135	/* DSPI */
	136	#define CONFIG_FSL_DSPI
	137	#ifdef CONFIG_FSL_DSPI
e0579a58 GQ	138	#define CONFIG_DM_SPI_FLASH
	139	#define CONFIG_SPI_FLASH_STMICRO /* cs0 */
	140	#define CONFIG_SPI_FLASH_SST /* cs1 */
	141	#define CONFIG_SPI_FLASH_EON /* cs2 */
b0f20caf	142	#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
e0579a58 GQ	143	#define CONFIG_SF_DEFAULT_BUS 1
	144	#define CONFIG_SF_DEFAULT_CS 0
	145	#endif
166ef1e9	146	#endif
e0579a58	147
e8297341 SX	148	/* FMan ucode */
	149	#define CONFIG_SYS_DPAA_FMAN
	150	#ifdef CONFIG_SYS_DPAA_FMAN
	151	#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
	152
fd1b147c QG	153	#ifdef CONFIG_NAND_BOOT
	154	/* Store Fman ucode at offeset 0x160000(11 blocks). */
	155	#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
	156	#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
2a555839 QG	157	#elif defined(CONFIG_SD_BOOT)
	158	/*
	159	* PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
	160	* about 1MB (2040 blocks), Env is stored after the image, and the env size is
	161	* 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 2080(0x820).
	162	*/
	163	#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
	164	#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
	165	#elif defined(CONFIG_QSPI_BOOT)
166ef1e9 GQ	166	#define CONFIG_SYS_QE_FW_IN_SPIFLASH
	167	#define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000
	168	#define CONFIG_ENV_SPI_BUS 0
	169	#define CONFIG_ENV_SPI_CS 0
	170	#define CONFIG_ENV_SPI_MAX_HZ 1000000
	171	#define CONFIG_ENV_SPI_MODE 0x03
	172	#else
e8297341 SX	173	#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
	174	/* FMan fireware Pre-load address */
	175	#define CONFIG_SYS_FMAN_FW_ADDR 0x60300000
166ef1e9	176	#endif
e8297341 SX	177	#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
	178	#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
	179	#endif
	180
f3a8e2b7 MH	181	/* Miscellaneous configurable options */
f3a8e2b7 MH	182	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
f3a8e2b7 MH	183
	184	#define CONFIG_HWCONFIG
	185	#define HWCONFIG_BUFFER_SIZE 128
	186
dbe18f16 WS	187	#if defined(CONFIG_QSPI_BOOT) \|\| defined(CONFIG_SD_BOOT_QSPI)
	188	#define MTDPARTS_DEFAULT "mtdparts=spi0.0:1m(uboot)," \
	189	"5m(kernel),1m(dtb),9m(file_system)"
	190	#else
7f339632 WS	191	#define MTDPARTS_DEFAULT "mtdparts=60000000.nor:" \
	192	"2m@0x100000(nor_bank0_uboot),"\
	193	"40m@0x1100000(nor_bank0_fit)," \
	194	"7m(nor_bank0_user)," \
	195	"2m@0x4100000(nor_bank4_uboot)," \
	196	"40m@0x5100000(nor_bank4_fit),"\
	197	"-(nor_bank4_user);" \
	198	"7e800000.flash:" \
dbe18f16 WS	199	"1m(nand_uboot),1m(nand_uboot_env)," \
	200	"20m(nand_fit);spi0.0:1m(uboot)," \
	201	"5m(kernel),1m(dtb),9m(file_system)"
	202	#endif
	203
f3a8e2b7 MH	204	/* Initial environment variables */
	205	#define CONFIG_EXTRA_ENV_SETTINGS \
	206	"hwconfig=fsl_ddr:bank_intlv=auto\0" \
	207	"loadaddr=0x80100000\0" \
f3a8e2b7 MH	208	"fdt_high=0xffffffffffffffff\0" \
f3a8e2b7 MH	209	"initrd_high=0xffffffffffffffff\0" \
ad6767b6 QG	210	"kernel_start=0x61100000\0" \
	211	"kernel_load=0xa0000000\0" \
	212	"kernel_size=0x2800000\0" \
dbe18f16 WS	213	"console=ttyS0,115200\0" \
dbe18f16 WS	214	"mtdparts=" MTDPARTS_DEFAULT "\0"
f3a8e2b7 MH	215
f3a8e2b7 MH	216	#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
dbe18f16 WS	217	"earlycon=uart8250,mmio,0x21c0500 " \
	218	MTDPARTS_DEFAULT
	219
1297cdb4 QG	220	#if defined(CONFIG_QSPI_BOOT) \|\| defined(CONFIG_SD_BOOT_QSPI)
	221	#define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load " \
	222	"e0000 f00000 && bootm $kernel_load"
	223	#else
f3a8e2b7 MH	224	#define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \
f3a8e2b7 MH	225	"$kernel_size && bootm $kernel_load"
1297cdb4	226	#endif
f3a8e2b7 MH	227
	228	/* Monitor Command Prompt */
	229	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
f3a8e2b7 MH	230	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
f3a8e2b7 MH	231	sizeof(CONFIG_SYS_PROMPT) + 16)
f3a8e2b7 MH	232	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
	233	#define CONFIG_SYS_LONGHELP
	234	#define CONFIG_CMDLINE_EDITING 1
	235	#define CONFIG_AUTO_COMPLETE
	236	#define CONFIG_SYS_MAXARGS 64 /* max command args */
	237
	238	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
	239
ef6c55a2 AB	240	/* Hash command with SHA acceleration supported in hardware */
	241	#ifdef CONFIG_FSL_CAAM
	242	#define CONFIG_CMD_HASH
	243	#define CONFIG_SHA_HW_ACCEL
	244	#endif
	245
f3a8e2b7	246	#endif /* __LS1043A_COMMON_H */