[people/ms/u-boot.git] / include / configs / ls1043a_common.h

/*
 * Copyright (C) 2015 Freescale Semiconductor
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __LS1043A_COMMON_H
#define __LS1043A_COMMON_H

#define CONFIG_REMAKE_ELF
#define CONFIG_FSL_LAYERSCAPE
#define CONFIG_FSL_LSCH2
#define CONFIG_LS1043A
#define CONFIG_MP
#define CONFIG_SYS_FSL_CLK
#define CONFIG_GICV2

#include <asm/arch/config.h>
#ifdef CONFIG_SYS_FSL_SRDS_1
#define	CONFIG_SYS_HAS_SERDES
#endif

/* Link Definitions */
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)

#define CONFIG_SUPPORT_RAW_INITRD

#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BOARD_EARLY_INIT_F	1

#ifndef CONFIG_SYS_FSL_DDR4
#define CONFIG_SYS_FSL_DDR3		/* Use DDR3 memory */
#endif

#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000
#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE      0x880000000ULL

#define CPU_RELEASE_ADDR               secondary_boot_func

/* Generic Timer Definitions */
#define COUNTER_FREQUENCY		25000000	/* 25MHz */

/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 1024 * 1024)

/* Serial Port */
#define CONFIG_CONS_INDEX		1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0))

#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/* SD boot SPL */
#ifdef CONFIG_SD_BOOT
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_LDSCRIPT		"arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
#define CONFIG_SPL_WATCHDOG_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR		0xf0
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS		0x500

#define CONFIG_SPL_TEXT_BASE		0x10000000
#define CONFIG_SPL_MAX_SIZE		0x1d000
#define CONFIG_SPL_STACK		0x1001e000
#define CONFIG_SPL_PAD_TO		0x1d000

#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_TEXT_BASE + \
					CONFIG_SYS_MONITOR_LEN)
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
#define CONFIG_SPL_BSS_START_ADDR	0x80100000
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
#define CONFIG_SYS_MONITOR_LEN		0xa0000
#endif

/* NAND SPL */
#ifdef CONFIG_NAND_BOOT
#define CONFIG_SPL_PBL_PAD
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_LDSCRIPT		"arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
#define CONFIG_SPL_WATCHDOG_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_TEXT_BASE		0x10000000
#define CONFIG_SPL_MAX_SIZE		0x1a000
#define CONFIG_SPL_STACK		0x1001d000
#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_SPL_MALLOC_START	0x80200000
#define CONFIG_SPL_BSS_START_ADDR	0x80100000
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
#define CONFIG_SYS_MONITOR_LEN		0xa0000
#endif

/* IFC */
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_FSL_IFC
/*
 * CONFIG_SYS_FLASH_BASE has the final address (core view)
 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
 */
#define CONFIG_SYS_FLASH_BASE			0x60000000
#define CONFIG_SYS_FLASH_BASE_PHYS		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY	0x00000000

#ifndef CONFIG_SYS_NO_FLASH
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS	45	/* count down from 45/5: 9..1 */
#endif
#endif

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1
#define CONFIG_SYS_I2C_MXC_I2C2
#define CONFIG_SYS_I2C_MXC_I2C3
#define CONFIG_SYS_I2C_MXC_I2C4

/* PCIe */
#define CONFIG_PCI		/* Enable PCI/PCIE */
#define CONFIG_PCIE1		/* PCIE controller 1 */
#define CONFIG_PCIE2		/* PCIE controller 2 */
#define CONFIG_PCIE3		/* PCIE controller 3 */
#define CONFIG_PCIE_LAYERSCAPE	/* Use common FSL Layerscape PCIe code */
#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"

#define CONFIG_SYS_PCI_64BIT

#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF	0x00000000
#define CONFIG_SYS_PCIE_CFG0_SIZE	0x00001000	/* 4k */
#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF	0x00001000
#define CONFIG_SYS_PCIE_CFG1_SIZE	0x00001000	/* 4k */

#define CONFIG_SYS_PCIE_IO_BUS		0x00000000
#define CONFIG_SYS_PCIE_IO_PHYS_OFF	0x00010000
#define CONFIG_SYS_PCIE_IO_SIZE		0x00010000	/* 64k */

#define CONFIG_SYS_PCIE_MEM_BUS		0x40000000
#define CONFIG_SYS_PCIE_MEM_PHYS_OFF	0x40000000
#define CONFIG_SYS_PCIE_MEM_SIZE	0x40000000	/* 1G */

#ifdef CONFIG_PCI
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP
#define CONFIG_E1000
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_CMD_PCI
#endif

/* Command line configuration */
#define CONFIG_CMD_ENV
#define CONFIG_MENU
#define CONFIG_CMD_PXE

/*  MMC  */
#define CONFIG_MMC
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#define CONFIG_GENERIC_MMC
#define CONFIG_DOS_PARTITION
#endif

/*  DSPI  */
#define CONFIG_FSL_DSPI
#ifdef CONFIG_FSL_DSPI
#define CONFIG_DM_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO	/* cs0 */
#define CONFIG_SPI_FLASH_SST		/* cs1 */
#define CONFIG_SPI_FLASH_EON		/* cs2 */
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_SF_DEFAULT_BUS		1
#define CONFIG_SF_DEFAULT_CS		0
#endif
#endif

#define CONFIG_FSL_CAAM			/* Enable SEC/CAAM */

/* FMan ucode */
#define CONFIG_SYS_DPAA_FMAN
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_FM_MURAM_SIZE	0x60000

#ifdef CONFIG_NAND_BOOT
/* Store Fman ucode at offeset 0x160000(11 blocks). */
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
#define CONFIG_SYS_FMAN_FW_ADDR		(11 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SD_BOOT)
/*
 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 * about 1MB (2040 blocks), Env is stored after the image, and the env size is
 * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 2080(0x820).
 */
#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
#define CONFIG_SYS_FMAN_FW_ADDR		(512 * 0x820)
#elif defined(CONFIG_QSPI_BOOT)
#define CONFIG_SYS_QE_FW_IN_SPIFLASH
#define CONFIG_SYS_FMAN_FW_ADDR		0x400d0000
#define CONFIG_ENV_SPI_BUS		0
#define CONFIG_ENV_SPI_CS		0
#define CONFIG_ENV_SPI_MAX_HZ		1000000
#define CONFIG_ENV_SPI_MODE		0x03
#else
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
/* FMan fireware Pre-load address */
#define CONFIG_SYS_FMAN_FW_ADDR		0x60300000
#endif
#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#endif

/* Miscellaneous configurable options */
#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
#define CONFIG_ARCH_EARLY_INIT_R
#define CONFIG_BOARD_LATE_INIT

#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE		128

#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define MTDPARTS_DEFAULT "mtdparts=spi0.0:1m(uboot)," \
			"5m(kernel),1m(dtb),9m(file_system)"
#else
#define MTDPARTS_DEFAULT "mtdparts=60000000.nor:1m(nor_bank0_rcw)," \
			"1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \
			"1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \
			"1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \
			"1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \
			"40m(nor_bank4_fit);7e800000.flash:" \
			"1m(nand_uboot),1m(nand_uboot_env)," \
			"20m(nand_fit);spi0.0:1m(uboot)," \
			"5m(kernel),1m(dtb),9m(file_system)"
#endif

/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
	"loadaddr=0x80100000\0"			\
	"fdt_high=0xffffffffffffffff\0"		\
	"initrd_high=0xffffffffffffffff\0"	\
	"kernel_start=0x61100000\0"		\
	"kernel_load=0xa0000000\0"		\
	"kernel_size=0x2800000\0"		\
	"console=ttyS0,115200\0"                \
	"mtdparts=" MTDPARTS_DEFAULT "\0"

#define CONFIG_BOOTARGS			"console=ttyS0,115200 root=/dev/ram0 " \
					"earlycon=uart8250,mmio,0x21c0500 "    \
					MTDPARTS_DEFAULT

#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_BOOTCOMMAND		"sf probe && sf read $kernel_load "    \
					"e0000 f00000 && bootm $kernel_load"
#else
#define CONFIG_BOOTCOMMAND		"cp.b $kernel_start $kernel_load "     \
					"$kernel_size && bootm $kernel_load"
#endif

/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot args buffer */
#define CONFIG_SYS_LONGHELP
#define CONFIG_CMDLINE_EDITING		1
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_MAXARGS		64	/* max command args */

#define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */

/* Hash command with SHA acceleration supported in hardware */
#ifdef CONFIG_FSL_CAAM
#define CONFIG_CMD_HASH
#define CONFIG_SHA_HW_ACCEL
#endif

#endif /* __LS1043A_COMMON_H */
Commit	Line	Data
f3a8e2b7 MH	1	/*
	2	* Copyright (C) 2015 Freescale Semiconductor
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#ifndef __LS1043A_COMMON_H
	8	#define __LS1043A_COMMON_H
	9
	10	#define CONFIG_REMAKE_ELF
	11	#define CONFIG_FSL_LAYERSCAPE
	12	#define CONFIG_FSL_LSCH2
	13	#define CONFIG_LS1043A
831c068f	14	#define CONFIG_MP
f3a8e2b7 MH	15	#define CONFIG_SYS_FSL_CLK
	16	#define CONFIG_GICV2
	17
	18	#include <asm/arch/config.h>
	19	#ifdef CONFIG_SYS_FSL_SRDS_1
	20	#define CONFIG_SYS_HAS_SERDES
	21	#endif
	22
	23	/* Link Definitions */
	24	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
	25
	26	#define CONFIG_SUPPORT_RAW_INITRD
	27
	28	#define CONFIG_SKIP_LOWLEVEL_INIT
	29	#define CONFIG_BOARD_EARLY_INIT_F 1
	30
f3a8e2b7 MH	31	#ifndef CONFIG_SYS_FSL_DDR4
	32	#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
	33	#endif
	34
	35	#define CONFIG_VERY_BIG_RAM
	36	#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
	37	#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
	38	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
e994dddb	39	#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
f3a8e2b7	40
831c068f HZ	41	#define CPU_RELEASE_ADDR secondary_boot_func
831c068f HZ	42
f3a8e2b7 MH	43	/* Generic Timer Definitions */
	44	#define COUNTER_FREQUENCY 25000000 /* 25MHz */
	45
	46	/* Size of malloc() pool */
	47	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
	48
	49	/* Serial Port */
	50	#define CONFIG_CONS_INDEX 1
f3a8e2b7 MH	51	#define CONFIG_SYS_NS16550_SERIAL
	52	#define CONFIG_SYS_NS16550_REG_SIZE 1
	53	#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
	54
	55	#define CONFIG_BAUDRATE 115200
	56	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	57
c7ca8b07 GQ	58	/* SD boot SPL */
	59	#ifdef CONFIG_SD_BOOT
	60	#define CONFIG_SPL_FRAMEWORK
	61	#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
	62	#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
c7ca8b07 GQ	63	#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
c7ca8b07 GQ	64	#define CONFIG_SPL_WATCHDOG_SUPPORT
c7ca8b07	65	#define CONFIG_SPL_SERIAL_SUPPORT
c7ca8b07 GQ	66	#define CONFIG_SPL_MMC_SUPPORT
	67	#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xf0
	68	#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x500
	69
	70	#define CONFIG_SPL_TEXT_BASE 0x10000000
	71	#define CONFIG_SPL_MAX_SIZE 0x1d000
	72	#define CONFIG_SPL_STACK 0x1001e000
	73	#define CONFIG_SPL_PAD_TO 0x1d000
	74
	75	#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
	76	CONFIG_SYS_MONITOR_LEN)
	77	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
	78	#define CONFIG_SPL_BSS_START_ADDR 0x80100000
	79	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
	80	#define CONFIG_SYS_MONITOR_LEN 0xa0000
	81	#endif
	82
3ad44729 GQ	83	/* NAND SPL */
	84	#ifdef CONFIG_NAND_BOOT
	85	#define CONFIG_SPL_PBL_PAD
	86	#define CONFIG_SPL_FRAMEWORK
	87	#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
	88	#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
3ad44729	89	#define CONFIG_SPL_WATCHDOG_SUPPORT
3ad44729 GQ	90	#define CONFIG_SPL_SERIAL_SUPPORT
	91	#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
	92	#define CONFIG_SPL_NAND_SUPPORT
3ad44729 GQ	93	#define CONFIG_SPL_TEXT_BASE 0x10000000
	94	#define CONFIG_SPL_MAX_SIZE 0x1a000
	95	#define CONFIG_SPL_STACK 0x1001d000
	96	#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
	97	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
	98	#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
	99	#define CONFIG_SPL_BSS_START_ADDR 0x80100000
	100	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
	101	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
	102	#define CONFIG_SYS_MONITOR_LEN 0xa0000
	103	#endif
	104
f3a8e2b7	105	/* IFC */
b0f20caf	106	#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
f3a8e2b7 MH	107	#define CONFIG_FSL_IFC
	108	/*
	109	* CONFIG_SYS_FLASH_BASE has the final address (core view)
	110	* CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
	111	* CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
	112	* CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
	113	*/
	114	#define CONFIG_SYS_FLASH_BASE 0x60000000
	115	#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
	116	#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
	117
	118	#ifndef CONFIG_SYS_NO_FLASH
	119	#define CONFIG_FLASH_CFI_DRIVER
	120	#define CONFIG_SYS_FLASH_CFI
	121	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
	122	#define CONFIG_SYS_FLASH_QUIET_TEST
	123	#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
	124	#endif
166ef1e9	125	#endif
f3a8e2b7 MH	126
f3a8e2b7 MH	127	/* I2C */
f3a8e2b7 MH	128	#define CONFIG_SYS_I2C
	129	#define CONFIG_SYS_I2C_MXC
	130	#define CONFIG_SYS_I2C_MXC_I2C1
	131	#define CONFIG_SYS_I2C_MXC_I2C2
	132	#define CONFIG_SYS_I2C_MXC_I2C3
	133	#define CONFIG_SYS_I2C_MXC_I2C4
	134
	135	/* PCIe */
	136	#define CONFIG_PCI /* Enable PCI/PCIE */
	137	#define CONFIG_PCIE1 /* PCIE controller 1 */
	138	#define CONFIG_PCIE2 /* PCIE controller 2 */
	139	#define CONFIG_PCIE3 /* PCIE controller 3 */
	140	#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
	141	#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
	142
	143	#define CONFIG_SYS_PCI_64BIT
	144
	145	#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
	146	#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
	147	#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
	148	#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
	149
	150	#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
	151	#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
	152	#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
	153
	154	#define CONFIG_SYS_PCIE_MEM_BUS 0x40000000
	155	#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x40000000
	156	#define CONFIG_SYS_PCIE_MEM_SIZE 0x40000000 /* 1G */
	157
	158	#ifdef CONFIG_PCI
	159	#define CONFIG_NET_MULTI
	160	#define CONFIG_PCI_PNP
	161	#define CONFIG_E1000
	162	#define CONFIG_PCI_SCAN_SHOW
	163	#define CONFIG_CMD_PCI
	164	#endif
	165
	166	/* Command line configuration */
f3a8e2b7	167	#define CONFIG_CMD_ENV
6ffc4905 WS	168	#define CONFIG_MENU
6ffc4905 WS	169	#define CONFIG_CMD_PXE
f3a8e2b7	170
8ef0d5c4 YL	171	/* MMC */
	172	#define CONFIG_MMC
	173	#ifdef CONFIG_MMC
8ef0d5c4 YL	174	#define CONFIG_FSL_ESDHC
	175	#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
	176	#define CONFIG_GENERIC_MMC
	177	#define CONFIG_DOS_PARTITION
	178	#endif
	179
e0579a58 GQ	180	/* DSPI */
	181	#define CONFIG_FSL_DSPI
	182	#ifdef CONFIG_FSL_DSPI
e0579a58 GQ	183	#define CONFIG_DM_SPI_FLASH
	184	#define CONFIG_SPI_FLASH_STMICRO /* cs0 */
	185	#define CONFIG_SPI_FLASH_SST /* cs1 */
	186	#define CONFIG_SPI_FLASH_EON /* cs2 */
b0f20caf	187	#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
e0579a58 GQ	188	#define CONFIG_SF_DEFAULT_BUS 1
	189	#define CONFIG_SF_DEFAULT_CS 0
	190	#endif
166ef1e9	191	#endif
e0579a58	192
ef6c55a2 AB	193	#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
ef6c55a2 AB	194
e8297341 SX	195	/* FMan ucode */
	196	#define CONFIG_SYS_DPAA_FMAN
	197	#ifdef CONFIG_SYS_DPAA_FMAN
	198	#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
	199
fd1b147c QG	200	#ifdef CONFIG_NAND_BOOT
	201	/* Store Fman ucode at offeset 0x160000(11 blocks). */
	202	#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
	203	#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
2a555839 QG	204	#elif defined(CONFIG_SD_BOOT)
	205	/*
	206	* PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
	207	* about 1MB (2040 blocks), Env is stored after the image, and the env size is
	208	* 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 2080(0x820).
	209	*/
	210	#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
	211	#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
	212	#elif defined(CONFIG_QSPI_BOOT)
166ef1e9 GQ	213	#define CONFIG_SYS_QE_FW_IN_SPIFLASH
	214	#define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000
	215	#define CONFIG_ENV_SPI_BUS 0
	216	#define CONFIG_ENV_SPI_CS 0
	217	#define CONFIG_ENV_SPI_MAX_HZ 1000000
	218	#define CONFIG_ENV_SPI_MODE 0x03
	219	#else
e8297341 SX	220	#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
	221	/* FMan fireware Pre-load address */
	222	#define CONFIG_SYS_FMAN_FW_ADDR 0x60300000
166ef1e9	223	#endif
e8297341 SX	224	#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
	225	#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
	226	#endif
	227
f3a8e2b7 MH	228	/* Miscellaneous configurable options */
	229	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
	230	#define CONFIG_ARCH_EARLY_INIT_R
	231	#define CONFIG_BOARD_LATE_INIT
	232
	233	#define CONFIG_HWCONFIG
	234	#define HWCONFIG_BUFFER_SIZE 128
	235
dbe18f16 WS	236	#if defined(CONFIG_QSPI_BOOT) \|\| defined(CONFIG_SD_BOOT_QSPI)
	237	#define MTDPARTS_DEFAULT "mtdparts=spi0.0:1m(uboot)," \
	238	"5m(kernel),1m(dtb),9m(file_system)"
	239	#else
	240	#define MTDPARTS_DEFAULT "mtdparts=60000000.nor:1m(nor_bank0_rcw)," \
	241	"1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \
	242	"1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \
	243	"1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \
	244	"1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \
	245	"40m(nor_bank4_fit);7e800000.flash:" \
	246	"1m(nand_uboot),1m(nand_uboot_env)," \
	247	"20m(nand_fit);spi0.0:1m(uboot)," \
	248	"5m(kernel),1m(dtb),9m(file_system)"
	249	#endif
	250
f3a8e2b7 MH	251	/* Initial environment variables */
	252	#define CONFIG_EXTRA_ENV_SETTINGS \
	253	"hwconfig=fsl_ddr:bank_intlv=auto\0" \
	254	"loadaddr=0x80100000\0" \
f3a8e2b7 MH	255	"fdt_high=0xffffffffffffffff\0" \
f3a8e2b7 MH	256	"initrd_high=0xffffffffffffffff\0" \
ad6767b6 QG	257	"kernel_start=0x61100000\0" \
	258	"kernel_load=0xa0000000\0" \
	259	"kernel_size=0x2800000\0" \
dbe18f16 WS	260	"console=ttyS0,115200\0" \
dbe18f16 WS	261	"mtdparts=" MTDPARTS_DEFAULT "\0"
f3a8e2b7 MH	262
f3a8e2b7 MH	263	#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
dbe18f16 WS	264	"earlycon=uart8250,mmio,0x21c0500 " \
	265	MTDPARTS_DEFAULT
	266
1297cdb4 QG	267	#if defined(CONFIG_QSPI_BOOT) \|\| defined(CONFIG_SD_BOOT_QSPI)
	268	#define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load " \
	269	"e0000 f00000 && bootm $kernel_load"
	270	#else
f3a8e2b7 MH	271	#define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \
f3a8e2b7 MH	272	"$kernel_size && bootm $kernel_load"
1297cdb4	273	#endif
f3a8e2b7 MH	274
	275	/* Monitor Command Prompt */
	276	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
f3a8e2b7 MH	277	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
f3a8e2b7 MH	278	sizeof(CONFIG_SYS_PROMPT) + 16)
f3a8e2b7 MH	279	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
	280	#define CONFIG_SYS_LONGHELP
	281	#define CONFIG_CMDLINE_EDITING 1
	282	#define CONFIG_AUTO_COMPLETE
	283	#define CONFIG_SYS_MAXARGS 64 /* max command args */
	284
	285	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
	286
ef6c55a2 AB	287	/* Hash command with SHA acceleration supported in hardware */
	288	#ifdef CONFIG_FSL_CAAM
	289	#define CONFIG_CMD_HASH
	290	#define CONFIG_SHA_HW_ACCEL
	291	#endif
	292
f3a8e2b7	293	#endif /* __LS1043A_COMMON_H */