[people/ms/u-boot.git] / include / configs / ls1043aqds.h

/*
 * Copyright 2015 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __LS1043AQDS_H__
#define __LS1043AQDS_H__

#include "ls1043a_common.h"

#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO

#if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT)
#define CONFIG_SYS_TEXT_BASE		0x82000000
#else
#define CONFIG_SYS_TEXT_BASE		0x60100000
#endif

#ifndef __ASSEMBLY__
unsigned long get_board_sys_clk(void);
unsigned long get_board_ddr_clk(void);
#endif

#define CONFIG_SYS_CLK_FREQ		100000000
#define CONFIG_DDR_CLK_FREQ		100000000

#define CONFIG_SKIP_LOWLEVEL_INIT

#define CONFIG_LAYERSCAPE_NS_ACCESS

#define CONFIG_DIMM_SLOTS_PER_CTLR	1
/* Physical Memory Map */
#define CONFIG_CHIP_SELECTS_PER_CTRL	4
#define CONFIG_NR_DRAM_BANKS		2

#define CONFIG_DDR_SPD
#define SPD_EEPROM_ADDRESS		0x51
#define CONFIG_SYS_SPD_BUS_NUM		0

#define CONFIG_FSL_DDR_INTERACTIVE	/* Interactive debugging */
#ifndef CONFIG_SYS_FSL_DDR4
#define CONFIG_SYS_FSL_DDR3		/* Use DDR3 memory */
#endif

#define CONFIG_DDR_ECC
#ifdef CONFIG_DDR_ECC
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE           0xdeadbeef
#endif

#define CONFIG_SYS_HAS_SERDES

#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_FMAN_ENET
#define CONFIG_PHYLIB
#define CONFIG_PHY_VITESSE
#define CONFIG_PHY_REALTEK
#define CONFIG_PHYLIB_10G
#define RGMII_PHY1_ADDR		0x1
#define RGMII_PHY2_ADDR		0x2
#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
/* PHY address on QSGMII riser card on slot 1 */
#define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4
#define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5
#define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6
#define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7
/* PHY address on QSGMII riser card on slot 2 */
#define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
#define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
#define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
#define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
#endif

#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043aqds/ls1043aqds_pbi.cfg
#endif

#ifdef CONFIG_NAND_BOOT
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg
#endif

#ifdef CONFIG_SD_BOOT
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg
#endif

/* LPUART */
#ifdef CONFIG_LPUART
#define CONFIG_LPUART_32B_REG
#endif

/* SATA */
#define CONFIG_LIBATA
#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_CMD_SCSI
#define CONFIG_CMD_FAT
#define CONFIG_CMD_EXT2
#define CONFIG_DOS_PARTITION
#define CONFIG_BOARD_LATE_INIT

#define CONFIG_SYS_SATA				AHCI_BASE_ADDR

#define CONFIG_SYS_SCSI_MAX_SCSI_ID		1
#define CONFIG_SYS_SCSI_MAX_LUN			1
#define CONFIG_SYS_SCSI_MAX_DEVICE		(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
						CONFIG_SYS_SCSI_MAX_LUN)

/*
 * IFC Definitions
 */
#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
				CSPR_PORT_SIZE_16 | \
				CSPR_MSEL_NOR | \
				CSPR_V)
#define CONFIG_SYS_NOR1_CSPR_EXT	(0x0)
#define CONFIG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
				+ 0x8000000) | \
				CSPR_PORT_SIZE_16 | \
				CSPR_MSEL_NOR | \
				CSPR_V)
#define CONFIG_SYS_NOR_AMASK		IFC_AMASK(128 * 1024 * 1024)

#define CONFIG_SYS_NOR_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
					CSOR_NOR_TRHZ_80)
#define CONFIG_SYS_NOR_FTIM0		(FTIM0_NOR_TACSE(0x4) | \
					FTIM0_NOR_TEADC(0x5) | \
					FTIM0_NOR_TEAHC(0x5))
#define CONFIG_SYS_NOR_FTIM1		(FTIM1_NOR_TACO(0x35) | \
					FTIM1_NOR_TRAD_NOR(0x1a) | \
					FTIM1_NOR_TSEQRAD_NOR(0x13))
#define CONFIG_SYS_NOR_FTIM2		(FTIM2_NOR_TCS(0x4) | \
					FTIM2_NOR_TCH(0x4) | \
					FTIM2_NOR_TWPH(0xe) | \
					FTIM2_NOR_TWP(0x1c))
#define CONFIG_SYS_NOR_FTIM3		0

#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS, \
					CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}

#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
#define CONFIG_SYS_WRITE_SWAPPED_DATA

/*
 * NAND Flash Definitions
 */
#define CONFIG_NAND_FSL_IFC

#define CONFIG_SYS_NAND_BASE		0x7e800000
#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE

#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)

#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
				| CSPR_PORT_SIZE_8	\
				| CSPR_MSEL_NAND	\
				| CSPR_V)
#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */ \
				| CSOR_NAND_RAL_3	/* RAL = 3 Bytes */ \
				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
				| CSOR_NAND_SPRZ_64	/* Spare size = 64 */ \
				| CSOR_NAND_PB(64))	/* 64 Pages Per Block */

#define CONFIG_SYS_NAND_ONFI_DETECTION

#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x7) | \
					FTIM0_NAND_TWP(0x18)   | \
					FTIM0_NAND_TWCHT(0x7) | \
					FTIM0_NAND_TWH(0xa))
#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
					FTIM1_NAND_TWBE(0x39)  | \
					FTIM1_NAND_TRR(0xe)   | \
					FTIM1_NAND_TRP(0x18))
#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0xf) | \
					FTIM2_NAND_TREH(0xa) | \
					FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3           0x0

#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND

#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)

#ifdef CONFIG_NAND_BOOT
#define CONFIG_SPL_PAD_TO		0x20000		/* block aligned */
#define CONFIG_SYS_NAND_U_BOOT_OFFS	CONFIG_SPL_PAD_TO
#define CONFIG_SYS_NAND_U_BOOT_SIZE	(640 << 10)
#endif

/*
 * QIXIS Definitions
 */
#define CONFIG_FSL_QIXIS

#ifdef CONFIG_FSL_QIXIS
#define QIXIS_BASE			0x7fb00000
#define QIXIS_BASE_PHYS			QIXIS_BASE
#define CONFIG_SYS_I2C_FPGA_ADDR	0x66
#define QIXIS_LBMAP_SWITCH		6
#define QIXIS_LBMAP_MASK		0x0f
#define QIXIS_LBMAP_SHIFT		0
#define QIXIS_LBMAP_DFLTBANK		0x00
#define QIXIS_LBMAP_ALTBANK		0x04
#define QIXIS_LBMAP_NAND		0x09
#define QIXIS_LBMAP_SD			0x00
#define QIXIS_RCW_SRC_NAND		0x106
#define QIXIS_RCW_SRC_SD		0x040
#define QIXIS_RST_CTL_RESET		0x41
#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08

#define CONFIG_SYS_FPGA_CSPR_EXT	(0x0)
#define CONFIG_SYS_FPGA_CSPR		(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
					CSPR_PORT_SIZE_8 | \
					CSPR_MSEL_GPCM | \
					CSPR_V)
#define CONFIG_SYS_FPGA_AMASK		IFC_AMASK(64 * 1024)
#define CONFIG_SYS_FPGA_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
					CSOR_NOR_NOR_MODE_AVD_NOR | \
					CSOR_NOR_TRHZ_80)

/*
 * QIXIS Timing parameters for IFC GPCM
 */
#define CONFIG_SYS_FPGA_FTIM0		(FTIM0_GPCM_TACSE(0xc) | \
					FTIM0_GPCM_TEADC(0x20) | \
					FTIM0_GPCM_TEAHC(0x10))
#define CONFIG_SYS_FPGA_FTIM1		(FTIM1_GPCM_TACO(0x50) | \
					FTIM1_GPCM_TRAD(0x1f))
#define CONFIG_SYS_FPGA_FTIM2		(FTIM2_GPCM_TCS(0x8) | \
					FTIM2_GPCM_TCH(0x8) | \
					FTIM2_GPCM_TWP(0xf0))
#define CONFIG_SYS_FPGA_FTIM3		0x0
#endif

#ifdef CONFIG_NAND_BOOT
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR1_CSPR_EXT
#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR1_CSPR
#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR3_EXT		CONFIG_SYS_FPGA_CSPR_EXT
#define CONFIG_SYS_CSPR3		CONFIG_SYS_FPGA_CSPR
#define CONFIG_SYS_AMASK3		CONFIG_SYS_FPGA_AMASK
#define CONFIG_SYS_CSOR3		CONFIG_SYS_FPGA_CSOR
#define CONFIG_SYS_CS3_FTIM0		CONFIG_SYS_FPGA_FTIM0
#define CONFIG_SYS_CS3_FTIM1		CONFIG_SYS_FPGA_FTIM1
#define CONFIG_SYS_CS3_FTIM2		CONFIG_SYS_FPGA_FTIM2
#define CONFIG_SYS_CS3_FTIM3		CONFIG_SYS_FPGA_FTIM3
#else
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR1_CSPR_EXT
#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR3_EXT		CONFIG_SYS_FPGA_CSPR_EXT
#define CONFIG_SYS_CSPR3		CONFIG_SYS_FPGA_CSPR
#define CONFIG_SYS_AMASK3		CONFIG_SYS_FPGA_AMASK
#define CONFIG_SYS_CSOR3		CONFIG_SYS_FPGA_CSOR
#define CONFIG_SYS_CS3_FTIM0		CONFIG_SYS_FPGA_FTIM0
#define CONFIG_SYS_CS3_FTIM1		CONFIG_SYS_FPGA_FTIM1
#define CONFIG_SYS_CS3_FTIM2		CONFIG_SYS_FPGA_FTIM2
#define CONFIG_SYS_CS3_FTIM3		CONFIG_SYS_FPGA_FTIM3
#endif

/*
 * I2C bus multiplexer
 */
#define I2C_MUX_PCA_ADDR_PRI		0x77
#define I2C_MUX_PCA_ADDR_SEC		0x76 /* Secondary multiplexer */
#define I2C_RETIMER_ADDR		0x18
#define I2C_MUX_CH_DEFAULT		0x8
#define I2C_MUX_CH_CH7301		0xC
#define I2C_MUX_CH5			0xD
#define I2C_MUX_CH7			0xF

#define I2C_MUX_CH_VOL_MONITOR 0xa

/* Voltage monitor on channel 2*/
#define I2C_VOL_MONITOR_ADDR           0x40
#define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
#define I2C_VOL_MONITOR_BUS_V_OVF      0x1
#define I2C_VOL_MONITOR_BUS_V_SHIFT    3

#define CONFIG_VID_FLS_ENV		"ls1043aqds_vdd_mv"
#ifndef CONFIG_SPL_BUILD
#define CONFIG_VID
#endif
#define CONFIG_VOL_MONITOR_IR36021_SET
#define CONFIG_VOL_MONITOR_INA220
/* The lowest and highest voltage allowed for LS1043AQDS */
#define VDD_MV_MIN			819
#define VDD_MV_MAX			1212

/*
 * Miscellaneous configurable options
 */
#define CONFIG_MISC_INIT_R
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
#define CONFIG_SYS_PROMPT		"=> "
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_PBSIZE		\
		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE

#define CONFIG_CMD_GREPENV
#define CONFIG_CMD_MEMINFO
#define CONFIG_CMD_MEMTEST
#define CONFIG_SYS_MEMTEST_START	0x80000000
#define CONFIG_SYS_MEMTEST_END		0x9fffffff

#define CONFIG_SYS_HZ			1000

/*
 * Stack sizes
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE		(30 * 1024)

#define CONFIG_SYS_INIT_SP_OFFSET \
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)

#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
#else
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
#endif

/*
 * Environment
 */
#define CONFIG_ENV_OVERWRITE

#ifdef CONFIG_NAND_BOOT
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE			0x2000
#define CONFIG_ENV_OFFSET		(10 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SD_BOOT)
#define CONFIG_ENV_OFFSET		(1024 * 1024)
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV		0
#define CONFIG_ENV_SIZE			0x2000
#else
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x200000)
#define CONFIG_ENV_SECT_SIZE		0x20000
#define CONFIG_ENV_SIZE			0x20000
#endif

#define CONFIG_OF_LIBFDT
#define CONFIG_OF_BOARD_SETUP
#define CONFIG_CMD_BOOTZ
#define CONFIG_CMD_MII
#define CONFIG_CMDLINE_TAG

#include <asm/fsl_secure_boot.h>

#endif /* __LS1043AQDS_H__ */
Commit	Line	Data
02b5d2ed SX	1	/*
	2	* Copyright 2015 Freescale Semiconductor, Inc.
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#ifndef __LS1043AQDS_H__
	8	#define __LS1043AQDS_H__
	9
	10	#include "ls1043a_common.h"
	11
	12	#define CONFIG_DISPLAY_CPUINFO
	13	#define CONFIG_DISPLAY_BOARDINFO
	14
	15	#if defined(CONFIG_NAND_BOOT) \|\| defined(CONFIG_SD_BOOT)
	16	#define CONFIG_SYS_TEXT_BASE 0x82000000
	17	#else
	18	#define CONFIG_SYS_TEXT_BASE 0x60100000
	19	#endif
	20
	21	#ifndef __ASSEMBLY__
	22	unsigned long get_board_sys_clk(void);
	23	unsigned long get_board_ddr_clk(void);
	24	#endif
	25
	26	#define CONFIG_SYS_CLK_FREQ 100000000
	27	#define CONFIG_DDR_CLK_FREQ 100000000
	28
	29	#define CONFIG_SKIP_LOWLEVEL_INIT
	30
	31	#define CONFIG_LAYERSCAPE_NS_ACCESS
	32
	33	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
	34	/* Physical Memory Map */
	35	#define CONFIG_CHIP_SELECTS_PER_CTRL 4
58e4ad1d	36	#define CONFIG_NR_DRAM_BANKS 2
02b5d2ed SX	37
	38	#define CONFIG_DDR_SPD
	39	#define SPD_EEPROM_ADDRESS 0x51
	40	#define CONFIG_SYS_SPD_BUS_NUM 0
	41
	42	#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
	43	#ifndef CONFIG_SYS_FSL_DDR4
	44	#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
	45	#endif
	46
	47	#define CONFIG_DDR_ECC
	48	#ifdef CONFIG_DDR_ECC
	49	#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
	50	#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
	51	#endif
	52
	53	#define CONFIG_SYS_HAS_SERDES
	54
	55	#ifdef CONFIG_SYS_DPAA_FMAN
	56	#define CONFIG_FMAN_ENET
	57	#define CONFIG_PHYLIB
	58	#define CONFIG_PHY_VITESSE
	59	#define CONFIG_PHY_REALTEK
	60	#define CONFIG_PHYLIB_10G
	61	#define RGMII_PHY1_ADDR 0x1
	62	#define RGMII_PHY2_ADDR 0x2
	63	#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
	64	#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
	65	#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
	66	#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
	67	/* PHY address on QSGMII riser card on slot 1 */
	68	#define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4
	69	#define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5
	70	#define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6
	71	#define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7
	72	/* PHY address on QSGMII riser card on slot 2 */
	73	#define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
	74	#define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
	75	#define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
	76	#define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
	77	#endif
	78
	79	#ifdef CONFIG_RAMBOOT_PBL
	80	#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043aqds/ls1043aqds_pbi.cfg
	81	#endif
	82
	83	#ifdef CONFIG_NAND_BOOT
	84	#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg
	85	#endif
	86
	87	#ifdef CONFIG_SD_BOOT
	88	#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg
	89	#endif
	90
2970e14f WS	91	/* LPUART */
	92	#ifdef CONFIG_LPUART
	93	#define CONFIG_LPUART_32B_REG
	94	#endif
	95
989c5f0a TY	96	/* SATA */
	97	#define CONFIG_LIBATA
	98	#define CONFIG_SCSI_AHCI
	99	#define CONFIG_SCSI_AHCI_PLAT
	100	#define CONFIG_CMD_SCSI
	101	#define CONFIG_CMD_FAT
	102	#define CONFIG_CMD_EXT2
	103	#define CONFIG_DOS_PARTITION
	104	#define CONFIG_BOARD_LATE_INIT
	105
	106	#define CONFIG_SYS_SATA AHCI_BASE_ADDR
	107
	108	#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
	109	#define CONFIG_SYS_SCSI_MAX_LUN 1
	110	#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
	111	CONFIG_SYS_SCSI_MAX_LUN)
	112
02b5d2ed SX	113	/*
	114	* IFC Definitions
	115	*/
	116	#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
	117	#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \| \
	118	CSPR_PORT_SIZE_16 \| \
	119	CSPR_MSEL_NOR \| \
	120	CSPR_V)
	121	#define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
	122	#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
	123	+ 0x8000000) \| \
	124	CSPR_PORT_SIZE_16 \| \
	125	CSPR_MSEL_NOR \| \
	126	CSPR_V)
	127	#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
	128
	129	#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) \| \
	130	CSOR_NOR_TRHZ_80)
	131	#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) \| \
	132	FTIM0_NOR_TEADC(0x5) \| \
	133	FTIM0_NOR_TEAHC(0x5))
	134	#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) \| \
	135	FTIM1_NOR_TRAD_NOR(0x1a) \| \
	136	FTIM1_NOR_TSEQRAD_NOR(0x13))
	137	#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) \| \
	138	FTIM2_NOR_TCH(0x4) \| \
	139	FTIM2_NOR_TWPH(0xe) \| \
	140	FTIM2_NOR_TWP(0x1c))
	141	#define CONFIG_SYS_NOR_FTIM3 0
	142
	143	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
	144	#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
	145	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	146	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
	147
	148	#define CONFIG_SYS_FLASH_EMPTY_INFO
	149	#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
	150	CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
	151
	152	#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
	153	#define CONFIG_SYS_WRITE_SWAPPED_DATA
	154
	155	/*
	156	* NAND Flash Definitions
	157	*/
	158	#define CONFIG_NAND_FSL_IFC
	159
	160	#define CONFIG_SYS_NAND_BASE 0x7e800000
	161	#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
	162
	163	#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
	164
	165	#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
	166	\| CSPR_PORT_SIZE_8 \
	167	\| CSPR_MSEL_NAND \
	168	\| CSPR_V)
	169	#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
	170	#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
	171	\| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
	172	\| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
	173	\| CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
	174	\| CSOR_NAND_PGS_2K /* Page Size = 2K */ \
	175	\| CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
	176	\| CSOR_NAND_PB(64)) /* 64 Pages Per Block */
177
178	#define CONFIG_SYS_NAND_ONFI_DETECTION
179
180	#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) \| \
181	FTIM0_NAND_TWP(0x18) \| \
182	FTIM0_NAND_TWCHT(0x7) \| \
183	FTIM0_NAND_TWH(0xa))
184	#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) \| \
185	FTIM1_NAND_TWBE(0x39) \| \
186	FTIM1_NAND_TRR(0xe) \| \
187	FTIM1_NAND_TRP(0x18))
188	#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) \| \
189	FTIM2_NAND_TREH(0xa) \| \
190	FTIM2_NAND_TWHRE(0x1e))
191	#define CONFIG_SYS_NAND_FTIM3 0x0
192
193	#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
194	#define CONFIG_SYS_MAX_NAND_DEVICE 1
195	#define CONFIG_MTD_NAND_VERIFY_WRITE
196	#define CONFIG_CMD_NAND
197
198	#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
199
200	#ifdef CONFIG_NAND_BOOT
201	#define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */
202	#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
203	#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10)
204	#endif
205
206	/*
207	* QIXIS Definitions
208	*/
209	#define CONFIG_FSL_QIXIS
210
211	#ifdef CONFIG_FSL_QIXIS
212	#define QIXIS_BASE 0x7fb00000
213	#define QIXIS_BASE_PHYS QIXIS_BASE
214	#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
215	#define QIXIS_LBMAP_SWITCH 6
216	#define QIXIS_LBMAP_MASK 0x0f
217	#define QIXIS_LBMAP_SHIFT 0
218	#define QIXIS_LBMAP_DFLTBANK 0x00
219	#define QIXIS_LBMAP_ALTBANK 0x04
ee2a4eee GQ	220	#define QIXIS_LBMAP_NAND 0x09
	221	#define QIXIS_LBMAP_SD 0x00
	222	#define QIXIS_RCW_SRC_NAND 0x106
	223	#define QIXIS_RCW_SRC_SD 0x040
a4b7d68c	224	#define QIXIS_RST_CTL_RESET 0x41
02b5d2ed SX	225	#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
	226	#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
	227	#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
	228
	229	#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
	230	#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \| \
	231	CSPR_PORT_SIZE_8 \| \
	232	CSPR_MSEL_GPCM \| \
	233	CSPR_V)
	234	#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
	235	#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) \| \
	236	CSOR_NOR_NOR_MODE_AVD_NOR \| \
	237	CSOR_NOR_TRHZ_80)
	238
	239	/*
	240	* QIXIS Timing parameters for IFC GPCM
	241	*/
	242	#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) \| \
	243	FTIM0_GPCM_TEADC(0x20) \| \
	244	FTIM0_GPCM_TEAHC(0x10))
	245	#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) \| \
	246	FTIM1_GPCM_TRAD(0x1f))
	247	#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) \| \
	248	FTIM2_GPCM_TCH(0x8) \| \
	249	FTIM2_GPCM_TWP(0xf0))
	250	#define CONFIG_SYS_FPGA_FTIM3 0x0
	251	#endif
	252
	253	#ifdef CONFIG_NAND_BOOT
	254	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
	255	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
	256	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
	257	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
	258	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
	259	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
	260	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
	261	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
	262	#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
	263	#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
	264	#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
	265	#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
	266	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
	267	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
	268	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
	269	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
	270	#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
	271	#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
	272	#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
	273	#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
	274	#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
	275	#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
	276	#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
	277	#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
	278	#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
	279	#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
	280	#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
	281	#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
	282	#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
	283	#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
	284	#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
	285	#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
	286	#else
	287	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
	288	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
289	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
290	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
291	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
292	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
293	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
294	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
295	#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
296	#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
297	#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
298	#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
299	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
300	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
301	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
302	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
303	#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
304	#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
305	#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
306	#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
307	#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
308	#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
309	#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
310	#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
311	#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
312	#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
313	#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
314	#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
315	#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
316	#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
317	#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
318	#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
319	#endif
320
321	/*
322	* I2C bus multiplexer
323	*/
324	#define I2C_MUX_PCA_ADDR_PRI 0x77
325	#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
326	#define I2C_RETIMER_ADDR 0x18
327	#define I2C_MUX_CH_DEFAULT 0x8
328	#define I2C_MUX_CH_CH7301 0xC
329	#define I2C_MUX_CH5 0xD
330	#define I2C_MUX_CH7 0xF
331
332	#define I2C_MUX_CH_VOL_MONITOR 0xa
333
334	/* Voltage monitor on channel 2*/
335	#define I2C_VOL_MONITOR_ADDR 0x40
336	#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
337	#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
338	#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
339
340	#define CONFIG_VID_FLS_ENV "ls1043aqds_vdd_mv"
341	#ifndef CONFIG_SPL_BUILD
342	#define CONFIG_VID
343	#endif
344	#define CONFIG_VOL_MONITOR_IR36021_SET
345	#define CONFIG_VOL_MONITOR_INA220
346	/* The lowest and highest voltage allowed for LS1043AQDS */
347	#define VDD_MV_MIN 819
348	#define VDD_MV_MAX 1212
349
350	/*
351	* Miscellaneous configurable options
352	*/
353	#define CONFIG_MISC_INIT_R
354	#define CONFIG_SYS_LONGHELP /* undef to save memory */
355	#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
356	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
357	#define CONFIG_SYS_PROMPT "=> "
358	#define CONFIG_AUTO_COMPLETE
359	#define CONFIG_SYS_PBSIZE \
360	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
361	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
362
363	#define CONFIG_CMD_GREPENV
364	#define CONFIG_CMD_MEMINFO
365	#define CONFIG_CMD_MEMTEST
366	#define CONFIG_SYS_MEMTEST_START 0x80000000
367	#define CONFIG_SYS_MEMTEST_END 0x9fffffff
368
369	#define CONFIG_SYS_HZ 1000
370
371	/*
372	* Stack sizes
373	* The stack sizes are set up in start.S using the settings below
374	*/
375	#define CONFIG_STACKSIZE (30 * 1024)
376
377	#define CONFIG_SYS_INIT_SP_OFFSET \
378	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
379
380	#ifdef CONFIG_SPL_BUILD
381	#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
382	#else
383	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
384	#endif
385
386	/*
387	* Environment
388	*/
389	#define CONFIG_ENV_OVERWRITE
390
391	#ifdef CONFIG_NAND_BOOT
392	#define CONFIG_ENV_IS_IN_NAND
393	#define CONFIG_ENV_SIZE 0x2000
394	#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
395	#elif defined(CONFIG_SD_BOOT)
396	#define CONFIG_ENV_OFFSET (1024 * 1024)
397	#define CONFIG_ENV_IS_IN_MMC
398	#define CONFIG_SYS_MMC_ENV_DEV 0
399	#define CONFIG_ENV_SIZE 0x2000
400	#else
401	#define CONFIG_ENV_IS_IN_FLASH
402	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000)
403	#define CONFIG_ENV_SECT_SIZE 0x20000
404	#define CONFIG_ENV_SIZE 0x20000
405	#endif
406
407	#define CONFIG_OF_LIBFDT
408	#define CONFIG_OF_BOARD_SETUP
409	#define CONFIG_CMD_BOOTZ
410	#define CONFIG_CMD_MII
411	#define CONFIG_CMDLINE_TAG
412
ef6c55a2 AB	413	#include <asm/fsl_secure_boot.h>
ef6c55a2 AB	414
02b5d2ed	415	#endif /* __LS1043AQDS_H__ */