[people/ms/u-boot.git] / include / configs / ls1046aqds.h

/*
 * Copyright 2016 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __LS1046AQDS_H__
#define __LS1046AQDS_H__

#include "ls1046a_common.h"

#ifndef __ASSEMBLY__
unsigned long get_board_sys_clk(void);
unsigned long get_board_ddr_clk(void);
#endif

#define CONFIG_SYS_CLK_FREQ		get_board_sys_clk()
#define CONFIG_DDR_CLK_FREQ		get_board_ddr_clk()

#define CONFIG_SKIP_LOWLEVEL_INIT

#define CONFIG_LAYERSCAPE_NS_ACCESS

#define CONFIG_DIMM_SLOTS_PER_CTLR	1
/* Physical Memory Map */
#define CONFIG_CHIP_SELECTS_PER_CTRL	4
#define CONFIG_NR_DRAM_BANKS		2

#define CONFIG_DDR_SPD
#define SPD_EEPROM_ADDRESS		0x51
#define CONFIG_SYS_SPD_BUS_NUM		0

#ifndef CONFIG_SPL
#define CONFIG_FSL_DDR_INTERACTIVE	/* Interactive debugging */
#endif

#define CONFIG_DDR_ECC
#ifdef CONFIG_DDR_ECC
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE           0xdeadbeef
#endif

/* DSPI */
#ifdef CONFIG_FSL_DSPI
#define CONFIG_SPI_FLASH_STMICRO	/* cs0 */
#define CONFIG_SPI_FLASH_SST		/* cs1 */
#define CONFIG_SPI_FLASH_EON		/* cs2 */
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_SF_DEFAULT_BUS		1
#define CONFIG_SF_DEFAULT_CS		0
#endif
#endif

/* QSPI */
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#ifdef CONFIG_FSL_QSPI
#define CONFIG_SPI_FLASH_SPANSION
#define FSL_QSPI_FLASH_SIZE		(1 << 24)
#define FSL_QSPI_FLASH_NUM		2
#endif
#endif

#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_FMAN_ENET
#define CONFIG_PHY_VITESSE
#define CONFIG_PHY_REALTEK
#define CONFIG_PHYLIB_10G
#define RGMII_PHY1_ADDR		0x1
#define RGMII_PHY2_ADDR		0x2
#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
/* PHY address on QSGMII riser card on slot 2 */
#define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
#define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
#define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
#define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
#endif

#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_SYS_FSL_PBL_PBI \
	board/freescale/ls1046aqds/ls1046aqds_pbi.cfg
#endif

#ifdef CONFIG_NAND_BOOT
#define CONFIG_SYS_FSL_PBL_RCW \
	board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg
#endif

#ifdef CONFIG_SD_BOOT
#ifdef CONFIG_SD_BOOT_QSPI
#define CONFIG_SYS_FSL_PBL_RCW \
	board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg
#else
#define CONFIG_SYS_FSL_PBL_RCW \
	board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg
#endif
#endif

/* IFC */
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
#define	CONFIG_FSL_IFC
/*
 * CONFIG_SYS_FLASH_BASE has the final address (core view)
 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
 */
#define CONFIG_SYS_FLASH_BASE			0x60000000
#define CONFIG_SYS_FLASH_BASE_PHYS		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY	0x00000000

#ifdef CONFIG_MTD_NOR_FLASH
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS	45	/* count down from 45/5: 9..1 */
#endif
#endif

/* LPUART */
#ifdef CONFIG_LPUART
#define CONFIG_LPUART_32B_REG
#define CFG_UART_MUX_MASK	0x6
#define CFG_UART_MUX_SHIFT	1
#define CFG_LPUART_EN		0x2
#endif

/* EEPROM */
#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM		0
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x57
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5

/*
 * IFC Definitions
 */
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
				CSPR_PORT_SIZE_16 | \
				CSPR_MSEL_NOR | \
				CSPR_V)
#define CONFIG_SYS_NOR1_CSPR_EXT	(0x0)
#define CONFIG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
				+ 0x8000000) | \
				CSPR_PORT_SIZE_16 | \
				CSPR_MSEL_NOR | \
				CSPR_V)
#define CONFIG_SYS_NOR_AMASK		IFC_AMASK(128 * 1024 * 1024)

#define CONFIG_SYS_NOR_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
					CSOR_NOR_TRHZ_80)
#define CONFIG_SYS_NOR_FTIM0		(FTIM0_NOR_TACSE(0x4) | \
					FTIM0_NOR_TEADC(0x5) | \
					FTIM0_NOR_TAVDS(0x6) | \
					FTIM0_NOR_TEAHC(0x5))
#define CONFIG_SYS_NOR_FTIM1		(FTIM1_NOR_TACO(0x35) | \
					FTIM1_NOR_TRAD_NOR(0x1a) | \
					FTIM1_NOR_TSEQRAD_NOR(0x13))
#define CONFIG_SYS_NOR_FTIM2		(FTIM2_NOR_TCS(0x8) | \
					FTIM2_NOR_TCH(0x8) | \
					FTIM2_NOR_TWPH(0xe) | \
					FTIM2_NOR_TWP(0x1c))
#define CONFIG_SYS_NOR_FTIM3		0

#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS, \
					CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}

#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
#define CONFIG_SYS_WRITE_SWAPPED_DATA

/*
 * NAND Flash Definitions
 */
#define CONFIG_NAND_FSL_IFC

#define CONFIG_SYS_NAND_BASE		0x7e800000
#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE

#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)

#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
				| CSPR_PORT_SIZE_8	\
				| CSPR_MSEL_NAND	\
				| CSPR_V)
#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
				| CSOR_NAND_ECC_MODE_8	/* 8-bit ECC */ \
				| CSOR_NAND_RAL_3	/* RAL = 3 Bytes */ \
				| CSOR_NAND_PGS_4K	/* Page Size = 4K */ \
				| CSOR_NAND_SPRZ_224	/* Spare size = 224 */ \
				| CSOR_NAND_PB(64))	/* 64 Pages Per Block */

#define CONFIG_SYS_NAND_ONFI_DETECTION

#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x7) | \
					FTIM0_NAND_TWP(0x18)   | \
					FTIM0_NAND_TWCHT(0x7) | \
					FTIM0_NAND_TWH(0xa))
#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
					FTIM1_NAND_TWBE(0x39)  | \
					FTIM1_NAND_TRR(0xe)   | \
					FTIM1_NAND_TRP(0x18))
#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0xf) | \
					FTIM2_NAND_TREH(0xa) | \
					FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3           0x0

#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_MTD_NAND_VERIFY_WRITE

#define CONFIG_SYS_NAND_BLOCK_SIZE	(256 * 1024)
#endif

#ifdef CONFIG_NAND_BOOT
#define CONFIG_SPL_PAD_TO		0x40000		/* block aligned */
#define CONFIG_SYS_NAND_U_BOOT_OFFS	CONFIG_SPL_PAD_TO
#define CONFIG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
#endif

#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_QIXIS_I2C_ACCESS
#define CONFIG_SYS_I2C_EARLY_INIT
#endif

/*
 * QIXIS Definitions
 */
#define CONFIG_FSL_QIXIS

#ifdef CONFIG_FSL_QIXIS
#define QIXIS_BASE			0x7fb00000
#define QIXIS_BASE_PHYS			QIXIS_BASE
#define CONFIG_SYS_I2C_FPGA_ADDR	0x66
#define QIXIS_LBMAP_SWITCH		6
#define QIXIS_LBMAP_MASK		0x0f
#define QIXIS_LBMAP_SHIFT		0
#define QIXIS_LBMAP_DFLTBANK		0x00
#define QIXIS_LBMAP_ALTBANK		0x04
#define QIXIS_LBMAP_NAND		0x09
#define QIXIS_LBMAP_SD			0x00
#define QIXIS_LBMAP_SD_QSPI		0xff
#define QIXIS_LBMAP_QSPI		0xff
#define QIXIS_RCW_SRC_NAND		0x110
#define QIXIS_RCW_SRC_SD		0x040
#define QIXIS_RCW_SRC_QSPI		0x045
#define QIXIS_RST_CTL_RESET		0x41
#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08

#define CONFIG_SYS_FPGA_CSPR_EXT	(0x0)
#define CONFIG_SYS_FPGA_CSPR		(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
					CSPR_PORT_SIZE_8 | \
					CSPR_MSEL_GPCM | \
					CSPR_V)
#define CONFIG_SYS_FPGA_AMASK		IFC_AMASK(64 * 1024)
#define CONFIG_SYS_FPGA_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
					CSOR_NOR_NOR_MODE_AVD_NOR | \
					CSOR_NOR_TRHZ_80)

/*
 * QIXIS Timing parameters for IFC GPCM
 */
#define CONFIG_SYS_FPGA_FTIM0		(FTIM0_GPCM_TACSE(0xc) | \
					FTIM0_GPCM_TEADC(0x20) | \
					FTIM0_GPCM_TEAHC(0x10))
#define CONFIG_SYS_FPGA_FTIM1		(FTIM1_GPCM_TACO(0x50) | \
					FTIM1_GPCM_TRAD(0x1f))
#define CONFIG_SYS_FPGA_FTIM2		(FTIM2_GPCM_TCS(0x8) | \
					FTIM2_GPCM_TCH(0x8) | \
					FTIM2_GPCM_TWP(0xf0))
#define CONFIG_SYS_FPGA_FTIM3		0x0
#endif

#ifdef CONFIG_NAND_BOOT
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR1_CSPR_EXT
#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR1_CSPR
#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR3_EXT		CONFIG_SYS_FPGA_CSPR_EXT
#define CONFIG_SYS_CSPR3		CONFIG_SYS_FPGA_CSPR
#define CONFIG_SYS_AMASK3		CONFIG_SYS_FPGA_AMASK
#define CONFIG_SYS_CSOR3		CONFIG_SYS_FPGA_CSOR
#define CONFIG_SYS_CS3_FTIM0		CONFIG_SYS_FPGA_FTIM0
#define CONFIG_SYS_CS3_FTIM1		CONFIG_SYS_FPGA_FTIM1
#define CONFIG_SYS_CS3_FTIM2		CONFIG_SYS_FPGA_FTIM2
#define CONFIG_SYS_CS3_FTIM3		CONFIG_SYS_FPGA_FTIM3
#else
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR1_CSPR_EXT
#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR3_EXT		CONFIG_SYS_FPGA_CSPR_EXT
#define CONFIG_SYS_CSPR3		CONFIG_SYS_FPGA_CSPR
#define CONFIG_SYS_AMASK3		CONFIG_SYS_FPGA_AMASK
#define CONFIG_SYS_CSOR3		CONFIG_SYS_FPGA_CSOR
#define CONFIG_SYS_CS3_FTIM0		CONFIG_SYS_FPGA_FTIM0
#define CONFIG_SYS_CS3_FTIM1		CONFIG_SYS_FPGA_FTIM1
#define CONFIG_SYS_CS3_FTIM2		CONFIG_SYS_FPGA_FTIM2
#define CONFIG_SYS_CS3_FTIM3		CONFIG_SYS_FPGA_FTIM3
#endif

/*
 * I2C bus multiplexer
 */
#define I2C_MUX_PCA_ADDR_PRI		0x77
#define I2C_MUX_PCA_ADDR_SEC		0x76 /* Secondary multiplexer */
#define I2C_RETIMER_ADDR		0x18
#define I2C_MUX_CH_DEFAULT		0x8
#define I2C_MUX_CH_CH7301		0xC
#define I2C_MUX_CH5			0xD
#define I2C_MUX_CH6			0xE
#define I2C_MUX_CH7			0xF

#define I2C_MUX_CH_VOL_MONITOR 0xa

/* Voltage monitor on channel 2*/
#define I2C_VOL_MONITOR_ADDR           0x40
#define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
#define I2C_VOL_MONITOR_BUS_V_OVF      0x1
#define I2C_VOL_MONITOR_BUS_V_SHIFT    3

#define CONFIG_VID_FLS_ENV		"ls1046aqds_vdd_mv"
#ifndef CONFIG_SPL_BUILD
#define CONFIG_VID
#endif
#define CONFIG_VOL_MONITOR_IR36021_SET
#define CONFIG_VOL_MONITOR_INA220
/* The lowest and highest voltage allowed for LS1046AQDS */
#define VDD_MV_MIN			819
#define VDD_MV_MAX			1212

/*
 * Miscellaneous configurable options
 */
#define CONFIG_MISC_INIT_R

#define CONFIG_SYS_MEMTEST_START	0x80000000
#define CONFIG_SYS_MEMTEST_END		0x9fffffff

#define CONFIG_SYS_HZ			1000

#define CONFIG_SYS_INIT_SP_OFFSET \
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)

#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */

/*
 * Environment
 */
#define CONFIG_ENV_OVERWRITE

#ifdef CONFIG_NAND_BOOT
#define CONFIG_ENV_SIZE			0x2000
#define CONFIG_ENV_OFFSET		(12 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SD_BOOT)
#define CONFIG_ENV_OFFSET		(3 * 1024 * 1024)
#define CONFIG_SYS_MMC_ENV_DEV		0
#define CONFIG_ENV_SIZE			0x2000
#elif defined(CONFIG_QSPI_BOOT)
#define CONFIG_ENV_SIZE			0x2000          /* 8KB */
#define CONFIG_ENV_OFFSET		0x300000        /* 3MB */
#define CONFIG_ENV_SECT_SIZE		0x10000
#else
#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x300000)
#define CONFIG_ENV_SECT_SIZE		0x20000
#define CONFIG_ENV_SIZE			0x20000
#endif

#define CONFIG_CMDLINE_TAG

#undef CONFIG_BOOTCOMMAND
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_BOOTCOMMAND		"sf probe && sf read $kernel_load "    \
					"e0000 f00000 && bootm $kernel_load"
#else
#define CONFIG_BOOTCOMMAND		"cp.b $kernel_start $kernel_load "     \
					"$kernel_size && bootm $kernel_load"
#endif

#include <asm/fsl_secure_boot.h>

#endif /* __LS1046AQDS_H__ */
Commit	Line	Data
126fe70d SX	1	/*
	2	* Copyright 2016 Freescale Semiconductor, Inc.
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#ifndef __LS1046AQDS_H__
	8	#define __LS1046AQDS_H__
	9
	10	#include "ls1046a_common.h"
	11
126fe70d SX	12	#ifndef __ASSEMBLY__
	13	unsigned long get_board_sys_clk(void);
	14	unsigned long get_board_ddr_clk(void);
	15	#endif
	16
	17	#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
	18	#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
	19
	20	#define CONFIG_SKIP_LOWLEVEL_INIT
	21
	22	#define CONFIG_LAYERSCAPE_NS_ACCESS
	23
	24	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
	25	/* Physical Memory Map */
	26	#define CONFIG_CHIP_SELECTS_PER_CTRL 4
	27	#define CONFIG_NR_DRAM_BANKS 2
	28
	29	#define CONFIG_DDR_SPD
	30	#define SPD_EEPROM_ADDRESS 0x51
	31	#define CONFIG_SYS_SPD_BUS_NUM 0
	32
dc760aed	33	#ifndef CONFIG_SPL
126fe70d	34	#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
dc760aed	35	#endif
126fe70d SX	36
	37	#define CONFIG_DDR_ECC
	38	#ifdef CONFIG_DDR_ECC
	39	#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
	40	#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
	41	#endif
	42
126fe70d SX	43	/* DSPI */
	44	#ifdef CONFIG_FSL_DSPI
	45	#define CONFIG_SPI_FLASH_STMICRO /* cs0 */
	46	#define CONFIG_SPI_FLASH_SST /* cs1 */
	47	#define CONFIG_SPI_FLASH_EON /* cs2 */
	48	#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
	49	#define CONFIG_SF_DEFAULT_BUS 1
	50	#define CONFIG_SF_DEFAULT_CS 0
	51	#endif
	52	#endif
	53
	54	/* QSPI */
	55	#if defined(CONFIG_QSPI_BOOT) \|\| defined(CONFIG_SD_BOOT_QSPI)
	56	#ifdef CONFIG_FSL_QSPI
	57	#define CONFIG_SPI_FLASH_SPANSION
	58	#define FSL_QSPI_FLASH_SIZE (1 << 24)
	59	#define FSL_QSPI_FLASH_NUM 2
	60	#endif
	61	#endif
	62
	63	#ifdef CONFIG_SYS_DPAA_FMAN
	64	#define CONFIG_FMAN_ENET
126fe70d SX	65	#define CONFIG_PHY_VITESSE
	66	#define CONFIG_PHY_REALTEK
	67	#define CONFIG_PHYLIB_10G
	68	#define RGMII_PHY1_ADDR 0x1
	69	#define RGMII_PHY2_ADDR 0x2
	70	#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
	71	#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
	72	#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
	73	#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
	74	/* PHY address on QSGMII riser card on slot 2 */
	75	#define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
	76	#define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
	77	#define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
	78	#define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
	79	#endif
	80
	81	#ifdef CONFIG_RAMBOOT_PBL
	82	#define CONFIG_SYS_FSL_PBL_PBI \
	83	board/freescale/ls1046aqds/ls1046aqds_pbi.cfg
	84	#endif
	85
	86	#ifdef CONFIG_NAND_BOOT
	87	#define CONFIG_SYS_FSL_PBL_RCW \
	88	board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg
	89	#endif
	90
	91	#ifdef CONFIG_SD_BOOT
	92	#ifdef CONFIG_SD_BOOT_QSPI
	93	#define CONFIG_SYS_FSL_PBL_RCW \
	94	board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg
	95	#else
	96	#define CONFIG_SYS_FSL_PBL_RCW \
	97	board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg
	98	#endif
	99	#endif
	100
	101	/* IFC */
	102	#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
	103	#define CONFIG_FSL_IFC
	104	/*
	105	* CONFIG_SYS_FLASH_BASE has the final address (core view)
	106	* CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
	107	* CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
	108	* CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
	109	*/
	110	#define CONFIG_SYS_FLASH_BASE 0x60000000
	111	#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
	112	#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
	113
e856bdcf	114	#ifdef CONFIG_MTD_NOR_FLASH
126fe70d SX	115	#define CONFIG_FLASH_CFI_DRIVER
	116	#define CONFIG_SYS_FLASH_CFI
	117	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
	118	#define CONFIG_SYS_FLASH_QUIET_TEST
	119	#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
	120	#endif
	121	#endif
	122
fdc2b54c SX	123	/* LPUART */
	124	#ifdef CONFIG_LPUART
	125	#define CONFIG_LPUART_32B_REG
	126	#define CFG_UART_MUX_MASK 0x6
	127	#define CFG_UART_MUX_SHIFT 1
	128	#define CFG_LPUART_EN 0x2
	129	#endif
	130
126fe70d SX	131	/* EEPROM */
	132	#define CONFIG_ID_EEPROM
	133	#define CONFIG_SYS_I2C_EEPROM_NXID
	134	#define CONFIG_SYS_EEPROM_BUS_NUM 0
	135	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
	136	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	137	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	138	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
	139
126fe70d SX	140	/*
	141	* IFC Definitions
	142	*/
	143	#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
	144	#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
	145	#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \| \
	146	CSPR_PORT_SIZE_16 \| \
	147	CSPR_MSEL_NOR \| \
	148	CSPR_V)
	149	#define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
	150	#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
	151	+ 0x8000000) \| \
	152	CSPR_PORT_SIZE_16 \| \
	153	CSPR_MSEL_NOR \| \
	154	CSPR_V)
	155	#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
	156
	157	#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) \| \
	158	CSOR_NOR_TRHZ_80)
	159	#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) \| \
	160	FTIM0_NOR_TEADC(0x5) \| \
1b7910a3	161	FTIM0_NOR_TAVDS(0x6) \| \
126fe70d SX	162	FTIM0_NOR_TEAHC(0x5))
	163	#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) \| \
	164	FTIM1_NOR_TRAD_NOR(0x1a) \| \
	165	FTIM1_NOR_TSEQRAD_NOR(0x13))
1b7910a3 YS	166	#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) \| \
1b7910a3 YS	167	FTIM2_NOR_TCH(0x8) \| \
126fe70d SX	168	FTIM2_NOR_TWPH(0xe) \| \
	169	FTIM2_NOR_TWP(0x1c))
	170	#define CONFIG_SYS_NOR_FTIM3 0
	171
	172	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
	173	#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
	174	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	175	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
	176
	177	#define CONFIG_SYS_FLASH_EMPTY_INFO
	178	#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
	179	CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
	180
	181	#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
	182	#define CONFIG_SYS_WRITE_SWAPPED_DATA
	183
	184	/*
	185	* NAND Flash Definitions
	186	*/
	187	#define CONFIG_NAND_FSL_IFC
	188
	189	#define CONFIG_SYS_NAND_BASE 0x7e800000
	190	#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
	191
	192	#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
	193
	194	#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
	195	\| CSPR_PORT_SIZE_8 \
	196	\| CSPR_MSEL_NAND \
	197	\| CSPR_V)
	198	#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
	199	#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
	200	\| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
	201	\| CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \
	202	\| CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
	203	\| CSOR_NAND_PGS_4K /* Page Size = 4K */ \
	204	\| CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
	205	\| CSOR_NAND_PB(64)) /* 64 Pages Per Block */
	206
	207	#define CONFIG_SYS_NAND_ONFI_DETECTION
	208
	209	#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) \| \
	210	FTIM0_NAND_TWP(0x18) \| \
	211	FTIM0_NAND_TWCHT(0x7) \| \
	212	FTIM0_NAND_TWH(0xa))
	213	#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) \| \
	214	FTIM1_NAND_TWBE(0x39) \| \
	215	FTIM1_NAND_TRR(0xe) \| \
	216	FTIM1_NAND_TRP(0x18))
	217	#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) \| \
	218	FTIM2_NAND_TREH(0xa) \| \
	219	FTIM2_NAND_TWHRE(0x1e))
	220	#define CONFIG_SYS_NAND_FTIM3 0x0
	221
	222	#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
	223	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	224	#define CONFIG_MTD_NAND_VERIFY_WRITE
126fe70d SX	225
	226	#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
	227	#endif
	228
	229	#ifdef CONFIG_NAND_BOOT
	230	#define CONFIG_SPL_PAD_TO 0x40000 /* block aligned */
	231	#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
	232	#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
	233	#endif
	234
	235	#if defined(CONFIG_QSPI_BOOT) \|\| defined(CONFIG_SD_BOOT_QSPI)
	236	#define CONFIG_QIXIS_I2C_ACCESS
	237	#define CONFIG_SYS_I2C_EARLY_INIT
126fe70d SX	238	#endif
	239
	240	/*
	241	* QIXIS Definitions
	242	*/
	243	#define CONFIG_FSL_QIXIS
	244
	245	#ifdef CONFIG_FSL_QIXIS
	246	#define QIXIS_BASE 0x7fb00000
	247	#define QIXIS_BASE_PHYS QIXIS_BASE
	248	#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
	249	#define QIXIS_LBMAP_SWITCH 6
	250	#define QIXIS_LBMAP_MASK 0x0f
	251	#define QIXIS_LBMAP_SHIFT 0
	252	#define QIXIS_LBMAP_DFLTBANK 0x00
	253	#define QIXIS_LBMAP_ALTBANK 0x04
	254	#define QIXIS_LBMAP_NAND 0x09
	255	#define QIXIS_LBMAP_SD 0x00
	256	#define QIXIS_LBMAP_SD_QSPI 0xff
	257	#define QIXIS_LBMAP_QSPI 0xff
	258	#define QIXIS_RCW_SRC_NAND 0x110
	259	#define QIXIS_RCW_SRC_SD 0x040
	260	#define QIXIS_RCW_SRC_QSPI 0x045
	261	#define QIXIS_RST_CTL_RESET 0x41
	262	#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
	263	#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
	264	#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
	265
	266	#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
	267	#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \| \
	268	CSPR_PORT_SIZE_8 \| \
	269	CSPR_MSEL_GPCM \| \
	270	CSPR_V)
	271	#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
	272	#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) \| \
	273	CSOR_NOR_NOR_MODE_AVD_NOR \| \
	274	CSOR_NOR_TRHZ_80)
	275
	276	/*
	277	* QIXIS Timing parameters for IFC GPCM
	278	*/
	279	#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) \| \
	280	FTIM0_GPCM_TEADC(0x20) \| \
	281	FTIM0_GPCM_TEAHC(0x10))
	282	#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) \| \
	283	FTIM1_GPCM_TRAD(0x1f))
	284	#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) \| \
	285	FTIM2_GPCM_TCH(0x8) \| \
	286	FTIM2_GPCM_TWP(0xf0))
	287	#define CONFIG_SYS_FPGA_FTIM3 0x0
	288	#endif
	289
	290	#ifdef CONFIG_NAND_BOOT
	291	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
	292	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
	293	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
	294	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
	295	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
	296	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
	297	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
	298	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
	299	#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
	300	#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
	301	#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
302	#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
303	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
304	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
305	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
306	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
307	#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
308	#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
309	#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
310	#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
311	#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
312	#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
313	#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
314	#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
315	#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
316	#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
317	#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
318	#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
319	#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
320	#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
321	#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
322	#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
323	#else
324	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
325	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
326	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
327	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
328	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
329	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
330	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
331	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
332	#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
333	#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
334	#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
335	#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
336	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
337	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
338	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
339	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
340	#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
341	#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
342	#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
343	#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
344	#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
345	#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
346	#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
347	#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
348	#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
349	#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
350	#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
351	#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
352	#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
353	#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
354	#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
355	#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
356	#endif
357
358	/*
359	* I2C bus multiplexer
360	*/
361	#define I2C_MUX_PCA_ADDR_PRI 0x77
362	#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
363	#define I2C_RETIMER_ADDR 0x18
364	#define I2C_MUX_CH_DEFAULT 0x8
365	#define I2C_MUX_CH_CH7301 0xC
366	#define I2C_MUX_CH5 0xD
367	#define I2C_MUX_CH6 0xE
368	#define I2C_MUX_CH7 0xF
369
370	#define I2C_MUX_CH_VOL_MONITOR 0xa
371
372	/* Voltage monitor on channel 2*/
373	#define I2C_VOL_MONITOR_ADDR 0x40
374	#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
375	#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
376	#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
377
378	#define CONFIG_VID_FLS_ENV "ls1046aqds_vdd_mv"
379	#ifndef CONFIG_SPL_BUILD
380	#define CONFIG_VID
381	#endif
382	#define CONFIG_VOL_MONITOR_IR36021_SET
383	#define CONFIG_VOL_MONITOR_INA220
384	/* The lowest and highest voltage allowed for LS1046AQDS */
385	#define VDD_MV_MIN 819
386	#define VDD_MV_MAX 1212
387
388	/*
389	* Miscellaneous configurable options
390	*/
391	#define CONFIG_MISC_INIT_R
126fe70d SX	392
	393	#define CONFIG_SYS_MEMTEST_START 0x80000000
	394	#define CONFIG_SYS_MEMTEST_END 0x9fffffff
	395
	396	#define CONFIG_SYS_HZ 1000
	397
126fe70d SX	398	#define CONFIG_SYS_INIT_SP_OFFSET \
	399	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	400
	401	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
	402
	403	/*
	404	* Environment
	405	*/
	406	#define CONFIG_ENV_OVERWRITE
	407
	408	#ifdef CONFIG_NAND_BOOT
126fe70d	409	#define CONFIG_ENV_SIZE 0x2000
752513d8	410	#define CONFIG_ENV_OFFSET (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
126fe70d	411	#elif defined(CONFIG_SD_BOOT)
8104deb2	412	#define CONFIG_ENV_OFFSET (3 * 1024 * 1024)
126fe70d SX	413	#define CONFIG_SYS_MMC_ENV_DEV 0
	414	#define CONFIG_ENV_SIZE 0x2000
	415	#elif defined(CONFIG_QSPI_BOOT)
126fe70d	416	#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
8104deb2	417	#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
126fe70d SX	418	#define CONFIG_ENV_SECT_SIZE 0x10000
126fe70d SX	419	#else
8104deb2	420	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
126fe70d SX	421	#define CONFIG_ENV_SECT_SIZE 0x20000
	422	#define CONFIG_ENV_SIZE 0x20000
	423	#endif
	424
	425	#define CONFIG_CMDLINE_TAG
	426
8de227ee	427	#undef CONFIG_BOOTCOMMAND
126fe70d SX	428	#if defined(CONFIG_QSPI_BOOT) \|\| defined(CONFIG_SD_BOOT_QSPI)
	429	#define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load " \
	430	"e0000 f00000 && bootm $kernel_load"
	431	#else
	432	#define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \
	433	"$kernel_size && bootm $kernel_load"
	434	#endif
	435
126fe70d SX	436	#include <asm/fsl_secure_boot.h>
	437
	438	#endif /* __LS1046AQDS_H__ */