[people/ms/u-boot.git] / include / configs / ls1046aqds.h

/*
 * Copyright 2016 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __LS1046AQDS_H__
#define __LS1046AQDS_H__

#include "ls1046a_common.h"

#if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT)
#define CONFIG_SYS_TEXT_BASE		0x82000000
#elif defined(CONFIG_QSPI_BOOT)
#define CONFIG_SYS_TEXT_BASE		0x40010000
#else
#define CONFIG_SYS_TEXT_BASE		0x60100000
#endif

#ifndef __ASSEMBLY__
unsigned long get_board_sys_clk(void);
unsigned long get_board_ddr_clk(void);
#endif

#define CONFIG_SYS_CLK_FREQ		get_board_sys_clk()
#define CONFIG_DDR_CLK_FREQ		get_board_ddr_clk()

#define CONFIG_SKIP_LOWLEVEL_INIT

#define CONFIG_LAYERSCAPE_NS_ACCESS

#define CONFIG_DIMM_SLOTS_PER_CTLR	1
/* Physical Memory Map */
#define CONFIG_CHIP_SELECTS_PER_CTRL	4
#define CONFIG_NR_DRAM_BANKS		2

#define CONFIG_DDR_SPD
#define SPD_EEPROM_ADDRESS		0x51
#define CONFIG_SYS_SPD_BUS_NUM		0

#define CONFIG_FSL_DDR_INTERACTIVE	/* Interactive debugging */

#define CONFIG_DDR_ECC
#ifdef CONFIG_DDR_ECC
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE           0xdeadbeef
#endif

/* DSPI */
#ifdef CONFIG_FSL_DSPI
#define CONFIG_SPI_FLASH_STMICRO	/* cs0 */
#define CONFIG_SPI_FLASH_SST		/* cs1 */
#define CONFIG_SPI_FLASH_EON		/* cs2 */
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_SF_DEFAULT_BUS		1
#define CONFIG_SF_DEFAULT_CS		0
#endif
#endif

/* QSPI */
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#ifdef CONFIG_FSL_QSPI
#define CONFIG_SPI_FLASH_SPANSION
#define FSL_QSPI_FLASH_SIZE		(1 << 24)
#define FSL_QSPI_FLASH_NUM		2
#endif
#endif

#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_FMAN_ENET
#define CONFIG_PHYLIB
#define CONFIG_PHY_VITESSE
#define CONFIG_PHY_REALTEK
#define CONFIG_PHYLIB_10G
#define RGMII_PHY1_ADDR		0x1
#define RGMII_PHY2_ADDR		0x2
#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
/* PHY address on QSGMII riser card on slot 2 */
#define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
#define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
#define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
#define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
#endif

#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_SYS_FSL_PBL_PBI \
	board/freescale/ls1046aqds/ls1046aqds_pbi.cfg
#endif

#ifdef CONFIG_NAND_BOOT
#define CONFIG_SYS_FSL_PBL_RCW \
	board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg
#endif

#ifdef CONFIG_SD_BOOT
#ifdef CONFIG_SD_BOOT_QSPI
#define CONFIG_SYS_FSL_PBL_RCW \
	board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg
#else
#define CONFIG_SYS_FSL_PBL_RCW \
	board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg
#endif
#endif

/* IFC */
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
#define	CONFIG_FSL_IFC
/*
 * CONFIG_SYS_FLASH_BASE has the final address (core view)
 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
 */
#define CONFIG_SYS_FLASH_BASE			0x60000000
#define CONFIG_SYS_FLASH_BASE_PHYS		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY	0x00000000

#ifndef CONFIG_SYS_NO_FLASH
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS	45	/* count down from 45/5: 9..1 */
#endif
#endif

/* SATA */
#define CONFIG_LIBATA
#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SCSI
#define CONFIG_DOS_PARTITION
#define CONFIG_BOARD_LATE_INIT

/* EEPROM */
#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM		0
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x57
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5

#define CONFIG_SYS_SATA				AHCI_BASE_ADDR

#define CONFIG_SYS_SCSI_MAX_SCSI_ID		1
#define CONFIG_SYS_SCSI_MAX_LUN			1
#define CONFIG_SYS_SCSI_MAX_DEVICE		(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
						CONFIG_SYS_SCSI_MAX_LUN)

/*
 * IFC Definitions
 */
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
				CSPR_PORT_SIZE_16 | \
				CSPR_MSEL_NOR | \
				CSPR_V)
#define CONFIG_SYS_NOR1_CSPR_EXT	(0x0)
#define CONFIG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
				+ 0x8000000) | \
				CSPR_PORT_SIZE_16 | \
				CSPR_MSEL_NOR | \
				CSPR_V)
#define CONFIG_SYS_NOR_AMASK		IFC_AMASK(128 * 1024 * 1024)

#define CONFIG_SYS_NOR_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
					CSOR_NOR_TRHZ_80)
#define CONFIG_SYS_NOR_FTIM0		(FTIM0_NOR_TACSE(0x4) | \
					FTIM0_NOR_TEADC(0x5) | \
					FTIM0_NOR_TEAHC(0x5))
#define CONFIG_SYS_NOR_FTIM1		(FTIM1_NOR_TACO(0x35) | \
					FTIM1_NOR_TRAD_NOR(0x1a) | \
					FTIM1_NOR_TSEQRAD_NOR(0x13))
#define CONFIG_SYS_NOR_FTIM2		(FTIM2_NOR_TCS(0x4) | \
					FTIM2_NOR_TCH(0x4) | \
					FTIM2_NOR_TWPH(0xe) | \
					FTIM2_NOR_TWP(0x1c))
#define CONFIG_SYS_NOR_FTIM3		0

#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS, \
					CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}

#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
#define CONFIG_SYS_WRITE_SWAPPED_DATA

/*
 * NAND Flash Definitions
 */
#define CONFIG_NAND_FSL_IFC

#define CONFIG_SYS_NAND_BASE		0x7e800000
#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE

#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)

#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
				| CSPR_PORT_SIZE_8	\
				| CSPR_MSEL_NAND	\
				| CSPR_V)
#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
				| CSOR_NAND_ECC_MODE_8	/* 8-bit ECC */ \
				| CSOR_NAND_RAL_3	/* RAL = 3 Bytes */ \
				| CSOR_NAND_PGS_4K	/* Page Size = 4K */ \
				| CSOR_NAND_SPRZ_224	/* Spare size = 224 */ \
				| CSOR_NAND_PB(64))	/* 64 Pages Per Block */

#define CONFIG_SYS_NAND_ONFI_DETECTION

#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x7) | \
					FTIM0_NAND_TWP(0x18)   | \
					FTIM0_NAND_TWCHT(0x7) | \
					FTIM0_NAND_TWH(0xa))
#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
					FTIM1_NAND_TWBE(0x39)  | \
					FTIM1_NAND_TRR(0xe)   | \
					FTIM1_NAND_TRP(0x18))
#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0xf) | \
					FTIM2_NAND_TREH(0xa) | \
					FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3           0x0

#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND

#define CONFIG_SYS_NAND_BLOCK_SIZE	(256 * 1024)
#endif

#ifdef CONFIG_NAND_BOOT
#define CONFIG_SPL_PAD_TO		0x40000		/* block aligned */
#define CONFIG_SYS_NAND_U_BOOT_OFFS	CONFIG_SPL_PAD_TO
#define CONFIG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
#endif

#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_QIXIS_I2C_ACCESS
#define CONFIG_SYS_I2C_EARLY_INIT
#define CONFIG_SYS_NO_FLASH
#endif

/*
 * QIXIS Definitions
 */
#define CONFIG_FSL_QIXIS

#ifdef CONFIG_FSL_QIXIS
#define QIXIS_BASE			0x7fb00000
#define QIXIS_BASE_PHYS			QIXIS_BASE
#define CONFIG_SYS_I2C_FPGA_ADDR	0x66
#define QIXIS_LBMAP_SWITCH		6
#define QIXIS_LBMAP_MASK		0x0f
#define QIXIS_LBMAP_SHIFT		0
#define QIXIS_LBMAP_DFLTBANK		0x00
#define QIXIS_LBMAP_ALTBANK		0x04
#define QIXIS_LBMAP_NAND		0x09
#define QIXIS_LBMAP_SD			0x00
#define QIXIS_LBMAP_SD_QSPI		0xff
#define QIXIS_LBMAP_QSPI		0xff
#define QIXIS_RCW_SRC_NAND		0x110
#define QIXIS_RCW_SRC_SD		0x040
#define QIXIS_RCW_SRC_QSPI		0x045
#define QIXIS_RST_CTL_RESET		0x41
#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08

#define CONFIG_SYS_FPGA_CSPR_EXT	(0x0)
#define CONFIG_SYS_FPGA_CSPR		(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
					CSPR_PORT_SIZE_8 | \
					CSPR_MSEL_GPCM | \
					CSPR_V)
#define CONFIG_SYS_FPGA_AMASK		IFC_AMASK(64 * 1024)
#define CONFIG_SYS_FPGA_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
					CSOR_NOR_NOR_MODE_AVD_NOR | \
					CSOR_NOR_TRHZ_80)

/*
 * QIXIS Timing parameters for IFC GPCM
 */
#define CONFIG_SYS_FPGA_FTIM0		(FTIM0_GPCM_TACSE(0xc) | \
					FTIM0_GPCM_TEADC(0x20) | \
					FTIM0_GPCM_TEAHC(0x10))
#define CONFIG_SYS_FPGA_FTIM1		(FTIM1_GPCM_TACO(0x50) | \
					FTIM1_GPCM_TRAD(0x1f))
#define CONFIG_SYS_FPGA_FTIM2		(FTIM2_GPCM_TCS(0x8) | \
					FTIM2_GPCM_TCH(0x8) | \
					FTIM2_GPCM_TWP(0xf0))
#define CONFIG_SYS_FPGA_FTIM3		0x0
#endif

#ifdef CONFIG_NAND_BOOT
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR1_CSPR_EXT
#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR1_CSPR
#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR3_EXT		CONFIG_SYS_FPGA_CSPR_EXT
#define CONFIG_SYS_CSPR3		CONFIG_SYS_FPGA_CSPR
#define CONFIG_SYS_AMASK3		CONFIG_SYS_FPGA_AMASK
#define CONFIG_SYS_CSOR3		CONFIG_SYS_FPGA_CSOR
#define CONFIG_SYS_CS3_FTIM0		CONFIG_SYS_FPGA_FTIM0
#define CONFIG_SYS_CS3_FTIM1		CONFIG_SYS_FPGA_FTIM1
#define CONFIG_SYS_CS3_FTIM2		CONFIG_SYS_FPGA_FTIM2
#define CONFIG_SYS_CS3_FTIM3		CONFIG_SYS_FPGA_FTIM3
#else
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR1_CSPR_EXT
#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR3_EXT		CONFIG_SYS_FPGA_CSPR_EXT
#define CONFIG_SYS_CSPR3		CONFIG_SYS_FPGA_CSPR
#define CONFIG_SYS_AMASK3		CONFIG_SYS_FPGA_AMASK
#define CONFIG_SYS_CSOR3		CONFIG_SYS_FPGA_CSOR
#define CONFIG_SYS_CS3_FTIM0		CONFIG_SYS_FPGA_FTIM0
#define CONFIG_SYS_CS3_FTIM1		CONFIG_SYS_FPGA_FTIM1
#define CONFIG_SYS_CS3_FTIM2		CONFIG_SYS_FPGA_FTIM2
#define CONFIG_SYS_CS3_FTIM3		CONFIG_SYS_FPGA_FTIM3
#endif

/*
 * I2C bus multiplexer
 */
#define I2C_MUX_PCA_ADDR_PRI		0x77
#define I2C_MUX_PCA_ADDR_SEC		0x76 /* Secondary multiplexer */
#define I2C_RETIMER_ADDR		0x18
#define I2C_MUX_CH_DEFAULT		0x8
#define I2C_MUX_CH_CH7301		0xC
#define I2C_MUX_CH5			0xD
#define I2C_MUX_CH6			0xE
#define I2C_MUX_CH7			0xF

#define I2C_MUX_CH_VOL_MONITOR 0xa

/* Voltage monitor on channel 2*/
#define I2C_VOL_MONITOR_ADDR           0x40
#define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
#define I2C_VOL_MONITOR_BUS_V_OVF      0x1
#define I2C_VOL_MONITOR_BUS_V_SHIFT    3

#define CONFIG_VID_FLS_ENV		"ls1046aqds_vdd_mv"
#ifndef CONFIG_SPL_BUILD
#define CONFIG_VID
#endif
#define CONFIG_VOL_MONITOR_IR36021_SET
#define CONFIG_VOL_MONITOR_INA220
/* The lowest and highest voltage allowed for LS1046AQDS */
#define VDD_MV_MIN			819
#define VDD_MV_MAX			1212

/*
 * Miscellaneous configurable options
 */
#define CONFIG_MISC_INIT_R
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_PBSIZE		\
		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE

#define CONFIG_SYS_MEMTEST_START	0x80000000
#define CONFIG_SYS_MEMTEST_END		0x9fffffff

#define CONFIG_SYS_HZ			1000

/*
 * Stack sizes
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE		(30 * 1024)

#define CONFIG_SYS_INIT_SP_OFFSET \
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)

#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */

/*
 * Environment
 */
#define CONFIG_ENV_OVERWRITE

#ifdef CONFIG_NAND_BOOT
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE			0x2000
#define CONFIG_ENV_OFFSET		(5 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SD_BOOT)
#define CONFIG_ENV_OFFSET		(1024 * 1024)
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV		0
#define CONFIG_ENV_SIZE			0x2000
#elif defined(CONFIG_QSPI_BOOT)
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SIZE			0x2000          /* 8KB */
#define CONFIG_ENV_OFFSET		0x100000        /* 1MB */
#define CONFIG_ENV_SECT_SIZE		0x10000
#else
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x200000)
#define CONFIG_ENV_SECT_SIZE		0x20000
#define CONFIG_ENV_SIZE			0x20000
#endif

#define CONFIG_CMDLINE_TAG

#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_BOOTCOMMAND		"sf probe && sf read $kernel_load "    \
					"e0000 f00000 && bootm $kernel_load"
#else
#define CONFIG_BOOTCOMMAND		"cp.b $kernel_start $kernel_load "     \
					"$kernel_size && bootm $kernel_load"
#endif

#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define MTDPARTS_DEFAULT "mtdparts=1550000.quadspi:2m(uboot)," \
			"14m(free)"
#else
#define MTDPARTS_DEFAULT "mtdparts=60000000.nor:1m(nor_bank0_rcw)," \
			"1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \
			"1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \
			"1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \
			"1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \
			"40m(nor_bank4_fit);7e800000.flash:" \
			"4m(nand_uboot),36m(nand_kernel)," \
			"472m(nand_free);spi0.0:2m(uboot)," \
			"14m(free)"
#endif

#include <asm/fsl_secure_boot.h>

#endif /* __LS1046AQDS_H__ */
Commit	Line	Data
126fe70d SX	1	/*
	2	* Copyright 2016 Freescale Semiconductor, Inc.
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#ifndef __LS1046AQDS_H__
	8	#define __LS1046AQDS_H__
	9
	10	#include "ls1046a_common.h"
	11
126fe70d SX	12	#if defined(CONFIG_NAND_BOOT) \|\| defined(CONFIG_SD_BOOT)
	13	#define CONFIG_SYS_TEXT_BASE 0x82000000
	14	#elif defined(CONFIG_QSPI_BOOT)
	15	#define CONFIG_SYS_TEXT_BASE 0x40010000
	16	#else
	17	#define CONFIG_SYS_TEXT_BASE 0x60100000
	18	#endif
	19
	20	#ifndef __ASSEMBLY__
	21	unsigned long get_board_sys_clk(void);
	22	unsigned long get_board_ddr_clk(void);
	23	#endif
	24
	25	#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
	26	#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
	27
	28	#define CONFIG_SKIP_LOWLEVEL_INIT
	29
	30	#define CONFIG_LAYERSCAPE_NS_ACCESS
	31
	32	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
	33	/* Physical Memory Map */
	34	#define CONFIG_CHIP_SELECTS_PER_CTRL 4
	35	#define CONFIG_NR_DRAM_BANKS 2
	36
	37	#define CONFIG_DDR_SPD
	38	#define SPD_EEPROM_ADDRESS 0x51
	39	#define CONFIG_SYS_SPD_BUS_NUM 0
	40
	41	#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
	42
	43	#define CONFIG_DDR_ECC
	44	#ifdef CONFIG_DDR_ECC
	45	#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
	46	#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
	47	#endif
	48
126fe70d SX	49	/* DSPI */
	50	#ifdef CONFIG_FSL_DSPI
	51	#define CONFIG_SPI_FLASH_STMICRO /* cs0 */
	52	#define CONFIG_SPI_FLASH_SST /* cs1 */
	53	#define CONFIG_SPI_FLASH_EON /* cs2 */
	54	#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
	55	#define CONFIG_SF_DEFAULT_BUS 1
	56	#define CONFIG_SF_DEFAULT_CS 0
	57	#endif
	58	#endif
	59
	60	/* QSPI */
	61	#if defined(CONFIG_QSPI_BOOT) \|\| defined(CONFIG_SD_BOOT_QSPI)
	62	#ifdef CONFIG_FSL_QSPI
	63	#define CONFIG_SPI_FLASH_SPANSION
	64	#define FSL_QSPI_FLASH_SIZE (1 << 24)
	65	#define FSL_QSPI_FLASH_NUM 2
	66	#endif
	67	#endif
	68
	69	#ifdef CONFIG_SYS_DPAA_FMAN
	70	#define CONFIG_FMAN_ENET
	71	#define CONFIG_PHYLIB
	72	#define CONFIG_PHY_VITESSE
	73	#define CONFIG_PHY_REALTEK
	74	#define CONFIG_PHYLIB_10G
	75	#define RGMII_PHY1_ADDR 0x1
	76	#define RGMII_PHY2_ADDR 0x2
	77	#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
	78	#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
	79	#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
	80	#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
	81	/* PHY address on QSGMII riser card on slot 2 */
	82	#define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
	83	#define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
	84	#define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
	85	#define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
	86	#endif
	87
	88	#ifdef CONFIG_RAMBOOT_PBL
	89	#define CONFIG_SYS_FSL_PBL_PBI \
	90	board/freescale/ls1046aqds/ls1046aqds_pbi.cfg
	91	#endif
	92
	93	#ifdef CONFIG_NAND_BOOT
	94	#define CONFIG_SYS_FSL_PBL_RCW \
	95	board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg
	96	#endif
	97
	98	#ifdef CONFIG_SD_BOOT
	99	#ifdef CONFIG_SD_BOOT_QSPI
	100	#define CONFIG_SYS_FSL_PBL_RCW \
	101	board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg
	102	#else
	103	#define CONFIG_SYS_FSL_PBL_RCW \
	104	board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg
	105	#endif
	106	#endif
	107
	108	/* IFC */
	109	#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
	110	#define CONFIG_FSL_IFC
	111	/*
	112	* CONFIG_SYS_FLASH_BASE has the final address (core view)
113	* CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
114	* CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
115	* CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
116	*/
117	#define CONFIG_SYS_FLASH_BASE 0x60000000
118	#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
119	#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
120
121	#ifndef CONFIG_SYS_NO_FLASH
122	#define CONFIG_FLASH_CFI_DRIVER
123	#define CONFIG_SYS_FLASH_CFI
124	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
125	#define CONFIG_SYS_FLASH_QUIET_TEST
126	#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
127	#endif
128	#endif
129
130	/* SATA */
131	#define CONFIG_LIBATA
132	#define CONFIG_SCSI_AHCI
133	#define CONFIG_SCSI_AHCI_PLAT
134	#define CONFIG_SCSI
135	#define CONFIG_DOS_PARTITION
136	#define CONFIG_BOARD_LATE_INIT
137
138	/* EEPROM */
139	#define CONFIG_ID_EEPROM
140	#define CONFIG_SYS_I2C_EEPROM_NXID
141	#define CONFIG_SYS_EEPROM_BUS_NUM 0
142	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
143	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
144	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
145	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
146
147	#define CONFIG_SYS_SATA AHCI_BASE_ADDR
148
149	#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
150	#define CONFIG_SYS_SCSI_MAX_LUN 1
151	#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
152	CONFIG_SYS_SCSI_MAX_LUN)
153
154	/*
155	* IFC Definitions
156	*/
157	#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
158	#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
159	#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \| \
160	CSPR_PORT_SIZE_16 \| \
161	CSPR_MSEL_NOR \| \
162	CSPR_V)
163	#define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
164	#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
165	+ 0x8000000) \| \
166	CSPR_PORT_SIZE_16 \| \
167	CSPR_MSEL_NOR \| \
168	CSPR_V)
169	#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
170
171	#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) \| \
172	CSOR_NOR_TRHZ_80)
173	#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) \| \
174	FTIM0_NOR_TEADC(0x5) \| \
175	FTIM0_NOR_TEAHC(0x5))
176	#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) \| \
177	FTIM1_NOR_TRAD_NOR(0x1a) \| \
178	FTIM1_NOR_TSEQRAD_NOR(0x13))
179	#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) \| \
180	FTIM2_NOR_TCH(0x4) \| \
181	FTIM2_NOR_TWPH(0xe) \| \
182	FTIM2_NOR_TWP(0x1c))
183	#define CONFIG_SYS_NOR_FTIM3 0
184
185	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
186	#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
187	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
188	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
189
190	#define CONFIG_SYS_FLASH_EMPTY_INFO
191	#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
192	CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
193
194	#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
195	#define CONFIG_SYS_WRITE_SWAPPED_DATA
196
197	/*
198	* NAND Flash Definitions
199	*/
200	#define CONFIG_NAND_FSL_IFC
201
202	#define CONFIG_SYS_NAND_BASE 0x7e800000
203	#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
204
205	#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
206
207	#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
208	\| CSPR_PORT_SIZE_8 \
209	\| CSPR_MSEL_NAND \
210	\| CSPR_V)
211	#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
212	#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
213	\| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
214	\| CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \
215	\| CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
216	\| CSOR_NAND_PGS_4K /* Page Size = 4K */ \
217	\| CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
218	\| CSOR_NAND_PB(64)) /* 64 Pages Per Block */
219
220	#define CONFIG_SYS_NAND_ONFI_DETECTION
221
222	#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) \| \
223	FTIM0_NAND_TWP(0x18) \| \
224	FTIM0_NAND_TWCHT(0x7) \| \
225	FTIM0_NAND_TWH(0xa))
226	#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) \| \
227	FTIM1_NAND_TWBE(0x39) \| \
228	FTIM1_NAND_TRR(0xe) \| \
229	FTIM1_NAND_TRP(0x18))
230	#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) \| \
231	FTIM2_NAND_TREH(0xa) \| \
232	FTIM2_NAND_TWHRE(0x1e))
233	#define CONFIG_SYS_NAND_FTIM3 0x0
234
235	#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
236	#define CONFIG_SYS_MAX_NAND_DEVICE 1
237	#define CONFIG_MTD_NAND_VERIFY_WRITE
238	#define CONFIG_CMD_NAND
239
240	#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
241	#endif
242
243	#ifdef CONFIG_NAND_BOOT
244	#define CONFIG_SPL_PAD_TO 0x40000 /* block aligned */
245	#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
246	#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
247	#endif
248
249	#if defined(CONFIG_QSPI_BOOT) \|\| defined(CONFIG_SD_BOOT_QSPI)
250	#define CONFIG_QIXIS_I2C_ACCESS
251	#define CONFIG_SYS_I2C_EARLY_INIT
252	#define CONFIG_SYS_NO_FLASH
253	#endif
254
255	/*
256	* QIXIS Definitions
257	*/
258	#define CONFIG_FSL_QIXIS
259
260	#ifdef CONFIG_FSL_QIXIS
261	#define QIXIS_BASE 0x7fb00000
262	#define QIXIS_BASE_PHYS QIXIS_BASE
263	#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
264	#define QIXIS_LBMAP_SWITCH 6
265	#define QIXIS_LBMAP_MASK 0x0f
266	#define QIXIS_LBMAP_SHIFT 0
267	#define QIXIS_LBMAP_DFLTBANK 0x00
268	#define QIXIS_LBMAP_ALTBANK 0x04
269	#define QIXIS_LBMAP_NAND 0x09
270	#define QIXIS_LBMAP_SD 0x00
271	#define QIXIS_LBMAP_SD_QSPI 0xff
272	#define QIXIS_LBMAP_QSPI 0xff
273	#define QIXIS_RCW_SRC_NAND 0x110
274	#define QIXIS_RCW_SRC_SD 0x040
275	#define QIXIS_RCW_SRC_QSPI 0x045
276	#define QIXIS_RST_CTL_RESET 0x41
277	#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
278	#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
279	#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
280
281	#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
282	#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \| \
283	CSPR_PORT_SIZE_8 \| \
284	CSPR_MSEL_GPCM \| \
285	CSPR_V)
286	#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
287	#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) \| \
288	CSOR_NOR_NOR_MODE_AVD_NOR \| \
289	CSOR_NOR_TRHZ_80)
290
291	/*
292	* QIXIS Timing parameters for IFC GPCM
293	*/
294	#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) \| \
295	FTIM0_GPCM_TEADC(0x20) \| \
296	FTIM0_GPCM_TEAHC(0x10))
297	#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) \| \
298	FTIM1_GPCM_TRAD(0x1f))
299	#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) \| \
300	FTIM2_GPCM_TCH(0x8) \| \
301	FTIM2_GPCM_TWP(0xf0))
302	#define CONFIG_SYS_FPGA_FTIM3 0x0
303	#endif
304
305	#ifdef CONFIG_NAND_BOOT
306	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
307	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
308	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
309	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
310	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
311	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
312	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
313	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
314	#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
315	#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
316	#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
317	#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
318	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
319	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
320	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
321	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
322	#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
323	#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
324	#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
325	#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
326	#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
327	#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
328	#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
329	#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
330	#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
331	#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
332	#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
333	#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
334	#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
335	#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
336	#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
337	#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
338	#else
339	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
340	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
341	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
342	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
343	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
344	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
345	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
346	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
347	#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
348	#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
349	#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
350	#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
351	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
352	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
353	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
354	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
355	#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
356	#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
357	#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
358	#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
359	#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
360	#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
361	#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
362	#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
363	#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
364	#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
365	#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
366	#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
367	#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
368	#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
369	#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
370	#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
371	#endif
372
373	/*
374	* I2C bus multiplexer
375	*/
376	#define I2C_MUX_PCA_ADDR_PRI 0x77
377	#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
378	#define I2C_RETIMER_ADDR 0x18
379	#define I2C_MUX_CH_DEFAULT 0x8
380	#define I2C_MUX_CH_CH7301 0xC
381	#define I2C_MUX_CH5 0xD
382	#define I2C_MUX_CH6 0xE
383	#define I2C_MUX_CH7 0xF
384
385	#define I2C_MUX_CH_VOL_MONITOR 0xa
386
387	/* Voltage monitor on channel 2*/
388	#define I2C_VOL_MONITOR_ADDR 0x40
389	#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
390	#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
391	#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
392
393	#define CONFIG_VID_FLS_ENV "ls1046aqds_vdd_mv"
394	#ifndef CONFIG_SPL_BUILD
395	#define CONFIG_VID
396	#endif
397	#define CONFIG_VOL_MONITOR_IR36021_SET
398	#define CONFIG_VOL_MONITOR_INA220
399	/* The lowest and highest voltage allowed for LS1046AQDS */
400	#define VDD_MV_MIN 819
401	#define VDD_MV_MAX 1212
402
403	/*
404	* Miscellaneous configurable options
405	*/
406	#define CONFIG_MISC_INIT_R
407	#define CONFIG_SYS_LONGHELP /* undef to save memory */
408	#define CONFIG_AUTO_COMPLETE
409	#define CONFIG_SYS_PBSIZE \
410	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
411	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
412
413	#define CONFIG_SYS_MEMTEST_START 0x80000000
414	#define CONFIG_SYS_MEMTEST_END 0x9fffffff
415
416	#define CONFIG_SYS_HZ 1000
417
418	/*
419	* Stack sizes
420	* The stack sizes are set up in start.S using the settings below
421	*/
422	#define CONFIG_STACKSIZE (30 * 1024)
423
424	#define CONFIG_SYS_INIT_SP_OFFSET \
425	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
426
427	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
428
429	/*
430	* Environment
431	*/
432	#define CONFIG_ENV_OVERWRITE
433
434	#ifdef CONFIG_NAND_BOOT
435	#define CONFIG_ENV_IS_IN_NAND
436	#define CONFIG_ENV_SIZE 0x2000
437	#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
438	#elif defined(CONFIG_SD_BOOT)
439	#define CONFIG_ENV_OFFSET (1024 * 1024)
440	#define CONFIG_ENV_IS_IN_MMC
441	#define CONFIG_SYS_MMC_ENV_DEV 0
442	#define CONFIG_ENV_SIZE 0x2000
443	#elif defined(CONFIG_QSPI_BOOT)
444	#define CONFIG_ENV_IS_IN_SPI_FLASH
445	#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
446	#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
447	#define CONFIG_ENV_SECT_SIZE 0x10000
448	#else
449	#define CONFIG_ENV_IS_IN_FLASH
450	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000)
451	#define CONFIG_ENV_SECT_SIZE 0x20000
452	#define CONFIG_ENV_SIZE 0x20000
453	#endif
454
455	#define CONFIG_CMDLINE_TAG
456
457	#if defined(CONFIG_QSPI_BOOT) \|\| defined(CONFIG_SD_BOOT_QSPI)
458	#define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load " \
459	"e0000 f00000 && bootm $kernel_load"
460	#else
461	#define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \
462	"$kernel_size && bootm $kernel_load"
463	#endif
464
465	#if defined(CONFIG_QSPI_BOOT) \|\| defined(CONFIG_SD_BOOT_QSPI)
466	#define MTDPARTS_DEFAULT "mtdparts=1550000.quadspi:2m(uboot)," \
467	"14m(free)"
468	#else
469	#define MTDPARTS_DEFAULT "mtdparts=60000000.nor:1m(nor_bank0_rcw)," \
470	"1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \
471	"1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \
472	"1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \
473	"1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \
474	"40m(nor_bank4_fit);7e800000.flash:" \
475	"4m(nand_uboot),36m(nand_kernel)," \
476	"472m(nand_free);spi0.0:2m(uboot)," \
477	"14m(free)"
478	#endif
479
480	#include <asm/fsl_secure_boot.h>
481
482	#endif /* __LS1046AQDS_H__ */