]>
Commit | Line | Data |
---|---|---|
b765ffb7 | 1 | /* |
f47b048b | 2 | * (C) Copyright 2007-2013 |
b765ffb7 SR |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
b765ffb7 SR |
6 | */ |
7 | ||
f14ae418 | 8 | /* |
b765ffb7 | 9 | * lwmon5.h - configuration for lwmon5 board |
f14ae418 | 10 | */ |
b765ffb7 SR |
11 | #ifndef __CONFIG_H |
12 | #define __CONFIG_H | |
13 | ||
f14ae418 SL |
14 | /* |
15 | * Liebherr extra version info | |
16 | */ | |
17 | #define CONFIG_IDENT_STRING " - v2.0" | |
18 | ||
19 | /* | |
b765ffb7 | 20 | * High Level Configuration Options |
f14ae418 | 21 | */ |
b765ffb7 SR |
22 | #define CONFIG_LWMON5 1 /* Board is lwmon5 */ |
23 | #define CONFIG_440EPX 1 /* Specific PPC440EPx */ | |
e73846b7 | 24 | #define CONFIG_440 1 /* ... PPC440 family */ |
b765ffb7 | 25 | #define CONFIG_4xx 1 /* ... PPC4xx family */ |
2ae18241 | 26 | |
f47b048b SR |
27 | #ifdef CONFIG_LCD4_LWMON5 |
28 | #define CONFIG_SYS_TEXT_BASE 0x01000000 /* SPL U-Boot TEXT_BASE */ | |
29 | #define CONFIG_HOSTNAME lcd4_lwmon5 | |
30 | #else | |
2ae18241 | 31 | #define CONFIG_SYS_TEXT_BASE 0xFFF80000 |
f47b048b | 32 | #define CONFIG_HOSTNAME lwmon5 |
2ae18241 WD |
33 | #endif |
34 | ||
b765ffb7 SR |
35 | #define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */ |
36 | ||
a321148b SR |
37 | #define CONFIG_4xx_DCACHE /* enable cache in SDRAM */ |
38 | ||
f14ae418 SL |
39 | #define CONFIG_BOARD_EARLY_INIT_F /* Call board_early_init_f */ |
40 | #define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r */ | |
41 | #define CONFIG_BOARD_POSTCLK_INIT /* Call board_postclk_init */ | |
42 | #define CONFIG_MISC_INIT_R /* Call misc_init_r */ | |
43 | #define CONFIG_BOARD_RESET /* Call board_reset */ | |
b765ffb7 | 44 | |
f14ae418 | 45 | /* |
b765ffb7 SR |
46 | * Base addresses -- Note these are effective addresses where the |
47 | * actual resources get mapped (not physical addresses) | |
f14ae418 | 48 | */ |
14d0a02a | 49 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of U-Boot */ |
f47b048b | 50 | #define CONFIG_SYS_MONITOR_LEN 0x80000 |
f14ae418 | 51 | #define CONFIG_SYS_MALLOC_LEN (1 << 20) /* Reserved for malloc */ |
6d0f6bcf JCPV |
52 | |
53 | #define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000 | |
54 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ | |
55 | #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */ | |
f14ae418 SL |
56 | #define CONFIG_SYS_LIME_BASE_0 0xc0000000 |
57 | #define CONFIG_SYS_LIME_BASE_1 0xc1000000 | |
58 | #define CONFIG_SYS_LIME_BASE_2 0xc2000000 | |
59 | #define CONFIG_SYS_LIME_BASE_3 0xc3000000 | |
60 | #define CONFIG_SYS_FPGA_BASE_0 0xc4000000 | |
61 | #define CONFIG_SYS_FPGA_BASE_1 0xc4200000 | |
6d0f6bcf JCPV |
62 | #define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */ |
63 | #define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */ | |
64 | #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ | |
f14ae418 SL |
65 | #define CONFIG_SYS_PCI_MEMBASE1 (CONFIG_SYS_PCI_MEMBASE + 0x10000000) |
66 | #define CONFIG_SYS_PCI_MEMBASE2 (CONFIG_SYS_PCI_MEMBASE1 + 0x10000000) | |
67 | #define CONFIG_SYS_PCI_MEMBASE3 (CONFIG_SYS_PCI_MEMBASE2 + 0x10000000) | |
b765ffb7 | 68 | |
f47b048b | 69 | #ifndef CONFIG_LCD4_LWMON5 |
6d0f6bcf JCPV |
70 | #define CONFIG_SYS_USB2D0_BASE 0xe0000100 |
71 | #define CONFIG_SYS_USB_DEVICE 0xe0000000 | |
72 | #define CONFIG_SYS_USB_HOST 0xe0000400 | |
f47b048b | 73 | #endif |
b765ffb7 | 74 | |
8f24e063 | 75 | /* |
f14ae418 SL |
76 | * Initial RAM & stack pointer |
77 | * | |
8f24e063 SR |
78 | * On LWMON5 we use D-cache as init-ram and stack pointer. We also move |
79 | * the POST_WORD from OCM to a 440EPx register that preserves it's | |
eb0615bf YT |
80 | * content during reset (GPT0_COMP6). This way we reserve the OCM (16k) |
81 | * for logbuffer only. (GPT0_COMP1-COMP5 are reserved for logbuffer header.) | |
8f24e063 | 82 | */ |
f47b048b | 83 | #ifndef CONFIG_LCD4_LWMON5 |
6d0f6bcf JCPV |
84 | #define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */ |
85 | #define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */ | |
553f0982 | 86 | #define CONFIG_SYS_INIT_RAM_SIZE (4 << 10) |
553f0982 | 87 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ |
25ddd1fb | 88 | GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 89 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
f47b048b SR |
90 | #else |
91 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE | |
92 | #define CONFIG_SYS_INIT_RAM_SIZE (4 << 10) | |
93 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ | |
94 | GENERATED_GBL_DATA_SIZE) | |
95 | #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) | |
96 | #endif | |
f14ae418 | 97 | /* unused GPT0 COMP reg */ |
800eb096 | 98 | #define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6) |
6d0f6bcf | 99 | #define CONFIG_SYS_OCM_SIZE (16 << 10) |
f14ae418 SL |
100 | /* 440EPx errata CHIP 11: don't use last 4kbytes */ |
101 | #define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) | |
b765ffb7 | 102 | |
8f15d4ad | 103 | /* Additional registers for watchdog timer post test */ |
6d0f6bcf JCPV |
104 | #define CONFIG_SYS_WATCHDOG_TIME_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK2) |
105 | #define CONFIG_SYS_WATCHDOG_FLAGS_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK1) | |
106 | #define CONFIG_SYS_DSPIC_TEST_ADDR CONFIG_SYS_WATCHDOG_FLAGS_ADDR | |
107 | #define CONFIG_SYS_OCM_STATUS_ADDR CONFIG_SYS_WATCHDOG_FLAGS_ADDR | |
108 | #define CONFIG_SYS_WATCHDOG_MAGIC 0x12480000 | |
109 | #define CONFIG_SYS_WATCHDOG_MAGIC_MASK 0xFFFF0000 | |
110 | #define CONFIG_SYS_DSPIC_TEST_MASK 0x00000001 | |
111 | #define CONFIG_SYS_OCM_STATUS_OK 0x00009A00 | |
112 | #define CONFIG_SYS_OCM_STATUS_FAIL 0x0000A300 | |
113 | #define CONFIG_SYS_OCM_STATUS_MASK 0x0000FF00 | |
8f15d4ad | 114 | |
f14ae418 | 115 | /* |
b765ffb7 | 116 | * Serial Port |
f14ae418 | 117 | */ |
550650dd SR |
118 | #define CONFIG_CONS_INDEX 2 /* Use UART1 */ |
119 | #define CONFIG_SYS_NS16550 | |
120 | #define CONFIG_SYS_NS16550_SERIAL | |
121 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
122 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() | |
6d0f6bcf | 123 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external clock provided */ |
b765ffb7 | 124 | #define CONFIG_BAUDRATE 115200 |
b765ffb7 | 125 | |
6d0f6bcf | 126 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
b765ffb7 SR |
127 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} |
128 | ||
f14ae418 | 129 | /* |
b765ffb7 | 130 | * Environment |
f14ae418 SL |
131 | */ |
132 | #define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */ | |
b765ffb7 | 133 | |
f14ae418 | 134 | /* |
b765ffb7 | 135 | * FLASH related |
f14ae418 SL |
136 | */ |
137 | #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ | |
00b1883a | 138 | #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ |
b765ffb7 | 139 | |
6d0f6bcf JCPV |
140 | #define CONFIG_SYS_FLASH0 0xFC000000 |
141 | #define CONFIG_SYS_FLASH1 0xF8000000 | |
142 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 } | |
b765ffb7 | 143 | |
f14ae418 | 144 | #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 /* max number of memory banks */ |
6d0f6bcf | 145 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ |
b765ffb7 | 146 | |
6d0f6bcf JCPV |
147 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
148 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
b765ffb7 | 149 | |
f14ae418 SL |
150 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */ |
151 | #define CONFIG_SYS_FLASH_PROTECTION /* use hardware flash protection */ | |
b765ffb7 | 152 | |
6d0f6bcf | 153 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
f14ae418 | 154 | #define CONFIG_SYS_FLASH_QUIET_TEST /* don't warn upon unknown flash */ |
b765ffb7 | 155 | |
0e8d1586 | 156 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */ |
f14ae418 | 157 | #define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN) - CONFIG_ENV_SECT_SIZE) |
0e8d1586 | 158 | #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ |
b765ffb7 SR |
159 | |
160 | /* Address and size of Redundant Environment Sector */ | |
f14ae418 | 161 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE) |
0e8d1586 | 162 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) |
b765ffb7 | 163 | |
f14ae418 | 164 | /* |
b765ffb7 | 165 | * DDR SDRAM |
f14ae418 SL |
166 | */ |
167 | #define CONFIG_SYS_MBYTES_SDRAM 256 | |
6d0f6bcf | 168 | #define CONFIG_SYS_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */ |
f14ae418 | 169 | #define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */ |
f47b048b | 170 | #ifndef CONFIG_LCD4_LWMON5 |
f14ae418 | 171 | #define CONFIG_DDR_ECC /* enable ECC */ |
f47b048b | 172 | #endif |
531e3e8b | 173 | |
f47b048b | 174 | #ifndef CONFIG_LCD4_LWMON5 |
531e3e8b | 175 | /* POST support */ |
f14ae418 SL |
176 | #define CONFIG_POST (CONFIG_SYS_POST_CACHE | \ |
177 | CONFIG_SYS_POST_CPU | \ | |
178 | CONFIG_SYS_POST_ECC | \ | |
179 | CONFIG_SYS_POST_ETHER | \ | |
180 | CONFIG_SYS_POST_FPU | \ | |
181 | CONFIG_SYS_POST_I2C | \ | |
182 | CONFIG_SYS_POST_MEMORY | \ | |
183 | CONFIG_SYS_POST_OCM | \ | |
184 | CONFIG_SYS_POST_RTC | \ | |
185 | CONFIG_SYS_POST_SPR | \ | |
186 | CONFIG_SYS_POST_UART | \ | |
187 | CONFIG_SYS_POST_SYSMON | \ | |
188 | CONFIG_SYS_POST_WATCHDOG | \ | |
189 | CONFIG_SYS_POST_DSP | \ | |
190 | CONFIG_SYS_POST_BSPEC1 | \ | |
191 | CONFIG_SYS_POST_BSPEC2 | \ | |
192 | CONFIG_SYS_POST_BSPEC3 | \ | |
193 | CONFIG_SYS_POST_BSPEC4 | \ | |
6d0f6bcf | 194 | CONFIG_SYS_POST_BSPEC5) |
8f15d4ad | 195 | |
f14ae418 | 196 | /* Define here the base-addresses of the UARTs to test in POST */ |
5d7c73e6 SR |
197 | #define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \ |
198 | CONFIG_SYS_NS16550_COM2 } | |
f14ae418 | 199 | |
834a45d7 SR |
200 | #define CONFIG_POST_UART { \ |
201 | "UART test", \ | |
202 | "uart", \ | |
203 | "This test verifies the UART operation.", \ | |
204 | POST_RAM | POST_SLOWTEST | POST_ALWAYS | POST_MANUAL, \ | |
205 | &uart_post_test, \ | |
206 | NULL, \ | |
207 | NULL, \ | |
208 | CONFIG_SYS_POST_UART \ | |
209 | } | |
210 | ||
f14ae418 | 211 | #define CONFIG_POST_WATCHDOG { \ |
8f15d4ad YT |
212 | "Watchdog timer test", \ |
213 | "watchdog", \ | |
214 | "This test checks the watchdog timer.", \ | |
215 | POST_RAM | POST_POWERON | POST_SLOWTEST | POST_MANUAL | POST_REBOOT, \ | |
216 | &lwmon5_watchdog_post_test, \ | |
217 | NULL, \ | |
218 | NULL, \ | |
f14ae418 | 219 | CONFIG_SYS_POST_WATCHDOG \ |
8f15d4ad YT |
220 | } |
221 | ||
f14ae418 | 222 | #define CONFIG_POST_BSPEC1 { \ |
8f15d4ad YT |
223 | "dsPIC init test", \ |
224 | "dspic_init", \ | |
225 | "This test returns result of dsPIC READY test run earlier.", \ | |
226 | POST_RAM | POST_ALWAYS, \ | |
227 | &dspic_init_post_test, \ | |
228 | NULL, \ | |
229 | NULL, \ | |
f14ae418 | 230 | CONFIG_SYS_POST_BSPEC1 \ |
8f15d4ad YT |
231 | } |
232 | ||
f14ae418 | 233 | #define CONFIG_POST_BSPEC2 { \ |
8f15d4ad YT |
234 | "dsPIC test", \ |
235 | "dspic", \ | |
236 | "This test gets result of dsPIC POST and dsPIC version.", \ | |
237 | POST_RAM | POST_ALWAYS, \ | |
238 | &dspic_post_test, \ | |
239 | NULL, \ | |
240 | NULL, \ | |
f14ae418 | 241 | CONFIG_SYS_POST_BSPEC2 \ |
8f15d4ad YT |
242 | } |
243 | ||
f14ae418 | 244 | #define CONFIG_POST_BSPEC3 { \ |
8f15d4ad YT |
245 | "FPGA test", \ |
246 | "fpga", \ | |
247 | "This test checks FPGA registers and memory.", \ | |
f14ae418 | 248 | POST_RAM | POST_ALWAYS | POST_MANUAL, \ |
8f15d4ad YT |
249 | &fpga_post_test, \ |
250 | NULL, \ | |
251 | NULL, \ | |
f14ae418 | 252 | CONFIG_SYS_POST_BSPEC3 \ |
8f15d4ad YT |
253 | } |
254 | ||
f14ae418 | 255 | #define CONFIG_POST_BSPEC4 { \ |
8f15d4ad YT |
256 | "GDC test", \ |
257 | "gdc", \ | |
258 | "This test checks GDC registers and memory.", \ | |
f14ae418 | 259 | POST_RAM | POST_ALWAYS | POST_MANUAL,\ |
8f15d4ad YT |
260 | &gdc_post_test, \ |
261 | NULL, \ | |
262 | NULL, \ | |
f14ae418 | 263 | CONFIG_SYS_POST_BSPEC4 \ |
8f15d4ad YT |
264 | } |
265 | ||
f14ae418 | 266 | #define CONFIG_POST_BSPEC5 { \ |
8f15d4ad YT |
267 | "SYSMON1 test", \ |
268 | "sysmon1", \ | |
269 | "This test checks GPIO_62_EPX pin indicating power failure.", \ | |
270 | POST_RAM | POST_MANUAL | POST_NORMAL | POST_SLOWTEST, \ | |
271 | &sysmon1_post_test, \ | |
272 | NULL, \ | |
273 | NULL, \ | |
f14ae418 | 274 | CONFIG_SYS_POST_BSPEC5 \ |
8f15d4ad | 275 | } |
3e4c90c6 | 276 | |
6d0f6bcf | 277 | #define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */ |
3e4c90c6 | 278 | #define CONFIG_LOGBUFFER |
eb0615bf | 279 | /* Reserve GPT0_COMP1-COMP5 for logbuffer header */ |
6d0f6bcf JCPV |
280 | #define CONFIG_ALT_LH_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP1) |
281 | #define CONFIG_ALT_LB_ADDR (CONFIG_SYS_OCM_BASE) | |
282 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ | |
f47b048b | 283 | #endif |
b765ffb7 | 284 | |
f14ae418 | 285 | /* |
b765ffb7 | 286 | * I2C |
f14ae418 SL |
287 | */ |
288 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
b765ffb7 | 289 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
d0b0dcaa | 290 | #define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ |
6d0f6bcf JCPV |
291 | #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ |
292 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
b765ffb7 | 293 | |
f14ae418 SL |
294 | #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* RTC */ |
295 | #define CONFIG_SYS_I2C_EEPROM_CPU_ADDR 0x52 /* EEPROM (CPU Modul) */ | |
296 | #define CONFIG_SYS_I2C_EEPROM_MB_ADDR 0x53 /* EEPROM AT24C128 (MainBoard) */ | |
297 | #define CONFIG_SYS_I2C_DSPIC_ADDR 0x54 /* dsPIC */ | |
298 | #define CONFIG_SYS_I2C_DSPIC_2_ADDR 0x55 /* dsPIC */ | |
299 | #define CONFIG_SYS_I2C_DSPIC_KEYB_ADDR 0x56 /* dsPIC */ | |
300 | #define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* dsPIC */ | |
301 | ||
6d0f6bcf JCPV |
302 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ |
303 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel AT24C128 has */ | |
c25dd8fc SR |
304 | /* 64 byte page write mode using*/ |
305 | /* last 6 bits of the address */ | |
6d0f6bcf | 306 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
f14ae418 SL |
307 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE |
308 | ||
309 | #define CONFIG_RTC_PCF8563 /* enable Philips PCF8563 RTC */ | |
310 | #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */ | |
311 | #define CONFIG_SYS_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */ | |
312 | #define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* PIC I/O addr */ | |
313 | ||
60aaaa07 PT |
314 | #define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_RTC_ADDR, \ |
315 | CONFIG_SYS_I2C_EEPROM_CPU_ADDR,\ | |
316 | CONFIG_SYS_I2C_EEPROM_MB_ADDR, \ | |
317 | CONFIG_SYS_I2C_DSPIC_ADDR, \ | |
318 | CONFIG_SYS_I2C_DSPIC_2_ADDR, \ | |
319 | CONFIG_SYS_I2C_DSPIC_KEYB_ADDR,\ | |
320 | CONFIG_SYS_I2C_DSPIC_IO_ADDR } | |
b765ffb7 | 321 | |
f14ae418 SL |
322 | /* |
323 | * Pass open firmware flat tree | |
324 | */ | |
325 | #define CONFIG_OF_LIBFDT | |
326 | #define CONFIG_OF_BOARD_SETUP | |
327 | /* Update size in "reg" property of NOR FLASH device tree nodes */ | |
328 | #define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE | |
b765ffb7 | 329 | |
a321148b SR |
330 | #define CONFIG_FIT /* enable FIT image support */ |
331 | ||
3ad63878 | 332 | #define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */ |
3ad63878 SR |
333 | |
334 | #define CONFIG_PREBOOT "setenv bootdelay 15" | |
b765ffb7 SR |
335 | |
336 | #undef CONFIG_BOOTARGS | |
337 | ||
338 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
339 | "hostname=lwmon5\0" \ | |
340 | "netdev=eth0\0" \ | |
5d187430 | 341 | "unlock=yes\0" \ |
3e4c90c6 | 342 | "logversion=2\0" \ |
b765ffb7 SR |
343 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
344 | "nfsroot=${serverip}:${rootpath}\0" \ | |
345 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
346 | "addip=setenv bootargs ${bootargs} " \ | |
347 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
348 | ":${hostname}:${netdev}:off panic=1\0" \ | |
349 | "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\ | |
04625764 SR |
350 | "addmisc=setenv bootargs ${bootargs} rtc-pcf8563.probe=0,0x51\0"\ |
351 | "flash_nfs=run nfsargs addip addtty addmisc;" \ | |
b765ffb7 | 352 | "bootm ${kernel_addr}\0" \ |
04625764 | 353 | "flash_self=run ramargs addip addtty addmisc;" \ |
b765ffb7 | 354 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
04625764 SR |
355 | "net_nfs=tftp 200000 ${bootfile};" \ |
356 | "run nfsargs addip addtty addmisc;bootm\0" \ | |
b765ffb7 SR |
357 | "rootpath=/opt/eldk/ppc_4xxFP\0" \ |
358 | "bootfile=/tftpboot/lwmon5/uImage\0" \ | |
359 | "kernel_addr=FC000000\0" \ | |
360 | "ramdisk_addr=FC180000\0" \ | |
361 | "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \ | |
362 | "update=protect off FFF80000 FFFFFFFF;era FFF80000 FFFFFFFF;" \ | |
363 | "cp.b 200000 FFF80000 80000\0" \ | |
d8ab58b2 | 364 | "upd=run load update\0" \ |
334043f6 | 365 | "lwe_env=tftp 200000 /tftpboot.dev/lwmon5/env_uboot.bin;" \ |
f14ae418 | 366 | "autoscr 200000\0" \ |
b765ffb7 SR |
367 | "" |
368 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
369 | ||
b765ffb7 | 370 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
b765ffb7 SR |
371 | |
372 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 373 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
b765ffb7 | 374 | |
96e21f86 | 375 | #define CONFIG_PPC4xx_EMAC |
b765ffb7 SR |
376 | #define CONFIG_IBM_EMAC4_V4 1 |
377 | #define CONFIG_MII 1 /* MII PHY management */ | |
378 | #define CONFIG_PHY_ADDR 3 /* PHY address, See schematics */ | |
379 | ||
380 | #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ | |
3ad63878 | 381 | #define CONFIG_PHY_RESET_DELAY 300 |
b765ffb7 SR |
382 | |
383 | #define CONFIG_HAS_ETH0 | |
6d0f6bcf | 384 | #define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ |
b765ffb7 | 385 | |
b765ffb7 SR |
386 | #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ |
387 | #define CONFIG_PHY1_ADDR 1 | |
388 | ||
d610a607 AG |
389 | /* Video console */ |
390 | #define CONFIG_VIDEO | |
391 | #define CONFIG_VIDEO_MB862xx | |
5d16ca87 | 392 | #define CONFIG_VIDEO_MB862xx_ACCEL |
d610a607 AG |
393 | #define CONFIG_CFB_CONSOLE |
394 | #define CONFIG_VIDEO_LOGO | |
395 | #define CONFIG_CONSOLE_EXTRA_INFO | |
396 | #define VIDEO_FB_16BPP_PIXEL_SWAP | |
229b6dce | 397 | #define VIDEO_FB_16BPP_WORD_SWAP |
d610a607 AG |
398 | |
399 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
400 | #define CONFIG_VIDEO_SW_CURSOR | |
401 | #define CONFIG_SPLASH_SCREEN | |
402 | ||
f47b048b | 403 | #ifndef CONFIG_LCD4_LWMON5 |
a321148b SR |
404 | /* |
405 | * USB/EHCI | |
406 | */ | |
407 | #define CONFIG_USB_EHCI /* Enable EHCI USB support */ | |
408 | #define CONFIG_USB_EHCI_PPC4XX /* on PPC4xx platform */ | |
409 | #define CONFIG_SYS_PPC4XX_USB_ADDR 0xe0000300 | |
a321148b SR |
410 | #define CONFIG_EHCI_MMIO_BIG_ENDIAN |
411 | #define CONFIG_EHCI_DESC_BIG_ENDIAN | |
412 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */ | |
b765ffb7 SR |
413 | #define CONFIG_USB_STORAGE |
414 | ||
b765ffb7 SR |
415 | /* Partitions */ |
416 | #define CONFIG_MAC_PARTITION | |
417 | #define CONFIG_DOS_PARTITION | |
418 | #define CONFIG_ISO_PARTITION | |
f47b048b | 419 | #endif |
b765ffb7 | 420 | |
079a136c JL |
421 | /* |
422 | * BOOTP options | |
423 | */ | |
424 | #define CONFIG_BOOTP_BOOTFILESIZE | |
425 | #define CONFIG_BOOTP_BOOTPATH | |
426 | #define CONFIG_BOOTP_GATEWAY | |
427 | #define CONFIG_BOOTP_HOSTNAME | |
b765ffb7 | 428 | |
a22d4da9 JL |
429 | /* |
430 | * Command line configuration. | |
431 | */ | |
432 | #include <config_cmd_default.h> | |
433 | ||
434 | #define CONFIG_CMD_ASKENV | |
435 | #define CONFIG_CMD_DATE | |
436 | #define CONFIG_CMD_DHCP | |
437 | #define CONFIG_CMD_DIAG | |
438 | #define CONFIG_CMD_EEPROM | |
439 | #define CONFIG_CMD_ELF | |
440 | #define CONFIG_CMD_FAT | |
441 | #define CONFIG_CMD_I2C | |
442 | #define CONFIG_CMD_IRQ | |
443 | #define CONFIG_CMD_MII | |
444 | #define CONFIG_CMD_NET | |
445 | #define CONFIG_CMD_NFS | |
a22d4da9 JL |
446 | #define CONFIG_CMD_PING |
447 | #define CONFIG_CMD_REGINFO | |
448 | #define CONFIG_CMD_SDRAM | |
b765ffb7 | 449 | |
d610a607 AG |
450 | #ifdef CONFIG_VIDEO |
451 | #define CONFIG_CMD_BMP | |
452 | #endif | |
453 | ||
f47b048b | 454 | #ifndef CONFIG_LCD4_LWMON5 |
a22d4da9 JL |
455 | #ifdef CONFIG_440EPX |
456 | #define CONFIG_CMD_USB | |
457 | #endif | |
f47b048b | 458 | #endif |
b765ffb7 | 459 | |
f14ae418 | 460 | /* |
b765ffb7 | 461 | * Miscellaneous configurable options |
f14ae418 | 462 | */ |
a22d4da9 JL |
463 | #define CONFIG_SUPPORT_VFAT |
464 | ||
6d0f6bcf JCPV |
465 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
466 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
58d20425 | 467 | |
6d0f6bcf | 468 | #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ |
58d20425 | 469 | |
a22d4da9 | 470 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 471 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
b765ffb7 | 472 | #else |
6d0f6bcf | 473 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
b765ffb7 | 474 | #endif |
6d0f6bcf JCPV |
475 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
476 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
477 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
b765ffb7 | 478 | |
6d0f6bcf JCPV |
479 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
480 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
b765ffb7 | 481 | |
6d0f6bcf JCPV |
482 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
483 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
b765ffb7 | 484 | |
6d0f6bcf | 485 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
b765ffb7 SR |
486 | |
487 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
488 | #define CONFIG_LOOPW 1 /* enable loopw command */ | |
489 | #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ | |
b765ffb7 SR |
490 | #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ |
491 | ||
f47b048b SR |
492 | #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/ |
493 | ||
494 | #ifndef CONFIG_LCD4_LWMON5 | |
f14ae418 | 495 | #ifndef DEBUG |
b765ffb7 | 496 | #define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */ |
f14ae418 | 497 | #endif |
2e721094 | 498 | #define CONFIG_WD_PERIOD 40000 /* in usec */ |
d32a874b | 499 | #define CONFIG_WD_MAX_RATE 66600 /* in ticks */ |
f47b048b | 500 | #endif |
b765ffb7 SR |
501 | |
502 | /* | |
503 | * For booting Linux, the board info and command line data | |
f14ae418 SL |
504 | * have to be in the first 16 MB of memory, since this is |
505 | * the maximum mapped by the 40x Linux kernel during initialization. | |
b765ffb7 | 506 | */ |
f14ae418 SL |
507 | #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux */ |
508 | #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ | |
b765ffb7 | 509 | |
f14ae418 | 510 | /* |
b765ffb7 | 511 | * External Bus Controller (EBC) Setup |
f14ae418 | 512 | */ |
6d0f6bcf | 513 | #define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE |
b765ffb7 SR |
514 | |
515 | /* Memory Bank 0 (NOR-FLASH) initialization */ | |
f14ae418 | 516 | #define CONFIG_SYS_EBC_PB0AP 0x03000280 |
6d0f6bcf | 517 | #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0xfc000) |
b765ffb7 SR |
518 | |
519 | /* Memory Bank 1 (Lime) initialization */ | |
6d0f6bcf | 520 | #define CONFIG_SYS_EBC_PB1AP 0x01004380 |
f14ae418 | 521 | #define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_LIME_BASE_0 | 0xbc000) |
b765ffb7 SR |
522 | |
523 | /* Memory Bank 2 (FPGA) initialization */ | |
6d0f6bcf JCPV |
524 | #define CONFIG_SYS_EBC_PB2AP 0x01004400 |
525 | #define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA_BASE_0 | 0x1c000) | |
b765ffb7 SR |
526 | |
527 | /* Memory Bank 3 (FPGA2) initialization */ | |
6d0f6bcf JCPV |
528 | #define CONFIG_SYS_EBC_PB3AP 0x01004400 |
529 | #define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_FPGA_BASE_1 | 0x1c000) | |
b765ffb7 | 530 | |
6d0f6bcf | 531 | #define CONFIG_SYS_EBC_CFG 0xb8400000 |
b765ffb7 | 532 | |
f14ae418 | 533 | /* |
04e6c38b | 534 | * Graphics (Fujitsu Lime) |
f14ae418 SL |
535 | */ |
536 | /* SDRAM Clock frequency adjustment register */ | |
537 | #define CONFIG_SYS_LIME_SDRAM_CLOCK 0xC1FC0038 | |
538 | #if 1 /* 133MHz is not tested enough, use 100MHz for now */ | |
b66091de | 539 | /* Lime Clock frequency is to set 100MHz */ |
6d0f6bcf | 540 | #define CONFIG_SYS_LIME_CLOCK_100MHZ 0x00000 |
f14ae418 | 541 | #else |
b66091de | 542 | /* Lime Clock frequency for 133MHz */ |
6d0f6bcf | 543 | #define CONFIG_SYS_LIME_CLOCK_133MHZ 0x10000 |
b66091de | 544 | #endif |
04e6c38b | 545 | |
f14ae418 SL |
546 | /* SDRAM Parameter register */ |
547 | #define CONFIG_SYS_LIME_MMR 0xC1FCFFFC | |
548 | /* | |
549 | * SDRAM parameter value; was 0x414FB7F2, caused several vertical bars | |
550 | * and pixel flare on display when 133MHz was configured. According to | |
551 | * SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed | |
552 | * Grade | |
553 | */ | |
6d0f6bcf | 554 | #ifdef CONFIG_SYS_LIME_CLOCK_133MHZ |
c28d3bbe WG |
555 | #define CONFIG_SYS_MB862xx_MMR 0x414FB7F3 |
556 | #define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_133MHZ | |
b66091de | 557 | #else |
c28d3bbe WG |
558 | #define CONFIG_SYS_MB862xx_MMR 0x414FB7F2 |
559 | #define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_100MHZ | |
b66091de | 560 | #endif |
04e6c38b | 561 | |
f14ae418 | 562 | /* |
b765ffb7 | 563 | * GPIO Setup |
f14ae418 | 564 | */ |
6d0f6bcf JCPV |
565 | #define CONFIG_SYS_GPIO_PHY1_RST 12 |
566 | #define CONFIG_SYS_GPIO_FLASH_WP 14 | |
567 | #define CONFIG_SYS_GPIO_PHY0_RST 22 | |
568 | #define CONFIG_SYS_GPIO_DSPIC_READY 51 | |
f14ae418 SL |
569 | #define CONFIG_SYS_GPIO_CAN_ENABLE 53 |
570 | #define CONFIG_SYS_GPIO_LSB_ENABLE 54 | |
6d0f6bcf JCPV |
571 | #define CONFIG_SYS_GPIO_EEPROM_EXT_WP 55 |
572 | #define CONFIG_SYS_GPIO_HIGHSIDE 56 | |
573 | #define CONFIG_SYS_GPIO_EEPROM_INT_WP 57 | |
574 | #define CONFIG_SYS_GPIO_BOARD_RESET 58 | |
575 | #define CONFIG_SYS_GPIO_LIME_S 59 | |
576 | #define CONFIG_SYS_GPIO_LIME_RST 60 | |
577 | #define CONFIG_SYS_GPIO_SYSMON_STATUS 62 | |
578 | #define CONFIG_SYS_GPIO_WATCHDOG 63 | |
b765ffb7 | 579 | |
f14ae418 | 580 | /* |
b765ffb7 SR |
581 | * PPC440 GPIO Configuration |
582 | */ | |
6d0f6bcf | 583 | #define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ |
b765ffb7 SR |
584 | { \ |
585 | /* GPIO Core 0 */ \ | |
586 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \ | |
587 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \ | |
588 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \ | |
589 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \ | |
590 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \ | |
591 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \ | |
592 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \ | |
593 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \ | |
594 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \ | |
595 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \ | |
596 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \ | |
597 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \ | |
598 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \ | |
599 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \ | |
600 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \ | |
20d500d5 | 601 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO15 */ \ |
1636d1c8 | 602 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4) */ \ |
b765ffb7 SR |
603 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5) */ \ |
604 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6) */ \ | |
605 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMCTxD(7) */ \ | |
606 | {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \ | |
607 | {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \ | |
608 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \ | |
609 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0 */ \ | |
610 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 GMCTxD(2) */ \ | |
611 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 GMCTxD(3) */ \ | |
612 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \ | |
613 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \ | |
614 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 USB2D_TXVALID */ \ | |
615 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \ | |
616 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \ | |
617 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \ | |
618 | }, \ | |
619 | { \ | |
620 | /* GPIO Core 1 */ \ | |
621 | {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \ | |
622 | {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \ | |
623 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \ | |
624 | {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \ | |
625 | {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0) UART3_SIN*/ \ | |
626 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \ | |
627 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \ | |
628 | {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \ | |
629 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \ | |
630 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \ | |
631 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \ | |
632 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \ | |
633 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \ | |
634 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \ | |
635 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \ | |
636 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \ | |
637 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \ | |
638 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO49 Unselect via TraceSelect Bit */ \ | |
04e6c38b | 639 | {GPIO1_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \ |
b765ffb7 SR |
640 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \ |
641 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \ | |
20d500d5 | 642 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \ |
b765ffb7 SR |
643 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \ |
644 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55 Unselect via TraceSelect Bit */ \ | |
645 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \ | |
646 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO57 Unselect via TraceSelect Bit */ \ | |
3e954beb | 647 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \ |
b765ffb7 SR |
648 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \ |
649 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \ | |
650 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \ | |
651 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \ | |
652 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \ | |
653 | } \ | |
654 | } | |
655 | ||
a22d4da9 | 656 | #if defined(CONFIG_CMD_KGDB) |
b765ffb7 SR |
657 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
658 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
659 | #endif | |
f47b048b SR |
660 | |
661 | /* | |
662 | * SPL related defines | |
663 | */ | |
664 | #ifdef CONFIG_LCD4_LWMON5 | |
665 | #define CONFIG_SPL | |
666 | #define CONFIG_SPL_FRAMEWORK | |
667 | #define CONFIG_SPL_BOARD_INIT | |
668 | #define CONFIG_SPL_NOR_SUPPORT | |
669 | #define CONFIG_SPL_TEXT_BASE 0xffff0000 /* last 64 KiB for SPL */ | |
670 | #define CONFIG_SYS_SPL_MAX_LEN (64 << 10) | |
671 | #define CONFIG_UBOOT_PAD_TO 458752 /* decimal for 'dd' */ | |
672 | #define CONFIG_SPL_START_S_PATH "arch/powerpc/cpu/ppc4xx" | |
673 | #define CONFIG_SPL_LDSCRIPT "arch/powerpc/cpu/ppc4xx/u-boot-spl.lds" | |
674 | #define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */ | |
675 | #define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */ | |
676 | #define CONFIG_SPL_SERIAL_SUPPORT | |
677 | ||
678 | /* Place BSS for SPL near end of SDRAM */ | |
679 | #define CONFIG_SPL_BSS_START_ADDR ((256 - 1) << 20) | |
680 | #define CONFIG_SPL_BSS_MAX_SIZE (64 << 10) | |
681 | ||
682 | #define CONFIG_SPL_OS_BOOT | |
683 | /* Place patched DT blob (fdt) at this address */ | |
684 | #define CONFIG_SYS_SPL_ARGS_ADDR 0x01800000 | |
685 | ||
686 | #define CONFIG_SPL_TARGET "u-boot-img-spl-at-end.bin" | |
687 | ||
688 | /* Settings for real U-Boot to be loaded from NOR flash */ | |
689 | #define CONFIG_SYS_UBOOT_BASE (-CONFIG_SYS_MONITOR_LEN) | |
690 | #define CONFIG_SYS_UBOOT_START 0x01002100 | |
691 | ||
692 | #define CONFIG_SYS_OS_BASE 0xf8000000 | |
693 | #define CONFIG_SYS_FDT_BASE 0xf87c0000 | |
694 | #endif | |
695 | ||
b765ffb7 | 696 | #endif /* __CONFIG_H */ |