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b765ffb7 SR |
1 | /* |
2 | * (C) Copyright 2007 | |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License as | |
7 | * published by the Free Software Foundation; either version 2 of | |
8 | * the License, or (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
18 | * MA 02111-1307 USA | |
19 | */ | |
20 | ||
21 | /************************************************************************ | |
22 | * lwmon5.h - configuration for lwmon5 board | |
23 | ***********************************************************************/ | |
24 | #ifndef __CONFIG_H | |
25 | #define __CONFIG_H | |
26 | ||
27 | /*----------------------------------------------------------------------- | |
28 | * High Level Configuration Options | |
29 | *----------------------------------------------------------------------*/ | |
30 | #define CONFIG_LWMON5 1 /* Board is lwmon5 */ | |
31 | #define CONFIG_440EPX 1 /* Specific PPC440EPx */ | |
e73846b7 | 32 | #define CONFIG_440 1 /* ... PPC440 family */ |
b765ffb7 SR |
33 | #define CONFIG_4xx 1 /* ... PPC4xx family */ |
34 | #define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */ | |
35 | ||
36 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ | |
3ad63878 | 37 | #define CONFIG_BOARD_POSTCLK_INIT 1 /* Call board_postclk_init */ |
b765ffb7 | 38 | #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ |
b765ffb7 SR |
39 | |
40 | /*----------------------------------------------------------------------- | |
41 | * Base addresses -- Note these are effective addresses where the | |
42 | * actual resources get mapped (not physical addresses) | |
43 | *----------------------------------------------------------------------*/ | |
44 | #define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ | |
45 | #define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc() */ | |
46 | ||
47 | #define CFG_BOOT_BASE_ADDR 0xf0000000 | |
48 | #define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ | |
9f24a808 | 49 | #define CFG_FLASH_BASE 0xf8000000 /* start of FLASH */ |
b765ffb7 SR |
50 | #define CFG_MONITOR_BASE TEXT_BASE |
51 | #define CFG_LIME_BASE_0 0xc0000000 | |
52 | #define CFG_LIME_BASE_1 0xc1000000 | |
53 | #define CFG_LIME_BASE_2 0xc2000000 | |
54 | #define CFG_LIME_BASE_3 0xc3000000 | |
55 | #define CFG_FPGA_BASE_0 0xc4000000 | |
56 | #define CFG_FPGA_BASE_1 0xc4200000 | |
57 | #define CFG_OCM_BASE 0xe0010000 /* ocm */ | |
58 | #define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */ | |
59 | #define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ | |
60 | #define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 | |
61 | #define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000 | |
62 | #define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000 | |
63 | ||
64 | /* Don't change either of these */ | |
65 | #define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */ | |
66 | ||
67 | #define CFG_USB2D0_BASE 0xe0000100 | |
68 | #define CFG_USB_DEVICE 0xe0000000 | |
69 | #define CFG_USB_HOST 0xe0000400 | |
70 | ||
71 | /*----------------------------------------------------------------------- | |
72 | * Initial RAM & stack pointer | |
73 | *----------------------------------------------------------------------*/ | |
8f24e063 SR |
74 | /* |
75 | * On LWMON5 we use D-cache as init-ram and stack pointer. We also move | |
76 | * the POST_WORD from OCM to a 440EPx register that preserves it's | |
77 | * content during reset (GPT0_COM6). This way we reserve the OCM (16k) | |
78 | * for logbuffer only. | |
79 | */ | |
80 | #define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */ | |
81 | #define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */ | |
b765ffb7 | 82 | #define CFG_INIT_RAM_END (4 << 10) |
8f24e063 | 83 | #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data*/ |
b765ffb7 | 84 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
8f24e063 SR |
85 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
86 | #define CFG_POST_ALT_WORD_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP6) | |
87 | /* unused GPT0 COMP reg */ | |
b765ffb7 | 88 | |
65b20dce YT |
89 | /* Additional registers for watchdog timer post test */ |
90 | ||
91 | #define CFG_DSPIC_TEST_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP5) | |
92 | #define CFG_WATCHDOG_TIME_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP4) | |
93 | #define CFG_WATCHDOG_FLAGS_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP5) | |
94 | #define CFG_WATCHDOG_MAGIC 0x12480000 | |
95 | #define CFG_WATCHDOG_MAGIC_MASK 0xFFFF0000 | |
96 | #define CFG_DSPIC_TEST_MASK 0x00000001 | |
97 | ||
b765ffb7 SR |
98 | /*----------------------------------------------------------------------- |
99 | * Serial Port | |
100 | *----------------------------------------------------------------------*/ | |
101 | #undef CFG_EXT_SERIAL_CLOCK /* no external clock provided */ | |
102 | #define CONFIG_BAUDRATE 115200 | |
103 | #define CONFIG_SERIAL_MULTI 1 | |
104 | /* define this if you want console on UART1 */ | |
105 | #define CONFIG_UART1_CONSOLE 1 /* use UART1 as console */ | |
106 | ||
107 | #define CFG_BAUDRATE_TABLE \ | |
108 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
109 | ||
110 | /*----------------------------------------------------------------------- | |
111 | * Environment | |
112 | *----------------------------------------------------------------------*/ | |
113 | #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ | |
114 | ||
115 | /*----------------------------------------------------------------------- | |
116 | * FLASH related | |
117 | *----------------------------------------------------------------------*/ | |
118 | #define CFG_FLASH_CFI /* The flash is CFI compatible */ | |
119 | #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ | |
120 | ||
9f24a808 SR |
121 | #define CFG_FLASH0 0xFC000000 |
122 | #define CFG_FLASH1 0xF8000000 | |
123 | #define CFG_FLASH_BANKS_LIST { CFG_FLASH1, CFG_FLASH0 } | |
b765ffb7 | 124 | |
9f24a808 | 125 | #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
b765ffb7 SR |
126 | #define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ |
127 | ||
128 | #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ | |
129 | #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
130 | ||
131 | #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ | |
132 | #define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */ | |
133 | ||
134 | #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ | |
135 | #define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ | |
136 | ||
1636d1c8 | 137 | #define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */ |
b765ffb7 SR |
138 | #define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE) |
139 | #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ | |
140 | ||
141 | /* Address and size of Redundant Environment Sector */ | |
142 | #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) | |
143 | #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) | |
144 | ||
145 | /*----------------------------------------------------------------------- | |
146 | * DDR SDRAM | |
147 | *----------------------------------------------------------------------*/ | |
148 | #define CFG_MBYTES_SDRAM (256) /* 256MB */ | |
149 | #define CFG_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */ | |
150 | #define CONFIG_DDR_DATA_EYE 1 /* use DDR2 optimization */ | |
151 | #if 0 /* test-only: disable ECC for now */ | |
152 | #define CONFIG_DDR_ECC 1 /* enable ECC */ | |
3e4c90c6 SR |
153 | #define CFG_POST_ECC_ON CFG_POST_ECC |
154 | #else | |
155 | #define CFG_POST_ECC_ON 0 | |
156 | #endif | |
531e3e8b PK |
157 | |
158 | /* POST support */ | |
75e1a84d | 159 | #define CONFIG_POST (CFG_POST_CACHE | \ |
3e4c90c6 | 160 | CFG_POST_CPU | \ |
75e1a84d | 161 | CFG_POST_ECC_ON | \ |
3e4c90c6 | 162 | CFG_POST_ETHER | \ |
75e1a84d SR |
163 | CFG_POST_FPU | \ |
164 | CFG_POST_I2C | \ | |
165 | CFG_POST_MEMORY | \ | |
166 | CFG_POST_RTC | \ | |
167 | CFG_POST_SPR | \ | |
65b20dce YT |
168 | CFG_POST_UART | \ |
169 | CFG_POST_SYSMON | \ | |
170 | CFG_POST_WATCHDOG | \ | |
171 | CFG_POST_DSP | \ | |
172 | CFG_POST_BSPEC1 | \ | |
173 | CFG_POST_BSPEC2 | \ | |
174 | CFG_POST_BSPEC3 | \ | |
175 | CFG_POST_BSPEC4 | \ | |
176 | CFG_POST_BSPEC5) | |
177 | ||
178 | #define CONFIG_POST_WATCHDOG {\ | |
179 | "Watchdog timer test", \ | |
180 | "watchdog", \ | |
181 | "This test checks the watchdog timer.", \ | |
182 | POST_RAM | POST_POWERON | POST_SLOWTEST | POST_MANUAL | POST_REBOOT, \ | |
183 | &lwmon5_watchdog_post_test, \ | |
184 | NULL, \ | |
185 | NULL, \ | |
186 | CFG_POST_WATCHDOG \ | |
187 | } | |
188 | ||
189 | #define CONFIG_POST_BSPEC1 {\ | |
190 | "dsPIC init test", \ | |
191 | "dspic_init", \ | |
192 | "This test returns result of dsPIC READY test run earlier.", \ | |
193 | POST_RAM | POST_ALWAYS, \ | |
194 | &dspic_init_post_test, \ | |
195 | NULL, \ | |
196 | NULL, \ | |
197 | CFG_POST_BSPEC1 \ | |
198 | } | |
199 | ||
200 | #define CONFIG_POST_BSPEC2 {\ | |
201 | "dsPIC test", \ | |
202 | "dspic", \ | |
203 | "This test gets result of dsPIC POST and dsPIC version.", \ | |
204 | POST_RAM | POST_ALWAYS, \ | |
205 | &dspic_post_test, \ | |
206 | NULL, \ | |
207 | NULL, \ | |
208 | CFG_POST_BSPEC2 \ | |
209 | } | |
210 | ||
211 | #define CONFIG_POST_BSPEC3 {\ | |
212 | "FPGA test", \ | |
213 | "fpga", \ | |
214 | "This test checks FPGA registers and memory.", \ | |
215 | POST_RAM | POST_ALWAYS, \ | |
216 | &fpga_post_test, \ | |
217 | NULL, \ | |
218 | NULL, \ | |
219 | CFG_POST_BSPEC3 \ | |
220 | } | |
221 | ||
222 | #define CONFIG_POST_BSPEC4 {\ | |
223 | "GDC test", \ | |
224 | "gdc", \ | |
225 | "This test checks GDC registers and memory.", \ | |
226 | POST_RAM | POST_ALWAYS, \ | |
227 | &gdc_post_test, \ | |
228 | NULL, \ | |
229 | NULL, \ | |
230 | CFG_POST_BSPEC4 \ | |
231 | } | |
232 | ||
233 | #define CONFIG_POST_BSPEC5 {\ | |
234 | "SYSMON1 test", \ | |
235 | "sysmon1", \ | |
236 | "This test checks GPIO_62_EPX pin indicating power failure.", \ | |
237 | POST_RAM | POST_MANUAL | POST_NORMAL | POST_SLOWTEST, \ | |
238 | &sysmon1_post_test, \ | |
239 | NULL, \ | |
240 | NULL, \ | |
241 | CFG_POST_BSPEC5 \ | |
242 | } | |
3e4c90c6 | 243 | |
42d55ea0 | 244 | #define CFG_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */ |
3e4c90c6 SR |
245 | #define CONFIG_LOGBUFFER |
246 | #define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ | |
b765ffb7 SR |
247 | |
248 | /*----------------------------------------------------------------------- | |
249 | * I2C | |
250 | *----------------------------------------------------------------------*/ | |
251 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
252 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
c25dd8fc | 253 | #define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ |
b765ffb7 SR |
254 | #define CFG_I2C_SLAVE 0x7F |
255 | ||
c25dd8fc SR |
256 | #define CFG_I2C_EEPROM_ADDR 0x53 /* EEPROM AT24C128 */ |
257 | #define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ | |
258 | #define CFG_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel AT24C128 has */ | |
259 | /* 64 byte page write mode using*/ | |
260 | /* last 6 bits of the address */ | |
261 | #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ | |
b765ffb7 | 262 | #define CFG_EEPROM_PAGE_WRITE_ENABLE |
b765ffb7 SR |
263 | |
264 | #define CONFIG_RTC_PCF8563 1 /* enable Philips PCF8563 RTC */ | |
265 | #define CFG_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */ | |
3ad63878 | 266 | #define CFG_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */ |
65b20dce | 267 | #define CFG_I2C_DSPIC_IO_ADDR 0x57 /* PIC I/O addr */ |
b765ffb7 | 268 | |
3ad63878 SR |
269 | #define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */ |
270 | #if 0 | |
271 | #define CONFIG_AUTOBOOT_KEYED /* Enable "password" protection */ | |
272 | #define CONFIG_AUTOBOOT_PROMPT "\nEnter password - autoboot in %d sec...\n" | |
273 | #define CONFIG_AUTOBOOT_DELAY_STR " " /* "password" */ | |
274 | #endif | |
275 | ||
276 | #define CONFIG_PREBOOT "setenv bootdelay 15" | |
b765ffb7 SR |
277 | |
278 | #undef CONFIG_BOOTARGS | |
279 | ||
280 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
281 | "hostname=lwmon5\0" \ | |
282 | "netdev=eth0\0" \ | |
5d187430 | 283 | "unlock=yes\0" \ |
3e4c90c6 | 284 | "logversion=2\0" \ |
b765ffb7 SR |
285 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
286 | "nfsroot=${serverip}:${rootpath}\0" \ | |
287 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
288 | "addip=setenv bootargs ${bootargs} " \ | |
289 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
290 | ":${hostname}:${netdev}:off panic=1\0" \ | |
291 | "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\ | |
04625764 SR |
292 | "addmisc=setenv bootargs ${bootargs} rtc-pcf8563.probe=0,0x51\0"\ |
293 | "flash_nfs=run nfsargs addip addtty addmisc;" \ | |
b765ffb7 | 294 | "bootm ${kernel_addr}\0" \ |
04625764 | 295 | "flash_self=run ramargs addip addtty addmisc;" \ |
b765ffb7 | 296 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
04625764 SR |
297 | "net_nfs=tftp 200000 ${bootfile};" \ |
298 | "run nfsargs addip addtty addmisc;bootm\0" \ | |
b765ffb7 SR |
299 | "rootpath=/opt/eldk/ppc_4xxFP\0" \ |
300 | "bootfile=/tftpboot/lwmon5/uImage\0" \ | |
301 | "kernel_addr=FC000000\0" \ | |
302 | "ramdisk_addr=FC180000\0" \ | |
303 | "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \ | |
304 | "update=protect off FFF80000 FFFFFFFF;era FFF80000 FFFFFFFF;" \ | |
305 | "cp.b 200000 FFF80000 80000\0" \ | |
d8ab58b2 | 306 | "upd=run load update\0" \ |
334043f6 SR |
307 | "lwe_env=tftp 200000 /tftpboot.dev/lwmon5/env_uboot.bin;" \ |
308 | "autoscr 200000\0" \ | |
b765ffb7 SR |
309 | "" |
310 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
311 | ||
312 | #if 0 | |
313 | #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ | |
314 | #else | |
315 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
316 | #endif | |
317 | ||
318 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
319 | #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
320 | ||
321 | #define CONFIG_IBM_EMAC4_V4 1 | |
322 | #define CONFIG_MII 1 /* MII PHY management */ | |
323 | #define CONFIG_PHY_ADDR 3 /* PHY address, See schematics */ | |
324 | ||
325 | #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ | |
3ad63878 | 326 | #define CONFIG_PHY_RESET_DELAY 300 |
b765ffb7 SR |
327 | |
328 | #define CONFIG_HAS_ETH0 | |
329 | #define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ | |
330 | ||
331 | #define CONFIG_NET_MULTI 1 | |
332 | #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ | |
333 | #define CONFIG_PHY1_ADDR 1 | |
334 | ||
d610a607 AG |
335 | /* Video console */ |
336 | #define CONFIG_VIDEO | |
337 | #define CONFIG_VIDEO_MB862xx | |
338 | #define CONFIG_CFB_CONSOLE | |
339 | #define CONFIG_VIDEO_LOGO | |
340 | #define CONFIG_CONSOLE_EXTRA_INFO | |
341 | #define VIDEO_FB_16BPP_PIXEL_SWAP | |
342 | ||
343 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
344 | #define CONFIG_VIDEO_SW_CURSOR | |
345 | #define CONFIG_SPLASH_SCREEN | |
346 | ||
b765ffb7 SR |
347 | /* USB */ |
348 | #ifdef CONFIG_440EPX | |
349 | #define CONFIG_USB_OHCI | |
350 | #define CONFIG_USB_STORAGE | |
351 | ||
352 | /* Comment this out to enable USB 1.1 device */ | |
353 | #define USB_2_0_DEVICE | |
354 | ||
b765ffb7 SR |
355 | #endif /* CONFIG_440EPX */ |
356 | ||
357 | /* Partitions */ | |
358 | #define CONFIG_MAC_PARTITION | |
359 | #define CONFIG_DOS_PARTITION | |
360 | #define CONFIG_ISO_PARTITION | |
361 | ||
079a136c JL |
362 | /* |
363 | * BOOTP options | |
364 | */ | |
365 | #define CONFIG_BOOTP_BOOTFILESIZE | |
366 | #define CONFIG_BOOTP_BOOTPATH | |
367 | #define CONFIG_BOOTP_GATEWAY | |
368 | #define CONFIG_BOOTP_HOSTNAME | |
b765ffb7 | 369 | |
a22d4da9 JL |
370 | /* |
371 | * Command line configuration. | |
372 | */ | |
373 | #include <config_cmd_default.h> | |
374 | ||
375 | #define CONFIG_CMD_ASKENV | |
376 | #define CONFIG_CMD_DATE | |
377 | #define CONFIG_CMD_DHCP | |
378 | #define CONFIG_CMD_DIAG | |
379 | #define CONFIG_CMD_EEPROM | |
380 | #define CONFIG_CMD_ELF | |
381 | #define CONFIG_CMD_FAT | |
382 | #define CONFIG_CMD_I2C | |
383 | #define CONFIG_CMD_IRQ | |
3b3bff4c | 384 | #define CONFIG_CMD_LOG |
a22d4da9 JL |
385 | #define CONFIG_CMD_MII |
386 | #define CONFIG_CMD_NET | |
387 | #define CONFIG_CMD_NFS | |
388 | #define CONFIG_CMD_PCI | |
389 | #define CONFIG_CMD_PING | |
390 | #define CONFIG_CMD_REGINFO | |
391 | #define CONFIG_CMD_SDRAM | |
b765ffb7 | 392 | |
d610a607 AG |
393 | #ifdef CONFIG_VIDEO |
394 | #define CONFIG_CMD_BMP | |
395 | #endif | |
396 | ||
a22d4da9 JL |
397 | #ifdef CONFIG_440EPX |
398 | #define CONFIG_CMD_USB | |
399 | #endif | |
b765ffb7 SR |
400 | |
401 | /*----------------------------------------------------------------------- | |
402 | * Miscellaneous configurable options | |
403 | *----------------------------------------------------------------------*/ | |
a22d4da9 JL |
404 | #define CONFIG_SUPPORT_VFAT |
405 | ||
b765ffb7 SR |
406 | #define CFG_LONGHELP /* undef to save memory */ |
407 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
58d20425 WD |
408 | |
409 | #define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ | |
410 | #ifdef CFG_HUSH_PARSER | |
411 | #define CFG_PROMPT_HUSH_PS2 "> " | |
412 | #endif | |
413 | ||
a22d4da9 | 414 | #if defined(CONFIG_CMD_KGDB) |
b765ffb7 SR |
415 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
416 | #else | |
417 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
418 | #endif | |
419 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
420 | #define CFG_MAXARGS 16 /* max number of command args */ | |
421 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
422 | ||
423 | #define CFG_MEMTEST_START 0x0400000 /* memtest works on */ | |
424 | #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
425 | ||
426 | #define CFG_LOAD_ADDR 0x100000 /* default load address */ | |
427 | #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
428 | ||
429 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
430 | ||
431 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
432 | #define CONFIG_LOOPW 1 /* enable loopw command */ | |
433 | #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ | |
434 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ | |
435 | #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ | |
436 | ||
437 | /*----------------------------------------------------------------------- | |
438 | * PCI stuff | |
439 | *----------------------------------------------------------------------*/ | |
440 | /* General PCI */ | |
441 | #define CONFIG_PCI /* include pci support */ | |
442 | #undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ | |
443 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
444 | #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ | |
445 | ||
446 | /* Board-specific PCI */ | |
b765ffb7 SR |
447 | #define CFG_PCI_TARGET_INIT |
448 | #define CFG_PCI_MASTER_INIT | |
449 | ||
450 | #define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ | |
451 | #define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ | |
452 | ||
453 | #define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */ | |
2e721094 | 454 | #define CONFIG_WD_PERIOD 40000 /* in usec */ |
b765ffb7 SR |
455 | |
456 | /* | |
457 | * For booting Linux, the board info and command line data | |
458 | * have to be in the first 8 MB of memory, since this is | |
459 | * the maximum mapped by the Linux kernel during initialization. | |
460 | */ | |
461 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
462 | ||
463 | /*----------------------------------------------------------------------- | |
464 | * External Bus Controller (EBC) Setup | |
465 | *----------------------------------------------------------------------*/ | |
466 | #define CFG_FLASH CFG_FLASH_BASE | |
467 | ||
468 | /* Memory Bank 0 (NOR-FLASH) initialization */ | |
469 | #define CFG_EBC_PB0AP 0x03050200 | |
9f24a808 | 470 | #define CFG_EBC_PB0CR (CFG_FLASH | 0xfc000) |
b765ffb7 SR |
471 | |
472 | /* Memory Bank 1 (Lime) initialization */ | |
473 | #define CFG_EBC_PB1AP 0x01004380 | |
474 | #define CFG_EBC_PB1CR (CFG_LIME_BASE_0 | 0xdc000) | |
475 | ||
476 | /* Memory Bank 2 (FPGA) initialization */ | |
477 | #define CFG_EBC_PB2AP 0x01004400 | |
478 | #define CFG_EBC_PB2CR (CFG_FPGA_BASE_0 | 0x1c000) | |
479 | ||
480 | /* Memory Bank 3 (FPGA2) initialization */ | |
481 | #define CFG_EBC_PB3AP 0x01004400 | |
482 | #define CFG_EBC_PB3CR (CFG_FPGA_BASE_1 | 0x1c000) | |
483 | ||
484 | #define CFG_EBC_CFG 0xb8400000 | |
485 | ||
04e6c38b SR |
486 | /*----------------------------------------------------------------------- |
487 | * Graphics (Fujitsu Lime) | |
488 | *----------------------------------------------------------------------*/ | |
489 | /* SDRAM Clock frequency adjustment register */ | |
b66091de AG |
490 | #define CFG_LIME_SDRAM_CLOCK 0xC1FC0038 |
491 | /* Lime Clock frequency is to set 100MHz */ | |
492 | #define CFG_LIME_CLOCK_100MHZ 0x00000 | |
493 | #if 0 | |
494 | /* Lime Clock frequency for 133MHz */ | |
04e6c38b | 495 | #define CFG_LIME_CLOCK_133MHZ 0x10000 |
b66091de | 496 | #endif |
04e6c38b SR |
497 | |
498 | /* SDRAM Parameter register */ | |
499 | #define CFG_LIME_MMR 0xC1FCFFFC | |
b66091de AG |
500 | /* SDRAM parameter value; was 0x414FB7F2, caused several vertical bars |
501 | and pixel flare on display when 133MHz was configured. According to | |
502 | SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed Grade */ | |
503 | #ifdef CFG_LIME_CLOCK_133MHZ | |
504 | #define CFG_LIME_MMR_VALUE 0x414FB7F3 | |
505 | #else | |
04e6c38b | 506 | #define CFG_LIME_MMR_VALUE 0x414FB7F2 |
b66091de | 507 | #endif |
04e6c38b | 508 | |
b765ffb7 SR |
509 | /*----------------------------------------------------------------------- |
510 | * GPIO Setup | |
511 | *----------------------------------------------------------------------*/ | |
512 | #define CFG_GPIO_PHY1_RST 12 | |
513 | #define CFG_GPIO_FLASH_WP 14 | |
514 | #define CFG_GPIO_PHY0_RST 22 | |
65b20dce | 515 | #define CFG_GPIO_DSPIC_READY 51 |
c25dd8fc | 516 | #define CFG_GPIO_EEPROM_EXT_WP 55 |
65b20dce | 517 | #define CFG_GPIO_HIGHSIDE 56 |
c25dd8fc | 518 | #define CFG_GPIO_EEPROM_INT_WP 57 |
b765ffb7 SR |
519 | #define CFG_GPIO_LIME_S 59 |
520 | #define CFG_GPIO_LIME_RST 60 | |
65b20dce | 521 | #define CFG_GPIO_SYSMON_STATUS 62 |
d7bfa620 | 522 | #define CFG_GPIO_WATCHDOG 63 |
b765ffb7 SR |
523 | |
524 | /*----------------------------------------------------------------------- | |
525 | * PPC440 GPIO Configuration | |
526 | */ | |
aee747f1 | 527 | #define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ |
b765ffb7 SR |
528 | { \ |
529 | /* GPIO Core 0 */ \ | |
530 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \ | |
531 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \ | |
532 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \ | |
533 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \ | |
534 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \ | |
535 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \ | |
536 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \ | |
537 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \ | |
538 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \ | |
539 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \ | |
540 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \ | |
541 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \ | |
542 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \ | |
543 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \ | |
544 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \ | |
20d500d5 | 545 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO15 */ \ |
1636d1c8 | 546 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4) */ \ |
b765ffb7 SR |
547 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5) */ \ |
548 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6) */ \ | |
549 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMCTxD(7) */ \ | |
550 | {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \ | |
551 | {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \ | |
552 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \ | |
553 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0 */ \ | |
554 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 GMCTxD(2) */ \ | |
555 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 GMCTxD(3) */ \ | |
556 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \ | |
557 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \ | |
558 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 USB2D_TXVALID */ \ | |
559 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \ | |
560 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \ | |
561 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \ | |
562 | }, \ | |
563 | { \ | |
564 | /* GPIO Core 1 */ \ | |
565 | {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \ | |
566 | {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \ | |
567 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \ | |
568 | {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \ | |
569 | {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0) UART3_SIN*/ \ | |
570 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \ | |
571 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \ | |
572 | {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \ | |
573 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \ | |
574 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \ | |
575 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \ | |
576 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \ | |
577 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \ | |
578 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \ | |
579 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \ | |
580 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \ | |
581 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \ | |
582 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO49 Unselect via TraceSelect Bit */ \ | |
04e6c38b | 583 | {GPIO1_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \ |
b765ffb7 SR |
584 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \ |
585 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \ | |
20d500d5 | 586 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \ |
b765ffb7 SR |
587 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \ |
588 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55 Unselect via TraceSelect Bit */ \ | |
589 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \ | |
590 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO57 Unselect via TraceSelect Bit */ \ | |
3e954beb | 591 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \ |
b765ffb7 SR |
592 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \ |
593 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \ | |
594 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \ | |
595 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \ | |
596 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \ | |
597 | } \ | |
598 | } | |
599 | ||
b765ffb7 SR |
600 | /* |
601 | * Internal Definitions | |
602 | * | |
603 | * Boot Flags | |
604 | */ | |
605 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
606 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
607 | ||
a22d4da9 | 608 | #if defined(CONFIG_CMD_KGDB) |
b765ffb7 SR |
609 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
610 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
611 | #endif | |
612 | #endif /* __CONFIG_H */ |