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Commit | Line | Data |
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b765ffb7 | 1 | /* |
f47b048b | 2 | * (C) Copyright 2007-2013 |
b765ffb7 SR |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
b765ffb7 SR |
6 | */ |
7 | ||
f14ae418 | 8 | /* |
b765ffb7 | 9 | * lwmon5.h - configuration for lwmon5 board |
f14ae418 | 10 | */ |
b765ffb7 SR |
11 | #ifndef __CONFIG_H |
12 | #define __CONFIG_H | |
13 | ||
f14ae418 SL |
14 | /* |
15 | * Liebherr extra version info | |
16 | */ | |
17 | #define CONFIG_IDENT_STRING " - v2.0" | |
18 | ||
19 | /* | |
b765ffb7 | 20 | * High Level Configuration Options |
f14ae418 | 21 | */ |
b765ffb7 SR |
22 | #define CONFIG_LWMON5 1 /* Board is lwmon5 */ |
23 | #define CONFIG_440EPX 1 /* Specific PPC440EPx */ | |
e73846b7 | 24 | #define CONFIG_440 1 /* ... PPC440 family */ |
2ae18241 | 25 | |
f47b048b SR |
26 | #ifdef CONFIG_LCD4_LWMON5 |
27 | #define CONFIG_SYS_TEXT_BASE 0x01000000 /* SPL U-Boot TEXT_BASE */ | |
28 | #define CONFIG_HOSTNAME lcd4_lwmon5 | |
29 | #else | |
2ae18241 | 30 | #define CONFIG_SYS_TEXT_BASE 0xFFF80000 |
f47b048b | 31 | #define CONFIG_HOSTNAME lwmon5 |
2ae18241 WD |
32 | #endif |
33 | ||
b765ffb7 SR |
34 | #define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */ |
35 | ||
a321148b SR |
36 | #define CONFIG_4xx_DCACHE /* enable cache in SDRAM */ |
37 | ||
f14ae418 SL |
38 | #define CONFIG_BOARD_EARLY_INIT_F /* Call board_early_init_f */ |
39 | #define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r */ | |
40 | #define CONFIG_BOARD_POSTCLK_INIT /* Call board_postclk_init */ | |
41 | #define CONFIG_MISC_INIT_R /* Call misc_init_r */ | |
42 | #define CONFIG_BOARD_RESET /* Call board_reset */ | |
b765ffb7 | 43 | |
f14ae418 | 44 | /* |
b765ffb7 SR |
45 | * Base addresses -- Note these are effective addresses where the |
46 | * actual resources get mapped (not physical addresses) | |
f14ae418 | 47 | */ |
14d0a02a | 48 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of U-Boot */ |
f47b048b | 49 | #define CONFIG_SYS_MONITOR_LEN 0x80000 |
f14ae418 | 50 | #define CONFIG_SYS_MALLOC_LEN (1 << 20) /* Reserved for malloc */ |
6d0f6bcf JCPV |
51 | |
52 | #define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000 | |
53 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ | |
54 | #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */ | |
f14ae418 SL |
55 | #define CONFIG_SYS_LIME_BASE_0 0xc0000000 |
56 | #define CONFIG_SYS_LIME_BASE_1 0xc1000000 | |
57 | #define CONFIG_SYS_LIME_BASE_2 0xc2000000 | |
58 | #define CONFIG_SYS_LIME_BASE_3 0xc3000000 | |
59 | #define CONFIG_SYS_FPGA_BASE_0 0xc4000000 | |
60 | #define CONFIG_SYS_FPGA_BASE_1 0xc4200000 | |
6d0f6bcf JCPV |
61 | #define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */ |
62 | #define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */ | |
63 | #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ | |
f14ae418 SL |
64 | #define CONFIG_SYS_PCI_MEMBASE1 (CONFIG_SYS_PCI_MEMBASE + 0x10000000) |
65 | #define CONFIG_SYS_PCI_MEMBASE2 (CONFIG_SYS_PCI_MEMBASE1 + 0x10000000) | |
66 | #define CONFIG_SYS_PCI_MEMBASE3 (CONFIG_SYS_PCI_MEMBASE2 + 0x10000000) | |
b765ffb7 | 67 | |
f47b048b | 68 | #ifndef CONFIG_LCD4_LWMON5 |
6d0f6bcf JCPV |
69 | #define CONFIG_SYS_USB2D0_BASE 0xe0000100 |
70 | #define CONFIG_SYS_USB_DEVICE 0xe0000000 | |
71 | #define CONFIG_SYS_USB_HOST 0xe0000400 | |
f47b048b | 72 | #endif |
b765ffb7 | 73 | |
8f24e063 | 74 | /* |
f14ae418 SL |
75 | * Initial RAM & stack pointer |
76 | * | |
8f24e063 SR |
77 | * On LWMON5 we use D-cache as init-ram and stack pointer. We also move |
78 | * the POST_WORD from OCM to a 440EPx register that preserves it's | |
eb0615bf YT |
79 | * content during reset (GPT0_COMP6). This way we reserve the OCM (16k) |
80 | * for logbuffer only. (GPT0_COMP1-COMP5 are reserved for logbuffer header.) | |
8f24e063 | 81 | */ |
f47b048b | 82 | #ifndef CONFIG_LCD4_LWMON5 |
6d0f6bcf JCPV |
83 | #define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */ |
84 | #define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */ | |
553f0982 | 85 | #define CONFIG_SYS_INIT_RAM_SIZE (4 << 10) |
553f0982 | 86 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ |
25ddd1fb | 87 | GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 88 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
f47b048b SR |
89 | #else |
90 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE | |
91 | #define CONFIG_SYS_INIT_RAM_SIZE (4 << 10) | |
92 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ | |
93 | GENERATED_GBL_DATA_SIZE) | |
94 | #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) | |
95 | #endif | |
f14ae418 | 96 | /* unused GPT0 COMP reg */ |
800eb096 | 97 | #define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6) |
6d0f6bcf | 98 | #define CONFIG_SYS_OCM_SIZE (16 << 10) |
f14ae418 SL |
99 | /* 440EPx errata CHIP 11: don't use last 4kbytes */ |
100 | #define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) | |
b765ffb7 | 101 | |
8f15d4ad | 102 | /* Additional registers for watchdog timer post test */ |
6d0f6bcf JCPV |
103 | #define CONFIG_SYS_WATCHDOG_TIME_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK2) |
104 | #define CONFIG_SYS_WATCHDOG_FLAGS_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK1) | |
105 | #define CONFIG_SYS_DSPIC_TEST_ADDR CONFIG_SYS_WATCHDOG_FLAGS_ADDR | |
106 | #define CONFIG_SYS_OCM_STATUS_ADDR CONFIG_SYS_WATCHDOG_FLAGS_ADDR | |
107 | #define CONFIG_SYS_WATCHDOG_MAGIC 0x12480000 | |
108 | #define CONFIG_SYS_WATCHDOG_MAGIC_MASK 0xFFFF0000 | |
109 | #define CONFIG_SYS_DSPIC_TEST_MASK 0x00000001 | |
110 | #define CONFIG_SYS_OCM_STATUS_OK 0x00009A00 | |
111 | #define CONFIG_SYS_OCM_STATUS_FAIL 0x0000A300 | |
112 | #define CONFIG_SYS_OCM_STATUS_MASK 0x0000FF00 | |
8f15d4ad | 113 | |
f14ae418 | 114 | /* |
b765ffb7 | 115 | * Serial Port |
f14ae418 | 116 | */ |
550650dd SR |
117 | #define CONFIG_CONS_INDEX 2 /* Use UART1 */ |
118 | #define CONFIG_SYS_NS16550 | |
119 | #define CONFIG_SYS_NS16550_SERIAL | |
120 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
121 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() | |
6d0f6bcf | 122 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external clock provided */ |
b765ffb7 | 123 | #define CONFIG_BAUDRATE 115200 |
b765ffb7 | 124 | |
6d0f6bcf | 125 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
b765ffb7 SR |
126 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} |
127 | ||
f14ae418 | 128 | /* |
b765ffb7 | 129 | * Environment |
f14ae418 SL |
130 | */ |
131 | #define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */ | |
b765ffb7 | 132 | |
f14ae418 | 133 | /* |
b765ffb7 | 134 | * FLASH related |
f14ae418 SL |
135 | */ |
136 | #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ | |
00b1883a | 137 | #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ |
b765ffb7 | 138 | |
6d0f6bcf JCPV |
139 | #define CONFIG_SYS_FLASH0 0xFC000000 |
140 | #define CONFIG_SYS_FLASH1 0xF8000000 | |
141 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 } | |
b765ffb7 | 142 | |
f14ae418 | 143 | #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 /* max number of memory banks */ |
6d0f6bcf | 144 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ |
b765ffb7 | 145 | |
6d0f6bcf JCPV |
146 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
147 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
b765ffb7 | 148 | |
f14ae418 SL |
149 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */ |
150 | #define CONFIG_SYS_FLASH_PROTECTION /* use hardware flash protection */ | |
b765ffb7 | 151 | |
6d0f6bcf | 152 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
f14ae418 | 153 | #define CONFIG_SYS_FLASH_QUIET_TEST /* don't warn upon unknown flash */ |
b765ffb7 | 154 | |
0e8d1586 | 155 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */ |
f14ae418 | 156 | #define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN) - CONFIG_ENV_SECT_SIZE) |
0e8d1586 | 157 | #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ |
b765ffb7 SR |
158 | |
159 | /* Address and size of Redundant Environment Sector */ | |
f14ae418 | 160 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE) |
0e8d1586 | 161 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) |
b765ffb7 | 162 | |
f14ae418 | 163 | /* |
b765ffb7 | 164 | * DDR SDRAM |
f14ae418 SL |
165 | */ |
166 | #define CONFIG_SYS_MBYTES_SDRAM 256 | |
6d0f6bcf | 167 | #define CONFIG_SYS_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */ |
f14ae418 | 168 | #define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */ |
f47b048b | 169 | #ifndef CONFIG_LCD4_LWMON5 |
f14ae418 | 170 | #define CONFIG_DDR_ECC /* enable ECC */ |
f47b048b | 171 | #endif |
531e3e8b | 172 | |
f47b048b | 173 | #ifndef CONFIG_LCD4_LWMON5 |
531e3e8b | 174 | /* POST support */ |
f14ae418 SL |
175 | #define CONFIG_POST (CONFIG_SYS_POST_CACHE | \ |
176 | CONFIG_SYS_POST_CPU | \ | |
177 | CONFIG_SYS_POST_ECC | \ | |
178 | CONFIG_SYS_POST_ETHER | \ | |
179 | CONFIG_SYS_POST_FPU | \ | |
180 | CONFIG_SYS_POST_I2C | \ | |
181 | CONFIG_SYS_POST_MEMORY | \ | |
182 | CONFIG_SYS_POST_OCM | \ | |
183 | CONFIG_SYS_POST_RTC | \ | |
184 | CONFIG_SYS_POST_SPR | \ | |
185 | CONFIG_SYS_POST_UART | \ | |
186 | CONFIG_SYS_POST_SYSMON | \ | |
187 | CONFIG_SYS_POST_WATCHDOG | \ | |
188 | CONFIG_SYS_POST_DSP | \ | |
189 | CONFIG_SYS_POST_BSPEC1 | \ | |
190 | CONFIG_SYS_POST_BSPEC2 | \ | |
191 | CONFIG_SYS_POST_BSPEC3 | \ | |
192 | CONFIG_SYS_POST_BSPEC4 | \ | |
6d0f6bcf | 193 | CONFIG_SYS_POST_BSPEC5) |
8f15d4ad | 194 | |
f14ae418 | 195 | /* Define here the base-addresses of the UARTs to test in POST */ |
5d7c73e6 SR |
196 | #define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \ |
197 | CONFIG_SYS_NS16550_COM2 } | |
f14ae418 | 198 | |
834a45d7 SR |
199 | #define CONFIG_POST_UART { \ |
200 | "UART test", \ | |
201 | "uart", \ | |
202 | "This test verifies the UART operation.", \ | |
203 | POST_RAM | POST_SLOWTEST | POST_ALWAYS | POST_MANUAL, \ | |
204 | &uart_post_test, \ | |
205 | NULL, \ | |
206 | NULL, \ | |
207 | CONFIG_SYS_POST_UART \ | |
208 | } | |
209 | ||
f14ae418 | 210 | #define CONFIG_POST_WATCHDOG { \ |
8f15d4ad YT |
211 | "Watchdog timer test", \ |
212 | "watchdog", \ | |
213 | "This test checks the watchdog timer.", \ | |
214 | POST_RAM | POST_POWERON | POST_SLOWTEST | POST_MANUAL | POST_REBOOT, \ | |
215 | &lwmon5_watchdog_post_test, \ | |
216 | NULL, \ | |
217 | NULL, \ | |
f14ae418 | 218 | CONFIG_SYS_POST_WATCHDOG \ |
8f15d4ad YT |
219 | } |
220 | ||
f14ae418 | 221 | #define CONFIG_POST_BSPEC1 { \ |
8f15d4ad YT |
222 | "dsPIC init test", \ |
223 | "dspic_init", \ | |
224 | "This test returns result of dsPIC READY test run earlier.", \ | |
225 | POST_RAM | POST_ALWAYS, \ | |
226 | &dspic_init_post_test, \ | |
227 | NULL, \ | |
228 | NULL, \ | |
f14ae418 | 229 | CONFIG_SYS_POST_BSPEC1 \ |
8f15d4ad YT |
230 | } |
231 | ||
f14ae418 | 232 | #define CONFIG_POST_BSPEC2 { \ |
8f15d4ad YT |
233 | "dsPIC test", \ |
234 | "dspic", \ | |
235 | "This test gets result of dsPIC POST and dsPIC version.", \ | |
236 | POST_RAM | POST_ALWAYS, \ | |
237 | &dspic_post_test, \ | |
238 | NULL, \ | |
239 | NULL, \ | |
f14ae418 | 240 | CONFIG_SYS_POST_BSPEC2 \ |
8f15d4ad YT |
241 | } |
242 | ||
f14ae418 | 243 | #define CONFIG_POST_BSPEC3 { \ |
8f15d4ad YT |
244 | "FPGA test", \ |
245 | "fpga", \ | |
246 | "This test checks FPGA registers and memory.", \ | |
f14ae418 | 247 | POST_RAM | POST_ALWAYS | POST_MANUAL, \ |
8f15d4ad YT |
248 | &fpga_post_test, \ |
249 | NULL, \ | |
250 | NULL, \ | |
f14ae418 | 251 | CONFIG_SYS_POST_BSPEC3 \ |
8f15d4ad YT |
252 | } |
253 | ||
f14ae418 | 254 | #define CONFIG_POST_BSPEC4 { \ |
8f15d4ad YT |
255 | "GDC test", \ |
256 | "gdc", \ | |
257 | "This test checks GDC registers and memory.", \ | |
f14ae418 | 258 | POST_RAM | POST_ALWAYS | POST_MANUAL,\ |
8f15d4ad YT |
259 | &gdc_post_test, \ |
260 | NULL, \ | |
261 | NULL, \ | |
f14ae418 | 262 | CONFIG_SYS_POST_BSPEC4 \ |
8f15d4ad YT |
263 | } |
264 | ||
f14ae418 | 265 | #define CONFIG_POST_BSPEC5 { \ |
8f15d4ad YT |
266 | "SYSMON1 test", \ |
267 | "sysmon1", \ | |
268 | "This test checks GPIO_62_EPX pin indicating power failure.", \ | |
269 | POST_RAM | POST_MANUAL | POST_NORMAL | POST_SLOWTEST, \ | |
270 | &sysmon1_post_test, \ | |
271 | NULL, \ | |
272 | NULL, \ | |
f14ae418 | 273 | CONFIG_SYS_POST_BSPEC5 \ |
8f15d4ad | 274 | } |
3e4c90c6 | 275 | |
6d0f6bcf | 276 | #define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */ |
3e4c90c6 | 277 | #define CONFIG_LOGBUFFER |
eb0615bf | 278 | /* Reserve GPT0_COMP1-COMP5 for logbuffer header */ |
6d0f6bcf JCPV |
279 | #define CONFIG_ALT_LH_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP1) |
280 | #define CONFIG_ALT_LB_ADDR (CONFIG_SYS_OCM_BASE) | |
281 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ | |
f47b048b | 282 | #endif |
b765ffb7 | 283 | |
f14ae418 | 284 | /* |
b765ffb7 | 285 | * I2C |
f14ae418 | 286 | */ |
880540de DE |
287 | #define CONFIG_SYS_I2C |
288 | #define CONFIG_SYS_I2C_PPC4XX | |
289 | #define CONFIG_SYS_I2C_PPC4XX_CH0 | |
290 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000 | |
291 | #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F | |
b765ffb7 | 292 | |
f14ae418 SL |
293 | #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* RTC */ |
294 | #define CONFIG_SYS_I2C_EEPROM_CPU_ADDR 0x52 /* EEPROM (CPU Modul) */ | |
295 | #define CONFIG_SYS_I2C_EEPROM_MB_ADDR 0x53 /* EEPROM AT24C128 (MainBoard) */ | |
296 | #define CONFIG_SYS_I2C_DSPIC_ADDR 0x54 /* dsPIC */ | |
297 | #define CONFIG_SYS_I2C_DSPIC_2_ADDR 0x55 /* dsPIC */ | |
298 | #define CONFIG_SYS_I2C_DSPIC_KEYB_ADDR 0x56 /* dsPIC */ | |
299 | #define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* dsPIC */ | |
300 | ||
6d0f6bcf JCPV |
301 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ |
302 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel AT24C128 has */ | |
c25dd8fc SR |
303 | /* 64 byte page write mode using*/ |
304 | /* last 6 bits of the address */ | |
6d0f6bcf | 305 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
f14ae418 SL |
306 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE |
307 | ||
308 | #define CONFIG_RTC_PCF8563 /* enable Philips PCF8563 RTC */ | |
309 | #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */ | |
310 | #define CONFIG_SYS_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */ | |
311 | #define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* PIC I/O addr */ | |
312 | ||
60aaaa07 PT |
313 | #define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_RTC_ADDR, \ |
314 | CONFIG_SYS_I2C_EEPROM_CPU_ADDR,\ | |
315 | CONFIG_SYS_I2C_EEPROM_MB_ADDR, \ | |
316 | CONFIG_SYS_I2C_DSPIC_ADDR, \ | |
317 | CONFIG_SYS_I2C_DSPIC_2_ADDR, \ | |
318 | CONFIG_SYS_I2C_DSPIC_KEYB_ADDR,\ | |
319 | CONFIG_SYS_I2C_DSPIC_IO_ADDR } | |
b765ffb7 | 320 | |
f14ae418 SL |
321 | /* |
322 | * Pass open firmware flat tree | |
323 | */ | |
324 | #define CONFIG_OF_LIBFDT | |
325 | #define CONFIG_OF_BOARD_SETUP | |
326 | /* Update size in "reg" property of NOR FLASH device tree nodes */ | |
327 | #define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE | |
b765ffb7 | 328 | |
a321148b SR |
329 | #define CONFIG_FIT /* enable FIT image support */ |
330 | ||
3ad63878 | 331 | #define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */ |
3ad63878 SR |
332 | |
333 | #define CONFIG_PREBOOT "setenv bootdelay 15" | |
b765ffb7 SR |
334 | |
335 | #undef CONFIG_BOOTARGS | |
336 | ||
337 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
338 | "hostname=lwmon5\0" \ | |
339 | "netdev=eth0\0" \ | |
5d187430 | 340 | "unlock=yes\0" \ |
3e4c90c6 | 341 | "logversion=2\0" \ |
b765ffb7 SR |
342 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
343 | "nfsroot=${serverip}:${rootpath}\0" \ | |
344 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
345 | "addip=setenv bootargs ${bootargs} " \ | |
346 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
347 | ":${hostname}:${netdev}:off panic=1\0" \ | |
348 | "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\ | |
04625764 SR |
349 | "addmisc=setenv bootargs ${bootargs} rtc-pcf8563.probe=0,0x51\0"\ |
350 | "flash_nfs=run nfsargs addip addtty addmisc;" \ | |
b765ffb7 | 351 | "bootm ${kernel_addr}\0" \ |
04625764 | 352 | "flash_self=run ramargs addip addtty addmisc;" \ |
b765ffb7 | 353 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
04625764 SR |
354 | "net_nfs=tftp 200000 ${bootfile};" \ |
355 | "run nfsargs addip addtty addmisc;bootm\0" \ | |
b765ffb7 SR |
356 | "rootpath=/opt/eldk/ppc_4xxFP\0" \ |
357 | "bootfile=/tftpboot/lwmon5/uImage\0" \ | |
358 | "kernel_addr=FC000000\0" \ | |
359 | "ramdisk_addr=FC180000\0" \ | |
360 | "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \ | |
361 | "update=protect off FFF80000 FFFFFFFF;era FFF80000 FFFFFFFF;" \ | |
362 | "cp.b 200000 FFF80000 80000\0" \ | |
d8ab58b2 | 363 | "upd=run load update\0" \ |
334043f6 | 364 | "lwe_env=tftp 200000 /tftpboot.dev/lwmon5/env_uboot.bin;" \ |
f14ae418 | 365 | "autoscr 200000\0" \ |
b765ffb7 SR |
366 | "" |
367 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
368 | ||
b765ffb7 | 369 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
b765ffb7 SR |
370 | |
371 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 372 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
b765ffb7 | 373 | |
96e21f86 | 374 | #define CONFIG_PPC4xx_EMAC |
b765ffb7 SR |
375 | #define CONFIG_IBM_EMAC4_V4 1 |
376 | #define CONFIG_MII 1 /* MII PHY management */ | |
377 | #define CONFIG_PHY_ADDR 3 /* PHY address, See schematics */ | |
378 | ||
379 | #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ | |
3ad63878 | 380 | #define CONFIG_PHY_RESET_DELAY 300 |
b765ffb7 SR |
381 | |
382 | #define CONFIG_HAS_ETH0 | |
6d0f6bcf | 383 | #define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ |
b765ffb7 | 384 | |
b765ffb7 SR |
385 | #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ |
386 | #define CONFIG_PHY1_ADDR 1 | |
387 | ||
d610a607 AG |
388 | /* Video console */ |
389 | #define CONFIG_VIDEO | |
390 | #define CONFIG_VIDEO_MB862xx | |
5d16ca87 | 391 | #define CONFIG_VIDEO_MB862xx_ACCEL |
d610a607 AG |
392 | #define CONFIG_CFB_CONSOLE |
393 | #define CONFIG_VIDEO_LOGO | |
394 | #define CONFIG_CONSOLE_EXTRA_INFO | |
395 | #define VIDEO_FB_16BPP_PIXEL_SWAP | |
229b6dce | 396 | #define VIDEO_FB_16BPP_WORD_SWAP |
d610a607 AG |
397 | |
398 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
399 | #define CONFIG_VIDEO_SW_CURSOR | |
400 | #define CONFIG_SPLASH_SCREEN | |
401 | ||
f47b048b | 402 | #ifndef CONFIG_LCD4_LWMON5 |
a321148b SR |
403 | /* |
404 | * USB/EHCI | |
405 | */ | |
406 | #define CONFIG_USB_EHCI /* Enable EHCI USB support */ | |
407 | #define CONFIG_USB_EHCI_PPC4XX /* on PPC4xx platform */ | |
408 | #define CONFIG_SYS_PPC4XX_USB_ADDR 0xe0000300 | |
a321148b SR |
409 | #define CONFIG_EHCI_MMIO_BIG_ENDIAN |
410 | #define CONFIG_EHCI_DESC_BIG_ENDIAN | |
411 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */ | |
b765ffb7 SR |
412 | #define CONFIG_USB_STORAGE |
413 | ||
b765ffb7 SR |
414 | /* Partitions */ |
415 | #define CONFIG_MAC_PARTITION | |
416 | #define CONFIG_DOS_PARTITION | |
417 | #define CONFIG_ISO_PARTITION | |
f47b048b | 418 | #endif |
b765ffb7 | 419 | |
079a136c JL |
420 | /* |
421 | * BOOTP options | |
422 | */ | |
423 | #define CONFIG_BOOTP_BOOTFILESIZE | |
424 | #define CONFIG_BOOTP_BOOTPATH | |
425 | #define CONFIG_BOOTP_GATEWAY | |
426 | #define CONFIG_BOOTP_HOSTNAME | |
b765ffb7 | 427 | |
a22d4da9 JL |
428 | /* |
429 | * Command line configuration. | |
430 | */ | |
a22d4da9 JL |
431 | #define CONFIG_CMD_ASKENV |
432 | #define CONFIG_CMD_DATE | |
433 | #define CONFIG_CMD_DHCP | |
434 | #define CONFIG_CMD_DIAG | |
435 | #define CONFIG_CMD_EEPROM | |
436 | #define CONFIG_CMD_ELF | |
437 | #define CONFIG_CMD_FAT | |
438 | #define CONFIG_CMD_I2C | |
439 | #define CONFIG_CMD_IRQ | |
440 | #define CONFIG_CMD_MII | |
a22d4da9 JL |
441 | #define CONFIG_CMD_PING |
442 | #define CONFIG_CMD_REGINFO | |
443 | #define CONFIG_CMD_SDRAM | |
b765ffb7 | 444 | |
d610a607 AG |
445 | #ifdef CONFIG_VIDEO |
446 | #define CONFIG_CMD_BMP | |
447 | #endif | |
448 | ||
f47b048b | 449 | #ifndef CONFIG_LCD4_LWMON5 |
a22d4da9 JL |
450 | #ifdef CONFIG_440EPX |
451 | #define CONFIG_CMD_USB | |
452 | #endif | |
f47b048b | 453 | #endif |
b765ffb7 | 454 | |
f14ae418 | 455 | /* |
b765ffb7 | 456 | * Miscellaneous configurable options |
f14ae418 | 457 | */ |
a22d4da9 JL |
458 | #define CONFIG_SUPPORT_VFAT |
459 | ||
6d0f6bcf | 460 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
58d20425 | 461 | |
6d0f6bcf | 462 | #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ |
58d20425 | 463 | |
a22d4da9 | 464 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 465 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
b765ffb7 | 466 | #else |
6d0f6bcf | 467 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
b765ffb7 | 468 | #endif |
6d0f6bcf JCPV |
469 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
470 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
471 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
b765ffb7 | 472 | |
6d0f6bcf JCPV |
473 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
474 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
b765ffb7 | 475 | |
6d0f6bcf JCPV |
476 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
477 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
b765ffb7 | 478 | |
b765ffb7 SR |
479 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
480 | #define CONFIG_LOOPW 1 /* enable loopw command */ | |
481 | #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ | |
b765ffb7 SR |
482 | #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ |
483 | ||
f47b048b SR |
484 | #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/ |
485 | ||
486 | #ifndef CONFIG_LCD4_LWMON5 | |
f14ae418 | 487 | #ifndef DEBUG |
b765ffb7 | 488 | #define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */ |
f14ae418 | 489 | #endif |
2e721094 | 490 | #define CONFIG_WD_PERIOD 40000 /* in usec */ |
d32a874b | 491 | #define CONFIG_WD_MAX_RATE 66600 /* in ticks */ |
f47b048b | 492 | #endif |
b765ffb7 SR |
493 | |
494 | /* | |
495 | * For booting Linux, the board info and command line data | |
f14ae418 SL |
496 | * have to be in the first 16 MB of memory, since this is |
497 | * the maximum mapped by the 40x Linux kernel during initialization. | |
b765ffb7 | 498 | */ |
f14ae418 SL |
499 | #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux */ |
500 | #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ | |
b765ffb7 | 501 | |
f14ae418 | 502 | /* |
b765ffb7 | 503 | * External Bus Controller (EBC) Setup |
f14ae418 | 504 | */ |
6d0f6bcf | 505 | #define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE |
b765ffb7 SR |
506 | |
507 | /* Memory Bank 0 (NOR-FLASH) initialization */ | |
f14ae418 | 508 | #define CONFIG_SYS_EBC_PB0AP 0x03000280 |
6d0f6bcf | 509 | #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0xfc000) |
b765ffb7 SR |
510 | |
511 | /* Memory Bank 1 (Lime) initialization */ | |
6d0f6bcf | 512 | #define CONFIG_SYS_EBC_PB1AP 0x01004380 |
f14ae418 | 513 | #define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_LIME_BASE_0 | 0xbc000) |
b765ffb7 SR |
514 | |
515 | /* Memory Bank 2 (FPGA) initialization */ | |
6d0f6bcf JCPV |
516 | #define CONFIG_SYS_EBC_PB2AP 0x01004400 |
517 | #define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA_BASE_0 | 0x1c000) | |
b765ffb7 SR |
518 | |
519 | /* Memory Bank 3 (FPGA2) initialization */ | |
6d0f6bcf JCPV |
520 | #define CONFIG_SYS_EBC_PB3AP 0x01004400 |
521 | #define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_FPGA_BASE_1 | 0x1c000) | |
b765ffb7 | 522 | |
6d0f6bcf | 523 | #define CONFIG_SYS_EBC_CFG 0xb8400000 |
b765ffb7 | 524 | |
f14ae418 | 525 | /* |
04e6c38b | 526 | * Graphics (Fujitsu Lime) |
f14ae418 SL |
527 | */ |
528 | /* SDRAM Clock frequency adjustment register */ | |
529 | #define CONFIG_SYS_LIME_SDRAM_CLOCK 0xC1FC0038 | |
530 | #if 1 /* 133MHz is not tested enough, use 100MHz for now */ | |
b66091de | 531 | /* Lime Clock frequency is to set 100MHz */ |
6d0f6bcf | 532 | #define CONFIG_SYS_LIME_CLOCK_100MHZ 0x00000 |
f14ae418 | 533 | #else |
b66091de | 534 | /* Lime Clock frequency for 133MHz */ |
6d0f6bcf | 535 | #define CONFIG_SYS_LIME_CLOCK_133MHZ 0x10000 |
b66091de | 536 | #endif |
04e6c38b | 537 | |
f14ae418 SL |
538 | /* SDRAM Parameter register */ |
539 | #define CONFIG_SYS_LIME_MMR 0xC1FCFFFC | |
540 | /* | |
541 | * SDRAM parameter value; was 0x414FB7F2, caused several vertical bars | |
542 | * and pixel flare on display when 133MHz was configured. According to | |
543 | * SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed | |
544 | * Grade | |
545 | */ | |
6d0f6bcf | 546 | #ifdef CONFIG_SYS_LIME_CLOCK_133MHZ |
c28d3bbe WG |
547 | #define CONFIG_SYS_MB862xx_MMR 0x414FB7F3 |
548 | #define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_133MHZ | |
b66091de | 549 | #else |
c28d3bbe WG |
550 | #define CONFIG_SYS_MB862xx_MMR 0x414FB7F2 |
551 | #define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_100MHZ | |
b66091de | 552 | #endif |
04e6c38b | 553 | |
f14ae418 | 554 | /* |
b765ffb7 | 555 | * GPIO Setup |
f14ae418 | 556 | */ |
6d0f6bcf JCPV |
557 | #define CONFIG_SYS_GPIO_PHY1_RST 12 |
558 | #define CONFIG_SYS_GPIO_FLASH_WP 14 | |
559 | #define CONFIG_SYS_GPIO_PHY0_RST 22 | |
9055f66c | 560 | #define CONFIG_SYS_GPIO_PERM_VOLT_FEED 49 |
6d0f6bcf | 561 | #define CONFIG_SYS_GPIO_DSPIC_READY 51 |
f14ae418 SL |
562 | #define CONFIG_SYS_GPIO_CAN_ENABLE 53 |
563 | #define CONFIG_SYS_GPIO_LSB_ENABLE 54 | |
6d0f6bcf JCPV |
564 | #define CONFIG_SYS_GPIO_EEPROM_EXT_WP 55 |
565 | #define CONFIG_SYS_GPIO_HIGHSIDE 56 | |
566 | #define CONFIG_SYS_GPIO_EEPROM_INT_WP 57 | |
567 | #define CONFIG_SYS_GPIO_BOARD_RESET 58 | |
568 | #define CONFIG_SYS_GPIO_LIME_S 59 | |
569 | #define CONFIG_SYS_GPIO_LIME_RST 60 | |
570 | #define CONFIG_SYS_GPIO_SYSMON_STATUS 62 | |
571 | #define CONFIG_SYS_GPIO_WATCHDOG 63 | |
b765ffb7 | 572 | |
9055f66c SR |
573 | /* On LCD4, GPIO49 has to be configured to 0 instead of 1 */ |
574 | #ifdef CONFIG_LCD4_LWMON5 | |
575 | #define GPIO49_VAL 0 | |
576 | #else | |
577 | #define GPIO49_VAL 1 | |
578 | #endif | |
579 | ||
f14ae418 | 580 | /* |
b765ffb7 SR |
581 | * PPC440 GPIO Configuration |
582 | */ | |
6d0f6bcf | 583 | #define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ |
b765ffb7 SR |
584 | { \ |
585 | /* GPIO Core 0 */ \ | |
586 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \ | |
587 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \ | |
588 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \ | |
589 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \ | |
590 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \ | |
591 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \ | |
592 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \ | |
593 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \ | |
594 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \ | |
595 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \ | |
596 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \ | |
597 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \ | |
598 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \ | |
599 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \ | |
600 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \ | |
20d500d5 | 601 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO15 */ \ |
1636d1c8 | 602 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4) */ \ |
b765ffb7 SR |
603 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5) */ \ |
604 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6) */ \ | |
605 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMCTxD(7) */ \ | |
606 | {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \ | |
607 | {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \ | |
608 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \ | |
609 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0 */ \ | |
610 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 GMCTxD(2) */ \ | |
611 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 GMCTxD(3) */ \ | |
612 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \ | |
613 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \ | |
614 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 USB2D_TXVALID */ \ | |
615 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \ | |
616 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \ | |
617 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \ | |
618 | }, \ | |
619 | { \ | |
620 | /* GPIO Core 1 */ \ | |
621 | {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \ | |
622 | {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \ | |
623 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \ | |
624 | {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \ | |
625 | {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0) UART3_SIN*/ \ | |
626 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \ | |
627 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \ | |
628 | {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \ | |
629 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \ | |
630 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \ | |
631 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \ | |
632 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \ | |
633 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \ | |
634 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \ | |
635 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \ | |
636 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \ | |
637 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \ | |
9055f66c | 638 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO49_VAL}, /* GPIO49 Unselect via TraceSelect Bit */ \ |
04e6c38b | 639 | {GPIO1_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \ |
b765ffb7 SR |
640 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \ |
641 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \ | |
20d500d5 | 642 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \ |
b765ffb7 SR |
643 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \ |
644 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55 Unselect via TraceSelect Bit */ \ | |
645 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \ | |
646 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO57 Unselect via TraceSelect Bit */ \ | |
3e954beb | 647 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \ |
b765ffb7 SR |
648 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \ |
649 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \ | |
650 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \ | |
651 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \ | |
652 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \ | |
653 | } \ | |
654 | } | |
655 | ||
a22d4da9 | 656 | #if defined(CONFIG_CMD_KGDB) |
b765ffb7 | 657 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
b765ffb7 | 658 | #endif |
f47b048b SR |
659 | |
660 | /* | |
661 | * SPL related defines | |
662 | */ | |
663 | #ifdef CONFIG_LCD4_LWMON5 | |
f47b048b SR |
664 | #define CONFIG_SPL_FRAMEWORK |
665 | #define CONFIG_SPL_BOARD_INIT | |
666 | #define CONFIG_SPL_NOR_SUPPORT | |
667 | #define CONFIG_SPL_TEXT_BASE 0xffff0000 /* last 64 KiB for SPL */ | |
668 | #define CONFIG_SYS_SPL_MAX_LEN (64 << 10) | |
669 | #define CONFIG_UBOOT_PAD_TO 458752 /* decimal for 'dd' */ | |
f47b048b SR |
670 | #define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */ |
671 | #define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */ | |
672 | #define CONFIG_SPL_SERIAL_SUPPORT | |
673 | ||
674 | /* Place BSS for SPL near end of SDRAM */ | |
675 | #define CONFIG_SPL_BSS_START_ADDR ((256 - 1) << 20) | |
676 | #define CONFIG_SPL_BSS_MAX_SIZE (64 << 10) | |
677 | ||
678 | #define CONFIG_SPL_OS_BOOT | |
679 | /* Place patched DT blob (fdt) at this address */ | |
680 | #define CONFIG_SYS_SPL_ARGS_ADDR 0x01800000 | |
681 | ||
682 | #define CONFIG_SPL_TARGET "u-boot-img-spl-at-end.bin" | |
683 | ||
684 | /* Settings for real U-Boot to be loaded from NOR flash */ | |
685 | #define CONFIG_SYS_UBOOT_BASE (-CONFIG_SYS_MONITOR_LEN) | |
686 | #define CONFIG_SYS_UBOOT_START 0x01002100 | |
687 | ||
688 | #define CONFIG_SYS_OS_BASE 0xf8000000 | |
689 | #define CONFIG_SYS_FDT_BASE 0xf87c0000 | |
690 | #endif | |
691 | ||
b765ffb7 | 692 | #endif /* __CONFIG_H */ |