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0f83b365 | 1 | /* |
2a4058c2 | 2 | * Aries M53 configuration |
0f83b365 MV |
3 | * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de> |
4 | * | |
3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
0f83b365 MV |
6 | */ |
7 | ||
8 | #ifndef __M53EVK_CONFIG_H__ | |
9 | #define __M53EVK_CONFIG_H__ | |
10 | ||
0f83b365 | 11 | #define CONFIG_MXC_GPIO |
0f83b365 MV |
12 | |
13 | #include <asm/arch/imx-regs.h> | |
14 | ||
0f83b365 | 15 | #define CONFIG_REVISION_TAG |
18fb0e3c | 16 | #define CONFIG_SYS_FSL_CLK |
0f83b365 | 17 | |
62d3c2d6 MV |
18 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ |
19 | ||
0f83b365 MV |
20 | /* |
21 | * Memory configurations | |
22 | */ | |
23 | #define CONFIG_NR_DRAM_BANKS 2 | |
24 | #define PHYS_SDRAM_1 CSD0_BASE_ADDR | |
97334c66 | 25 | #define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size) |
0f83b365 | 26 | #define PHYS_SDRAM_2 CSD1_BASE_ADDR |
97334c66 MV |
27 | #define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) |
28 | #define PHYS_SDRAM_SIZE (gd->ram_size) | |
0f83b365 MV |
29 | #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) |
30 | #define CONFIG_SYS_MEMTEST_START 0x70000000 | |
2f844e76 | 31 | #define CONFIG_SYS_MEMTEST_END 0x8ff00000 |
0f83b365 MV |
32 | |
33 | #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) | |
34 | #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) | |
35 | #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) | |
36 | ||
37 | #define CONFIG_SYS_INIT_SP_OFFSET \ | |
38 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
39 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
40 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
41 | ||
42 | #define CONFIG_SYS_TEXT_BASE 0x71000000 | |
43 | ||
44 | /* | |
45 | * U-Boot general configurations | |
46 | */ | |
47 | #define CONFIG_SYS_LONGHELP | |
0f83b365 MV |
48 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ |
49 | #define CONFIG_SYS_PBSIZE \ | |
50 | (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
51 | /* Print buffer size */ | |
52 | #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ | |
53 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
54 | /* Boot argument buffer size */ | |
0f83b365 MV |
55 | #define CONFIG_AUTO_COMPLETE /* Command auto complete */ |
56 | #define CONFIG_CMDLINE_EDITING /* Command history etc */ | |
0f83b365 MV |
57 | |
58 | /* | |
59 | * Serial Driver | |
60 | */ | |
61 | #define CONFIG_MXC_UART | |
62 | #define CONFIG_MXC_UART_BASE UART2_BASE | |
63 | #define CONFIG_CONS_INDEX 1 | |
0f83b365 MV |
64 | |
65 | /* | |
66 | * MMC Driver | |
67 | */ | |
68 | #ifdef CONFIG_CMD_MMC | |
0f83b365 MV |
69 | #define CONFIG_FSL_ESDHC |
70 | #define CONFIG_SYS_FSL_ESDHC_ADDR 0 | |
71 | #define CONFIG_SYS_FSL_ESDHC_NUM 1 | |
72 | #endif | |
73 | ||
74 | /* | |
75 | * NAND | |
76 | */ | |
77 | #define CONFIG_ENV_SIZE (16 * 1024) | |
78 | #ifdef CONFIG_CMD_NAND | |
79 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
80 | #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR_AXI | |
81 | #define CONFIG_NAND_MXC | |
82 | #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI | |
83 | #define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR | |
84 | #define CONFIG_SYS_NAND_LARGEPAGE | |
85 | #define CONFIG_MXC_NAND_HWECC | |
86 | #define CONFIG_SYS_NAND_USE_FLASH_BBT | |
87 | ||
88 | /* Environment is in NAND */ | |
0f83b365 MV |
89 | #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE |
90 | #define CONFIG_ENV_SECT_SIZE (128 * 1024) | |
fc23b530 MV |
91 | #define CONFIG_ENV_RANGE (4 * CONFIG_ENV_SECT_SIZE) |
92 | #define CONFIG_ENV_OFFSET (8 * CONFIG_ENV_SECT_SIZE) /* 1 MiB */ | |
0f83b365 MV |
93 | #define CONFIG_ENV_OFFSET_REDUND \ |
94 | (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) | |
95 | ||
0f83b365 MV |
96 | #define CONFIG_MTD_DEVICE |
97 | #define CONFIG_MTD_PARTITIONS | |
8331273c | 98 | #define MTDIDS_DEFAULT "nand0=mxc_nand" |
0f83b365 | 99 | #define MTDPARTS_DEFAULT \ |
8331273c | 100 | "mtdparts=mxc_nand:" \ |
fc23b530 MV |
101 | "1024k(u-boot)," \ |
102 | "512k(env1)," \ | |
103 | "512k(env2)," \ | |
104 | "14m(boot)," \ | |
105 | "240m(data)," \ | |
106 | "-@2048k(UBI)" | |
0f83b365 MV |
107 | #endif |
108 | ||
109 | /* | |
110 | * Ethernet on SOC (FEC) | |
111 | */ | |
112 | #ifdef CONFIG_CMD_NET | |
113 | #define CONFIG_FEC_MXC | |
114 | #define IMX_FEC_BASE FEC_BASE_ADDR | |
115 | #define CONFIG_FEC_MXC_PHYADDR 0x0 | |
116 | #define CONFIG_MII | |
117 | #define CONFIG_DISCOVER_PHY | |
118 | #define CONFIG_FEC_XCV_TYPE RMII | |
0f83b365 | 119 | #define CONFIG_PHY_MICREL |
85d8a5fc | 120 | #define CONFIG_ETHPRIME "FEC0" |
0f83b365 MV |
121 | #endif |
122 | ||
123 | /* | |
124 | * I2C | |
125 | */ | |
126 | #ifdef CONFIG_CMD_I2C | |
b089d039 | 127 | #define CONFIG_SYS_I2C |
128 | #define CONFIG_SYS_I2C_MXC | |
03544c66 AA |
129 | #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ |
130 | #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ | |
f8cb101e | 131 | #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ |
25fe0572 | 132 | #define CONFIG_SYS_RTC_BUS_NUM 1 /* I2C2 */ |
0f83b365 MV |
133 | #endif |
134 | ||
135 | /* | |
136 | * RTC | |
137 | */ | |
138 | #ifdef CONFIG_CMD_DATE | |
139 | #define CONFIG_RTC_M41T62 | |
140 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
141 | #define CONFIG_SYS_M41T11_BASE_YEAR 2000 | |
142 | #endif | |
143 | ||
144 | /* | |
145 | * USB | |
146 | */ | |
147 | #ifdef CONFIG_CMD_USB | |
0f83b365 | 148 | #define CONFIG_USB_EHCI_MX5 |
0f83b365 MV |
149 | #define CONFIG_USB_HOST_ETHER |
150 | #define CONFIG_USB_ETHER_ASIX | |
a743415f | 151 | #define CONFIG_USB_ETHER_MCS7830 |
0f83b365 MV |
152 | #define CONFIG_USB_ETHER_SMSC95XX |
153 | #define CONFIG_MXC_USB_PORT 1 | |
154 | #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) | |
155 | #define CONFIG_MXC_USB_FLAGS 0 | |
156 | #endif | |
157 | ||
158 | /* | |
159 | * SATA | |
160 | */ | |
161 | #ifdef CONFIG_CMD_SATA | |
162 | #define CONFIG_DWC_AHSATA | |
163 | #define CONFIG_SYS_SATA_MAX_DEVICE 1 | |
164 | #define CONFIG_DWC_AHSATA_PORT_ID 0 | |
165 | #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR | |
166 | #define CONFIG_LBA48 | |
167 | #define CONFIG_LIBATA | |
168 | #endif | |
169 | ||
502a710f MV |
170 | /* |
171 | * LCD | |
172 | */ | |
173 | #ifdef CONFIG_VIDEO | |
174 | #define CONFIG_VIDEO_IPUV3 | |
502a710f | 175 | #define CONFIG_VIDEO_BMP_RLE8 |
62d3c2d6 | 176 | #define CONFIG_VIDEO_BMP_GZIP |
502a710f | 177 | #define CONFIG_SPLASH_SCREEN |
62d3c2d6 MV |
178 | #define CONFIG_SPLASHIMAGE_GUARD |
179 | #define CONFIG_SPLASH_SCREEN_ALIGN | |
502a710f MV |
180 | #define CONFIG_BMP_16BPP |
181 | #define CONFIG_VIDEO_LOGO | |
62d3c2d6 MV |
182 | #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) |
183 | #define CONFIG_IPUV3_CLK 200000000 | |
502a710f MV |
184 | #endif |
185 | ||
0f83b365 MV |
186 | /* |
187 | * Boot Linux | |
188 | */ | |
189 | #define CONFIG_CMDLINE_TAG | |
190 | #define CONFIG_INITRD_TAG | |
191 | #define CONFIG_REVISION_TAG | |
192 | #define CONFIG_SETUP_MEMORY_TAGS | |
85d8a5fc | 193 | #define CONFIG_BOOTFILE "fitImage" |
0f83b365 MV |
194 | #define CONFIG_BOOTARGS "console=ttymxc1,115200" |
195 | #define CONFIG_LOADADDR 0x70800000 | |
85d8a5fc | 196 | #define CONFIG_BOOTCOMMAND "run mmc_mmc" |
0f83b365 | 197 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR |
0f83b365 MV |
198 | |
199 | /* | |
200 | * NAND SPL | |
201 | */ | |
0f83b365 MV |
202 | #define CONFIG_SPL_FRAMEWORK |
203 | #define CONFIG_SPL_TARGET "u-boot-with-nand-spl.imx" | |
0f83b365 MV |
204 | #define CONFIG_SPL_TEXT_BASE 0x70008000 |
205 | #define CONFIG_SPL_PAD_TO 0x8000 | |
206 | #define CONFIG_SPL_STACK 0x70004000 | |
0f83b365 MV |
207 | |
208 | #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO | |
209 | #define CONFIG_SYS_NAND_PAGE_SIZE 2048 | |
210 | #define CONFIG_SYS_NAND_OOBSIZE 64 | |
211 | #define CONFIG_SYS_NAND_PAGE_COUNT 64 | |
212 | #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) | |
213 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 | |
214 | ||
85d8a5fc LR |
215 | /* |
216 | * Extra Environments | |
217 | */ | |
218 | #define CONFIG_PREBOOT "run try_bootscript" | |
219 | #define CONFIG_HOSTNAME m53evk | |
220 | ||
221 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
222 | "consdev=ttymxc1\0" \ | |
223 | "baudrate=115200\0" \ | |
224 | "bootscript=boot.scr\0" \ | |
225 | "bootdev=/dev/mmcblk0p1\0" \ | |
226 | "rootdev=/dev/mmcblk0p2\0" \ | |
227 | "netdev=eth0\0" \ | |
228 | "rootpath=/opt/eldk-5.5/armv7a-hf/rootfs-qte-sdk\0" \ | |
229 | "kernel_addr_r=0x72000000\0" \ | |
230 | "addcons=" \ | |
231 | "setenv bootargs ${bootargs} " \ | |
232 | "console=${consdev},${baudrate}\0" \ | |
233 | "addip=" \ | |
234 | "setenv bootargs ${bootargs} " \ | |
235 | "ip=${ipaddr}:${serverip}:${gatewayip}:" \ | |
236 | "${netmask}:${hostname}:${netdev}:off\0" \ | |
237 | "addmisc=" \ | |
238 | "setenv bootargs ${bootargs} ${miscargs}\0" \ | |
239 | "adddfltmtd=" \ | |
240 | "if test \"x${mtdparts}\" == \"x\" ; then " \ | |
241 | "mtdparts default ; " \ | |
242 | "fi\0" \ | |
243 | "addmtd=" \ | |
244 | "run adddfltmtd ; " \ | |
245 | "setenv bootargs ${bootargs} ${mtdparts}\0" \ | |
246 | "addargs=run addcons addmtd addmisc\0" \ | |
247 | "mmcload=" \ | |
248 | "mmc rescan ; " \ | |
febae49a | 249 | "load mmc 0:1 ${kernel_addr_r} ${bootfile}\0" \ |
85d8a5fc LR |
250 | "ubiload=" \ |
251 | "ubi part UBI ; ubifsmount ubi0:rootfs ; " \ | |
252 | "ubifsload ${kernel_addr_r} /boot/${bootfile}\0" \ | |
253 | "netload=" \ | |
254 | "tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \ | |
255 | "miscargs=nohlt panic=1\0" \ | |
256 | "mmcargs=setenv bootargs root=${rootdev} rw rootwait\0" \ | |
257 | "ubiargs=" \ | |
258 | "setenv bootargs ubi.mtd=5 " \ | |
259 | "root=ubi0:rootfs rootfstype=ubifs\0" \ | |
260 | "nfsargs=" \ | |
261 | "setenv bootargs root=/dev/nfs rw " \ | |
262 | "nfsroot=${serverip}:${rootpath},v3,tcp\0" \ | |
263 | "mmc_mmc=" \ | |
264 | "run mmcload mmcargs addargs ; " \ | |
265 | "bootm ${kernel_addr_r}\0" \ | |
266 | "mmc_ubi=" \ | |
267 | "run mmcload ubiargs addargs ; " \ | |
268 | "bootm ${kernel_addr_r}\0" \ | |
269 | "mmc_nfs=" \ | |
270 | "run mmcload nfsargs addip addargs ; " \ | |
271 | "bootm ${kernel_addr_r}\0" \ | |
272 | "ubi_mmc=" \ | |
273 | "run ubiload mmcargs addargs ; " \ | |
274 | "bootm ${kernel_addr_r}\0" \ | |
275 | "ubi_ubi=" \ | |
276 | "run ubiload ubiargs addargs ; " \ | |
277 | "bootm ${kernel_addr_r}\0" \ | |
278 | "ubi_nfs=" \ | |
279 | "run ubiload nfsargs addip addargs ; " \ | |
280 | "bootm ${kernel_addr_r}\0" \ | |
281 | "net_mmc=" \ | |
282 | "run netload mmcargs addargs ; " \ | |
283 | "bootm ${kernel_addr_r}\0" \ | |
284 | "net_ubi=" \ | |
285 | "run netload ubiargs addargs ; " \ | |
286 | "bootm ${kernel_addr_r}\0" \ | |
287 | "net_nfs=" \ | |
288 | "run netload nfsargs addip addargs ; " \ | |
289 | "bootm ${kernel_addr_r}\0" \ | |
290 | "try_bootscript=" \ | |
291 | "mmc rescan;" \ | |
14b256e5 | 292 | "if test -e mmc 0:1 ${bootscript} ; then " \ |
febae49a | 293 | "if load mmc 0:1 ${kernel_addr_r} ${bootscript};" \ |
252499e6 MV |
294 | "then ; " \ |
295 | "echo Running bootscript... ; " \ | |
296 | "source ${kernel_addr_r} ; " \ | |
14b256e5 | 297 | "fi ; " \ |
85d8a5fc LR |
298 | "fi\0" |
299 | ||
0f83b365 | 300 | #endif /* __M53EVK_CONFIG_H__ */ |