[people/ms/u-boot.git] / include / configs / manroland / mpc5200-common.h

/*
 * (C) Copyright 2009
 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __MANROLAND_MPC52XX__COMMON_H
#define __MANROLAND_MPC52XX__COMMON_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU		*/
#define CONFIG_MPC5200		1	/* (more precisely an MPC5200 CPU)	*/

#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz	*/

#define CONFIG_HIGH_BATS	1	/* High BATs supported 			*/

/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1	*/
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200,\
					 230400 }

#if (CONFIG_SYS_TEXT_BASE == 0xFFF00000) /* Boot low */
#   define CONFIG_SYS_LOWBOOT		1
#endif

/*
 * IPB Bus clocking configuration.
 */
#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */

/*
 * I2C configuration
 */
#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #1 or #2 */

#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
#define CONFIG_SYS_I2C_SLAVE		0x7F

/*
 * EEPROM configuration
 */
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x58
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10

/*
 * RTC configuration
 */
#define CONFIG_RTC_PCF8563
#define CONFIG_SYS_I2C_RTC_ADDR		0x51

/* I2C SYSMON (LM75) */
#define CONFIG_DTT_LM81			1	/* ON Semi's LM75	*/
#define CONFIG_DTT_SENSORS		{0}	/* Sensor addresses	*/
#define CONFIG_SYS_DTT_MAX_TEMP		70
#define CONFIG_SYS_DTT_LOW_TEMP		-30
#define CONFIG_SYS_DTT_HYSTERESIS		3

/*
 * Flash configuration
 */
#define CONFIG_SYS_FLASH_BASE		0xFF800000

#define CONFIG_SYS_FLASH_SIZE		0x00800000 /* 8 MByte */

#define CONFIG_ENV_ADDR		(CONFIG_SYS_TEXT_BASE+0x40000) /* second sector */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks
					   (= chip selects) */
#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout [ms]*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout [ms]*/

#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_CFI_AMD_RESET

/*
 * Environment settings
 */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_SIZE		0x4000
#define CONFIG_ENV_OFFSET_REDUND   (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND     (CONFIG_ENV_SIZE)

/*
 * Memory map
 */
#define CONFIG_SYS_MBAR		0xF0000000
#define CONFIG_SYS_DEFAULT_MBAR	0x80000000

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE -\
					 GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_SRAM_BASE	0x80100000	/* CS 1 */
#define CONFIG_SYS_DISPLAY_BASE	0x80600000	/* CS 3 */

/* Settings for XLB = 132 MHz */
#define SDRAM_DDR	 1
#define SDRAM_MODE      0x018D0000
#define SDRAM_EMODE     0x40090000
#define SDRAM_CONTROL   0x714f0f00
#define SDRAM_CONFIG1   0x73722930
#define SDRAM_CONFIG2   0x47770000
#define SDRAM_TAPDELAY  0x10000000

/* Use ON-Chip SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
#ifdef CONFIG_POST
/* preserve space for the post_word at end of on-chip SRAM */
#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_POST_SIZE
#else
#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
#endif

#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#   define CONFIG_SYS_RAMBOOT		1
#endif

#define CONFIG_SYS_MONITOR_LEN		(192 << 10)
#define CONFIG_SYS_MALLOC_LEN		(512 << 10)
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)

/*
 * Ethernet configuration
 */
#define CONFIG_MPC5xxx_FEC	1
#define CONFIG_MPC5xxx_FEC_MII100
#define CONFIG_PHY_ADDR		0x00
#define CONFIG_MII		1

/*use  Hardware WDT */
#define CONFIG_HW_WATCHDOG

#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs		*/
#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value*/
#endif

/*
 * Various low-level settings
 */
#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL		HID0_ICE

#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE

/* 8Mbit SRAM @0x80100000 */
#define CONFIG_SYS_CS1_START		CONFIG_SYS_SRAM_BASE

#define CONFIG_SYS_CS_BURST		0x00000000
#define CONFIG_SYS_CS_DEADCYCLE	0x33333333

/*-----------------------------------------------------------------------
 * IDE/ATA stuff Supports IDE harddisk
 *-----------------------------------------------------------------------
 */

#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/

#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus	*/

#define CONFIG_IDE_PREINIT	1

#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000

#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA

/* Offset for data I/O			*/
#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)

/* Offset for normal register accesses	*/
#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)

/* Offset for alternate registers	*/
#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)

/* Interval between registers	*/
#define CONFIG_SYS_ATA_STRIDE          4

#define CONFIG_ATAPI            1

#define OF_CPU			"PowerPC,5200@0"
#define OF_SOC			"soc5200@f0000000"
#define OF_TBCLK		(bd->bi_busfreq / 4)
#define OF_STDOUT_PATH		"/soc5200@f0000000/serial@2000"
#define CONFIG_OF_IDE_FIXUP

#endif /* __MANROLAND_MPC52XX__COMMON_H */
Commit	Line	Data
7f625fc6 HS	1	/*
	2	* (C) Copyright 2009
	3	* Heiko Schocher, DENX Software Engineering, hs@denx.de.
	4	*
3765b3e7	5	* SPDX-License-Identifier: GPL-2.0+
7f625fc6 HS	6	*/
	7
	8	#ifndef __MANROLAND_MPC52XX__COMMON_H
	9	#define __MANROLAND_MPC52XX__COMMON_H
	10
	11	/*
	12	* High Level Configuration Options
	13	* (easy to change)
	14	*/
	15	#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
	16	#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
	17
	18	#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
	19
	20	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
	21
	22	/*
	23	* Serial console configuration
	24	*/
	25	#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
	26	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200,\
	27	230400 }
	28
14d0a02a	29	#if (CONFIG_SYS_TEXT_BASE == 0xFFF00000) /* Boot low */
7f625fc6 HS	30	# define CONFIG_SYS_LOWBOOT 1
	31	#endif
	32
	33	/*
	34	* IPB Bus clocking configuration.
	35	*/
	36	#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
	37
	38	/*
	39	* I2C configuration
	40	*/
	41	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
	42	#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
	43
	44	#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
	45	#define CONFIG_SYS_I2C_SLAVE 0x7F
	46
	47	/*
	48	* EEPROM configuration
	49	*/
	50	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58
	51	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	52	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
	53	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
	54
	55	/*
	56	* RTC configuration
	57	*/
	58	#define CONFIG_RTC_PCF8563
	59	#define CONFIG_SYS_I2C_RTC_ADDR 0x51
	60
	61	/* I2C SYSMON (LM75) */
	62	#define CONFIG_DTT_LM81 1 /* ON Semi's LM75 */
	63	#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
	64	#define CONFIG_SYS_DTT_MAX_TEMP 70
	65	#define CONFIG_SYS_DTT_LOW_TEMP -30
	66	#define CONFIG_SYS_DTT_HYSTERESIS 3
	67
	68	/*
	69	* Flash configuration
	70	*/
	71	#define CONFIG_SYS_FLASH_BASE 0xFF800000
	72
	73	#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */
	74
14d0a02a	75	#define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE+0x40000) /* second sector */
7f625fc6 HS	76	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
	77	(= chip selects) */
	78	#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout [ms]*/
	79	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout [ms]*/
	80
	81	#define CONFIG_FLASH_CFI_DRIVER
	82	#define CONFIG_SYS_FLASH_CFI
	83	#define CONFIG_SYS_FLASH_EMPTY_INFO
	84	#define CONFIG_SYS_FLASH_CFI_AMD_RESET
	85
	86	/*
	87	* Environment settings
	88	*/
	89	#define CONFIG_ENV_IS_IN_FLASH 1
	90	#define CONFIG_ENV_SIZE 0x4000
	91	#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
	92	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
	93
	94	/*
	95	* Memory map
	96	*/
	97	#define CONFIG_SYS_MBAR 0xF0000000
	98	#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
	99
553f0982	100	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE -\
25ddd1fb	101	GENERATED_GBL_DATA_SIZE)
7f625fc6 HS	102	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
	103
	104	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	105	#define CONFIG_SYS_SRAM_BASE 0x80100000 /* CS 1 */
	106	#define CONFIG_SYS_DISPLAY_BASE 0x80600000 /* CS 3 */
	107
	108	/* Settings for XLB = 132 MHz */
	109	#define SDRAM_DDR 1
	110	#define SDRAM_MODE 0x018D0000
	111	#define SDRAM_EMODE 0x40090000
	112	#define SDRAM_CONTROL 0x714f0f00
	113	#define SDRAM_CONFIG1 0x73722930
	114	#define SDRAM_CONFIG2 0x47770000
	115	#define SDRAM_TAPDELAY 0x10000000
	116
	117	/* Use ON-Chip SRAM until RAM will be available */
	118	#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
	119	#ifdef CONFIG_POST
	120	/* preserve space for the post_word at end of on-chip SRAM */
553f0982	121	#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
7f625fc6	122	#else
553f0982	123	#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
7f625fc6 HS	124	#endif
7f625fc6 HS	125
14d0a02a	126	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
7f625fc6 HS	127	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
	128	# define CONFIG_SYS_RAMBOOT 1
	129	#endif
	130
	131	#define CONFIG_SYS_MONITOR_LEN (192 << 10)
	132	#define CONFIG_SYS_MALLOC_LEN (512 << 10)
	133	#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
	134
	135	/*
	136	* Ethernet configuration
	137	*/
	138	#define CONFIG_MPC5xxx_FEC 1
	139	#define CONFIG_MPC5xxx_FEC_MII100
	140	#define CONFIG_PHY_ADDR 0x00
	141	#define CONFIG_MII 1
	142
	143	/use Hardware WDT /
	144	#define CONFIG_HW_WATCHDOG
	145
7f625fc6 HS	146	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
	147	#if defined(CONFIG_CMD_KGDB)
	148	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value*/
	149	#endif
	150
	151	/*
	152	* Various low-level settings
	153	*/
7f625fc6 HS	154	#define CONFIG_SYS_HID0_INIT HID0_ICE \| HID0_ICFI
7f625fc6 HS	155	#define CONFIG_SYS_HID0_FINAL HID0_ICE
7f625fc6 HS	156
	157	#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
	158	#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
	159	#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
	160	#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
	161
	162	/* 8Mbit SRAM @0x80100000 */
	163	#define CONFIG_SYS_CS1_START CONFIG_SYS_SRAM_BASE
	164
	165	#define CONFIG_SYS_CS_BURST 0x00000000
	166	#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
	167
	168	/*-----------------------------------------------------------------------
	169	* IDE/ATA stuff Supports IDE harddisk
	170	*-----------------------------------------------------------------------
	171	*/
	172
	173	#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
	174
	175	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
	176	#undef CONFIG_IDE_LED /* LED for ide not supported */
	177
	178	#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
	179
	180	#define CONFIG_IDE_PREINIT 1
	181
	182	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
	183
	184	#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
	185
	186	/* Offset for data I/O */
	187	#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
	188
	189	/* Offset for normal register accesses */
	190	#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
	191
	192	/* Offset for alternate registers */
	193	#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
	194
	195	/* Interval between registers */
	196	#define CONFIG_SYS_ATA_STRIDE 4
	197
	198	#define CONFIG_ATAPI 1
	199
	200	#define OF_CPU "PowerPC,5200@0"
	201	#define OF_SOC "soc5200@f0000000"
	202	#define OF_TBCLK (bd->bi_busfreq / 4)
	203	#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
3887c3fb	204	#define CONFIG_OF_IDE_FIXUP
7f625fc6 HS	205
7f625fc6 HS	206	#endif /* __MANROLAND_MPC52XX__COMMON_H */