[people/ms/u-boot.git] / include / configs / mcc200.h

/*
 * (C) Copyright 2006
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC5200
#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU		*/
#define CONFIG_MCC200		1	/* ... on MCC200 board			*/

#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33MHz		*/

#define CONFIG_MISC_INIT_R

#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM		0x02	/* Software reboot			*/

/*
 * Serial console configuration
 *
 *  To select console on the one of 8 external UARTs,
 * define CONFIG_QUART_CONSOLE as 1, 2, 3, or 4 for the first Quad UART,
 * or as 5, 6, 7, or 8 for the second Quad UART.
 * COM11, COM12, COM13, COM14 are located on the second Quad UART.
 *
 *  CONFIG_PSC_CONSOLE must be undefined in this case.
 */
#if !defined(CONFIG_PRS200)
/* MCC200 configuration: */
#ifdef CONFIG_CONSOLE_COM12
#define CONFIG_QUART_CONSOLE	6	/* console is on UARTF of QUART2	*/
#else
#define CONFIG_QUART_CONSOLE	8	/* console is on UARTH of QUART2	*/
#endif
#else
/* PRS200 configuration: */
#undef CONFIG_QUART_CONSOLE
#endif /* CONFIG_PRS200 */
/*
 *  To select console on PSC1, define CONFIG_PSC_CONSOLE as 1
 * and undefine CONFIG_QUART_CONSOLE.
 */
#if !defined(CONFIG_PRS200)
/* MCC200 configuration: */
#define CONFIG_SERIAL_MULTI	1
#define CONFIG_PSC_CONSOLE	1	/* PSC1 may be COM */
#define CONFIG_PSC_CONSOLE2	2	/* PSC2 is PSoC */
#else
/* PRS200 configuration: */
#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1		*/
#endif
#if defined(CONFIG_QUART_CONSOLE) && defined(CONFIG_PSC_CONSOLE) && \
	!defined(CONFIG_SERIAL_MULTI)
#error "Select only one console device!"
#endif
#define CONFIG_BAUDRATE		115200
#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

#define CONFIG_MII		1

#define CONFIG_DOS_PARTITION

/* USB */
#define CONFIG_USB_OHCI
#define CONFIG_USB_STORAGE
/* automatic software updates (see board/mcc200/auto_update.c) */
#define CONFIG_AUTO_UPDATE 1


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_BEDBUG
#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
#define CONFIG_CMD_USB


/*
 * Autobooting
 */
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */

#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define XMK_STR(x)		#x
#define MK_STR(x)		XMK_STR(x)

#ifdef CONFIG_PRS200
# define CFG__BOARDNAME		"prs200"
# define CFG__LINUX_CONSOLE	"ttyS0"
#else
# define CFG__BOARDNAME		"mcc200"
# define CFG__LINUX_CONSOLE	"ttyEU7"
#endif

#define CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"hostname=" CFG__BOARDNAME "\0"					\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addcons=setenv bootargs ${bootargs} "				\
		"console=${console},${baudrate}\0"			\
	"flash_nfs=run nfsargs addip addcons;"				\
		"bootm ${kernel_addr}\0"				\
	"flash_self=run ramargs addip addcons;"				\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"net_nfs=tftp 200000 ${bootfile};"				\
		"run nfsargs addip addcons;bootm\0"			\
	"console=" CFG__LINUX_CONSOLE "\0"				\
	"rootpath=/opt/eldk/ppc_6xx\0"					\
	"bootfile=/tftpboot/" CFG__BOARDNAME "/uImage\0"		\
	"load=tftp 200000 /tftpboot/" CFG__BOARDNAME "/u-boot.bin\0"	\
	"text_base=" MK_STR(TEXT_BASE) "\0"				\
	"update=protect off ${text_base} +${filesize};"			\
		"era ${text_base} +${filesize};"			\
		"cp.b 200000 ${text_base} ${filesize}\0"		\
	"unlock=yes\0"							\
	""
#undef MK_STR
#undef XMK_STR

#define CONFIG_BOOTCOMMAND	"run flash_self"

#define CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
#define CFG_PROMPT_HUSH_PS2	"> "

/*
 * IPB Bus clocking configuration.
 */
#define CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */

/*
 * I2C configuration
 */
#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
#define CFG_I2C_MODULE		2	/* Select I2C module #1 or #2 */

#define CFG_I2C_SPEED		100000 /* 100 kHz */
#define CFG_I2C_SLAVE		0x7F

/*
 * Flash configuration (8,16 or 32 MB)
 * TEXT base always at 0xFFF00000
 * ENV_ADDR always at  0xFFF40000
 * FLASH_BASE at 0xFC000000 for 64 MB (only 32MB are supported, not enough addr lines!!!)
 *		 0xFE000000 for 32 MB
 *		 0xFF000000 for 16 MB
 *		 0xFF800000 for  8 MB
 */
#define CFG_FLASH_BASE		0xfc000000
#define CFG_FLASH_SIZE		0x04000000

#define CFG_FLASH_CFI				/* The flash is CFI compatible	*/
#define CFG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/

#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }

#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/

#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
#define CFG_FLASH_PROTECTION	1	/* hardware flash protection		*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
#define CFG_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash	*/

#define CFG_ENV_IS_IN_FLASH	1	/* use FLASH for environment vars	*/

#define CFG_ENV_SECT_SIZE	0x40000	/* size of one complete sector	*/
#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
#define	CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/

/* Address and size of Redundant Environment Sector	*/
#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)

#define CONFIG_ENV_OVERWRITE	1	/* allow modification of vendor params */

#if TEXT_BASE == CFG_FLASH_BASE
#define CFG_LOWBOOT	1
#endif

/*
 * Memory map
 */
#define CFG_MBAR		0xf0000000
#define CFG_SDRAM_BASE		0x00000000
#define CFG_DEFAULT_MBAR	0x80000000

/* Use SRAM until RAM will be available */
#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */


#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

#define CFG_MONITOR_BASE	TEXT_BASE
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#   define CFG_RAMBOOT		1
#endif

#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#define CFG_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*
 * Ethernet configuration
 */
#define CONFIG_MPC5xxx_FEC	1
/*
 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
 */
/* #define CONFIG_FEC_10MBIT 1 */
#define CONFIG_PHY_ADDR		1

/*
 * LCD Splash Screen
 */
#if !defined(CONFIG_PRS200)
#define CONFIG_LCD		1
#define CONFIG_PROGRESSBAR 1
#endif

#if defined(CONFIG_LCD)
#define CONFIG_SPLASH_SCREEN	1
#define CFG_CONSOLE_IS_IN_ENV	1
#define LCD_BPP			LCD_MONOCHROME
#endif

/*
 * GPIO configuration
 */
/* 0x10000004 = 32MB SDRAM */
/* 0x90000004 = 64MB SDRAM */
#if defined(CONFIG_LCD)
/* set PSC2 in UART mode */
#define CFG_GPS_PORT_CONFIG	0x00000044
#else
#define CFG_GPS_PORT_CONFIG	0x00000004
#endif

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE		1024	/* Console I/O Buffer Size	*/
#else
#define CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size	*/
#define CFG_MAXARGS		16		/* max number of command args	*/
#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x00100000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/

#define CFG_LOAD_ADDR		0x100000	/* default load address */

#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */

#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs			*/
#if defined(CONFIG_CMD_KGDB)
#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
#endif

/*
 * Various low-level settings
 */
#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
#define CFG_HID0_FINAL		HID0_ICE

#define CFG_BOOTCS_START	CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
#define CFG_BOOTCS_CFG		0x0004fb00
#define CFG_CS0_START		CFG_FLASH_BASE
#define CFG_CS0_SIZE		CFG_FLASH_SIZE

/* Quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
#define CFG_CS2_START		0x80000000
#define CFG_CS2_SIZE		0x00001000
#define CFG_CS2_CFG		0x1d300

/* Second Quad UART @0x80010000 */
#define CFG_CS1_START		0x80010000
#define CFG_CS1_SIZE		0x00001000
#define CFG_CS1_CFG		0x1d300

/*
 *  Select one of quarts as a default
 * console. If undefined - PSC console
 * wil be default
 */
#define CFG_CS_BURST		0x00000000
#define CFG_CS_DEADCYCLE	0x33333333

#define CFG_RESET_ADDRESS	0xff000000

/*
 * QUART Expanders support
 */
#if defined(CONFIG_QUART_CONSOLE)
/*
 * We'll use NS16550 chip routines,
 */
#define CFG_NS16550		1
#define CFG_NS16550_SERIAL	1
#define CONFIG_CONS_INDEX	1
/*
 *  To achieve necessary offset on SC16C554
 * A0-A2 (register select) pins with NS16550
 * functions (in struct NS16550), REG_SIZE
 * should be 4, because A0-A2 pins are connected
 * to DA2-DA4 address bus lines.
 */
#define CFG_NS16550_REG_SIZE	4
/*
 * LocalPlus Bus already inited in cpu_init_f(),
 * so can work with QUART's chip selects.
 * One of four SC16C554 UARTs is selected with
 * A3-A4 (DA5-DA6) lines.
 */
#if (CONFIG_QUART_CONSOLE > 0) && (CONFIG_QUART_CONSOLE < 5) && !defined(CONFIG_PRS200)
#define CFG_NS16550_COM1	(CFG_CS2_START | (CONFIG_QUART_CONSOLE - 1)<<5)
#elif (CONFIG_QUART_CONSOLE > 4) && (CONFIG_QUART_CONSOLE < 9)
#define CFG_NS16550_COM1	(CFG_CS1_START | (CONFIG_QUART_CONSOLE - 5)<<5)
#elif
#error "Wrong QUART expander number."
#endif

/*
 * SC16C554 chip's external crystal oscillator frequency
 * is 7.3728 MHz
 */
#define CFG_NS16550_CLK		7372800
#endif /* CONFIG_QUART_CONSOLE */
/*-----------------------------------------------------------------------
 * USB stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_USB_CLOCK	0x0001BBBB
#define CONFIG_USB_CONFIG	0x00005000

#endif /* __CONFIG_H */
Commit	Line	Data
86ea5f93 WD	1	/*
	2	* (C) Copyright 2006
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#ifndef __CONFIG_H
	25	#define __CONFIG_H
	26
	27	/*
	28	* High Level Configuration Options
	29	* (easy to change)
	30	*/
	31
	32	#define CONFIG_MPC5200
	33	#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
	34	#define CONFIG_MCC200 1 /* ... on MCC200 board */
	35
	36	#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
	37
	38	#define CONFIG_MISC_INIT_R
	39
360b4103 WD	40	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
360b4103 WD	41	#define BOOTFLAG_WARM 0x02 /* Software reboot */
86ea5f93	42
86ea5f93 WD	43	/*
86ea5f93 WD	44	* Serial console configuration
87791f3b WD	45	*
	46	* To select console on the one of 8 external UARTs,
	47	* define CONFIG_QUART_CONSOLE as 1, 2, 3, or 4 for the first Quad UART,
	48	* or as 5, 6, 7, or 8 for the second Quad UART.
463764c8	49	* COM11, COM12, COM13, COM14 are located on the second Quad UART.
87791f3b WD	50	*
	51	* CONFIG_PSC_CONSOLE must be undefined in this case.
	52	*/
ed1cf845 WD	53	#if !defined(CONFIG_PRS200)
ed1cf845 WD	54	/* MCC200 configuration: */
463764c8 WD	55	#ifdef CONFIG_CONSOLE_COM12
	56	#define CONFIG_QUART_CONSOLE 6 /* console is on UARTF of QUART2 */
	57	#else
	58	#define CONFIG_QUART_CONSOLE 8 /* console is on UARTH of QUART2 */
	59	#endif
ed1cf845 WD	60	#else
	61	/* PRS200 configuration: */
	62	#undef CONFIG_QUART_CONSOLE
	63	#endif /* CONFIG_PRS200 */
87791f3b WD	64	/*
	65	* To select console on PSC1, define CONFIG_PSC_CONSOLE as 1
	66	* and undefine CONFIG_QUART_CONSOLE.
86ea5f93	67	*/
ed1cf845 WD	68	#if !defined(CONFIG_PRS200)
ed1cf845 WD	69	/* MCC200 configuration: */
0fd30252 WD	70	#define CONFIG_SERIAL_MULTI 1
	71	#define CONFIG_PSC_CONSOLE 1 /* PSC1 may be COM */
	72	#define CONFIG_PSC_CONSOLE2 2 /* PSC2 is PSoC */
ed1cf845 WD	73	#else
	74	/* PRS200 configuration: */
	75	#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
	76	#endif
0fd30252 WD	77	#if defined(CONFIG_QUART_CONSOLE) && defined(CONFIG_PSC_CONSOLE) && \
0fd30252 WD	78	!defined(CONFIG_SERIAL_MULTI)
87791f3b WD	79	#error "Select only one console device!"
87791f3b WD	80	#endif
86ea5f93 WD	81	#define CONFIG_BAUDRATE 115200
	82	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
	83
86ea5f93	84	#define CONFIG_MII 1
86ea5f93	85
86ea5f93 WD	86	#define CONFIG_DOS_PARTITION
	87
	88	/* USB */
86ea5f93	89	#define CONFIG_USB_OHCI
86ea5f93	90	#define CONFIG_USB_STORAGE
cdb97a66 AS	91	/* automatic software updates (see board/mcc200/auto_update.c) */
cdb97a66 AS	92	#define CONFIG_AUTO_UPDATE 1
86ea5f93	93
5dc11a51	94
86ea5f93	95	/*
5dc11a51	96	* Command line configuration.
86ea5f93	97	*/
5dc11a51 JL	98	#include <config_cmd_default.h>
	99
	100	#define CONFIG_CMD_BEDBUG
	101	#define CONFIG_CMD_FAT
	102	#define CONFIG_CMD_I2C
	103	#define CONFIG_CMD_USB
86ea5f93	104
86ea5f93 WD	105
	106	/*
	107	* Autobooting
	108	*/
	109	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	110
	111	#define CONFIG_PREBOOT "echo;" \
	112	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	113	"echo"
	114
	115	#undef CONFIG_BOOTARGS
	116
3b0ff842 WD	117	#define XMK_STR(x) #x
3b0ff842 WD	118	#define MK_STR(x) XMK_STR(x)
ed1cf845 WD	119
ed1cf845 WD	120	#ifdef CONFIG_PRS200
3b0ff842 WD	121	# define CFG__BOARDNAME "prs200"
3b0ff842 WD	122	# define CFG__LINUX_CONSOLE "ttyS0"
ed1cf845	123	#else
3b0ff842 WD	124	# define CFG__BOARDNAME "mcc200"
3b0ff842 WD	125	# define CFG__LINUX_CONSOLE "ttyEU7"
ed1cf845 WD	126	#endif
	127
	128	#define CONFIG_EXTRA_ENV_SETTINGS \
86ea5f93	129	"netdev=eth0\0" \
ed1cf845	130	"hostname=" CFG__BOARDNAME "\0" \
86ea5f93 WD	131	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	132	"nfsroot=${serverip}:${rootpath}\0" \
	133	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	134	"addip=setenv bootargs ${bootargs} " \
	135	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	136	":${hostname}:${netdev}:off panic=1\0" \
113f64e0	137	"addcons=setenv bootargs ${bootargs} " \
ed1cf845 WD	138	"console=${console},${baudrate}\0" \
ed1cf845 WD	139	"flash_nfs=run nfsargs addip addcons;" \
86ea5f93	140	"bootm ${kernel_addr}\0" \
ed1cf845	141	"flash_self=run ramargs addip addcons;" \
86ea5f93	142	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
ed1cf845 WD	143	"net_nfs=tftp 200000 ${bootfile};" \
ed1cf845 WD	144	"run nfsargs addip addcons;bootm\0" \
21a9cc02	145	"console=" CFG__LINUX_CONSOLE "\0" \
82f2e33a	146	"rootpath=/opt/eldk/ppc_6xx\0" \
ed1cf845 WD	147	"bootfile=/tftpboot/" CFG__BOARDNAME "/uImage\0" \
	148	"load=tftp 200000 /tftpboot/" CFG__BOARDNAME "/u-boot.bin\0" \
	149	"text_base=" MK_STR(TEXT_BASE) "\0" \
	150	"update=protect off ${text_base} +${filesize};" \
	151	"era ${text_base} +${filesize};" \
	152	"cp.b 200000 ${text_base} ${filesize}\0" \
58ad4978	153	"unlock=yes\0" \
86ea5f93	154	""
ed1cf845 WD	155	#undef MK_STR
ed1cf845 WD	156	#undef XMK_STR
86ea5f93 WD	157
	158	#define CONFIG_BOOTCOMMAND "run flash_self"
	159
82f2e33a WD	160	#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
	161	#define CFG_PROMPT_HUSH_PS2 "> "
	162
86ea5f93 WD	163	/*
	164	* IPB Bus clocking configuration.
	165	*/
c99512d6	166	#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
86ea5f93	167
86ea5f93 WD	168	/*
	169	* I2C configuration
	170	*/
	171	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
cdb97a66	172	#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
86ea5f93 WD	173
	174	#define CFG_I2C_SPEED 100000 /* 100 kHz */
	175	#define CFG_I2C_SLAVE 0x7F
	176
86ea5f93 WD	177	/*
	178	* Flash configuration (8,16 or 32 MB)
	179	* TEXT base always at 0xFFF00000
	180	* ENV_ADDR always at 0xFFF40000
58ad4978	181	* FLASH_BASE at 0xFC000000 for 64 MB (only 32MB are supported, not enough addr lines!!!)
360b4103 WD	182	* 0xFE000000 for 32 MB
	183	* 0xFF000000 for 16 MB
	184	* 0xFF800000 for 8 MB
86ea5f93	185	*/
58ad4978 SR	186	#define CFG_FLASH_BASE 0xfc000000
58ad4978 SR	187	#define CFG_FLASH_SIZE 0x04000000
86ea5f93	188
58ad4978 SR	189	#define CFG_FLASH_CFI /* The flash is CFI compatible */
58ad4978 SR	190	#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
86ea5f93	191
58ad4978	192	#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
86ea5f93	193
58ad4978 SR	194	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
58ad4978 SR	195	#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
86ea5f93	196
58ad4978 SR	197	#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
58ad4978 SR	198	#define CFG_FLASH_PROTECTION 1 /* hardware flash protection */
86ea5f93	199
58ad4978 SR	200	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
58ad4978 SR	201	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
86ea5f93	202
58ad4978 SR	203	#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
	204	#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
	205
360b4103	206	#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
58ad4978	207
360b4103	208	#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
58ad4978 SR	209	#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
	210	#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
	211
	212	/* Address and size of Redundant Environment Sector */
	213	#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
	214	#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
	215
	216	#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */
86ea5f93	217
f149d864 WD	218	#if TEXT_BASE == CFG_FLASH_BASE
	219	#define CFG_LOWBOOT 1
	220	#endif
	221
86ea5f93 WD	222	/*
	223	* Memory map
	224	*/
	225	#define CFG_MBAR 0xf0000000
	226	#define CFG_SDRAM_BASE 0x00000000
	227	#define CFG_DEFAULT_MBAR 0x80000000
	228
	229	/* Use SRAM until RAM will be available */
	230	#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
	231	#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
	232
	233
	234	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	235	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	236	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	237
360b4103	238	#define CFG_MONITOR_BASE TEXT_BASE
86ea5f93 WD	239	#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
	240	# define CFG_RAMBOOT 1
	241	#endif
	242
	243	#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
58ad4978	244	#define CFG_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
86ea5f93 WD	245	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	246
	247	/*
	248	* Ethernet configuration
	249	*/
	250	#define CONFIG_MPC5xxx_FEC 1
	251	/*
	252	* Define CONFIG_FEC_10MBIT to force FEC at 10Mb
	253	*/
	254	/* #define CONFIG_FEC_10MBIT 1 */
58ad4978	255	#define CONFIG_PHY_ADDR 1
86ea5f93	256
e8143e72 WD	257	/*
	258	* LCD Splash Screen
	259	*/
360b4103	260	#if !defined(CONFIG_PRS200)
e8143e72	261	#define CONFIG_LCD 1
638dd145	262	#define CONFIG_PROGRESSBAR 1
360b4103 WD	263	#endif
360b4103 WD	264
e8143e72 WD	265	#if defined(CONFIG_LCD)
	266	#define CONFIG_SPLASH_SCREEN 1
	267	#define CFG_CONSOLE_IS_IN_ENV 1
360b4103	268	#define LCD_BPP LCD_MONOCHROME
e8143e72 WD	269	#endif
e8143e72 WD	270
86ea5f93 WD	271	/*
	272	* GPIO configuration
	273	*/
bfc81252 WD	274	/* 0x10000004 = 32MB SDRAM */
bfc81252 WD	275	/* 0x90000004 = 64MB SDRAM */
e8143e72 WD	276	#if defined(CONFIG_LCD)
	277	/* set PSC2 in UART mode */
	278	#define CFG_GPS_PORT_CONFIG 0x00000044
	279	#else
5725f94a	280	#define CFG_GPS_PORT_CONFIG 0x00000004
e8143e72	281	#endif
86ea5f93 WD	282
	283	/*
	284	* Miscellaneous configurable options
	285	*/
360b4103 WD	286	#define CFG_LONGHELP /* undef to save memory */
360b4103 WD	287	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
5dc11a51	288	#if defined(CONFIG_CMD_KGDB)
360b4103	289	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
86ea5f93	290	#else
360b4103	291	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
86ea5f93	292	#endif
360b4103	293	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
86ea5f93 WD	294	#define CFG_MAXARGS 16 /* max number of command args */
	295	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	296
360b4103	297	#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
86ea5f93 WD	298	#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
	299
	300	#define CFG_LOAD_ADDR 0x100000 /* default load address */
	301
	302	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	303
5dc11a51 JL	304	#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
	305	#if defined(CONFIG_CMD_KGDB)
	306	# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	307	#endif
	308
86ea5f93 WD	309	/*
	310	* Various low-level settings
	311	*/
86ea5f93 WD	312	#define CFG_HID0_INIT HID0_ICE \| HID0_ICFI
86ea5f93 WD	313	#define CFG_HID0_FINAL HID0_ICE
86ea5f93	314
86ea5f93 WD	315	#define CFG_BOOTCS_START CFG_FLASH_BASE
	316	#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
	317	#define CFG_BOOTCS_CFG 0x0004fb00
	318	#define CFG_CS0_START CFG_FLASH_BASE
	319	#define CFG_CS0_SIZE CFG_FLASH_SIZE
86ea5f93	320
05d8dce9 WD	321	/* Quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
	322	#define CFG_CS2_START 0x80000000
	323	#define CFG_CS2_SIZE 0x00001000
b81a4630	324	#define CFG_CS2_CFG 0x1d300
05d8dce9	325
a874c8c6 WD	326	/* Second Quad UART @0x80010000 */
	327	#define CFG_CS1_START 0x80010000
	328	#define CFG_CS1_SIZE 0x00001000
	329	#define CFG_CS1_CFG 0x1d300
	330
87791f3b WD	331	/*
	332	* Select one of quarts as a default
	333	* console. If undefined - PSC console
	334	* wil be default
	335	*/
86ea5f93 WD	336	#define CFG_CS_BURST 0x00000000
	337	#define CFG_CS_DEADCYCLE 0x33333333
	338
	339	#define CFG_RESET_ADDRESS 0xff000000
	340
87791f3b WD	341	/*
	342	* QUART Expanders support
	343	*/
	344	#if defined(CONFIG_QUART_CONSOLE)
	345	/*
	346	* We'll use NS16550 chip routines,
	347	*/
	348	#define CFG_NS16550 1
	349	#define CFG_NS16550_SERIAL 1
	350	#define CONFIG_CONS_INDEX 1
	351	/*
	352	* To achieve necessary offset on SC16C554
	353	* A0-A2 (register select) pins with NS16550
	354	* functions (in struct NS16550), REG_SIZE
	355	* should be 4, because A0-A2 pins are connected
	356	* to DA2-DA4 address bus lines.
	357	*/
	358	#define CFG_NS16550_REG_SIZE 4
	359	/*
	360	* LocalPlus Bus already inited in cpu_init_f(),
	361	* so can work with QUART's chip selects.
	362	* One of four SC16C554 UARTs is selected with
	363	* A3-A4 (DA5-DA6) lines.
	364	*/
ed1cf845	365	#if (CONFIG_QUART_CONSOLE > 0) && (CONFIG_QUART_CONSOLE < 5) && !defined(CONFIG_PRS200)
87791f3b WD	366	#define CFG_NS16550_COM1 (CFG_CS2_START \| (CONFIG_QUART_CONSOLE - 1)<<5)
	367	#elif (CONFIG_QUART_CONSOLE > 4) && (CONFIG_QUART_CONSOLE < 9)
	368	#define CFG_NS16550_COM1 (CFG_CS1_START \| (CONFIG_QUART_CONSOLE - 5)<<5)
	369	#elif
	370	#error "Wrong QUART expander number."
	371	#endif
	372
	373	/*
	374	* SC16C554 chip's external crystal oscillator frequency
	375	* is 7.3728 MHz
	376	*/
	377	#define CFG_NS16550_CLK 7372800
	378	#endif /* CONFIG_QUART_CONSOLE */
86ea5f93 WD	379	/*-----------------------------------------------------------------------
	380	* USB stuff
	381	*-----------------------------------------------------------------------
	382	*/
	383	#define CONFIG_USB_CLOCK 0x0001BBBB
	384	#define CONFIG_USB_CONFIG 0x00005000
	385
86ea5f93	386	#endif /* __CONFIG_H */