projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 76316a31 | 1 | /* |
| 4aecfb16 | 2 | * (C) Copyright 2007-2010 Michal Simek |
| 76316a31 | 3 | * |
| cb1bc63b | 4 | * Michal SIMEK <monstr@monstr.eu> |
| 76316a31 | 5 | * |
| 1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
| 76316a31 MS |
7 | */ |
| 8 | ||
| 9 | #ifndef __CONFIG_H | |
| 10 | #define __CONFIG_H | |
| 11 | ||
| 52a822ed | 12 | #include "../board/xilinx/microblaze-generic/xparameters.h" |
| 76316a31 | 13 | |
| 4aecfb16 | 14 | /* MicroBlaze CPU */ |
| 1a50f164 | 15 | #define MICROBLAZE_V5 1 |
| 76316a31 | 16 | |
| bcec8f49 | 17 | /* linear and spi flash memory */ |
| 1fe7e8fa SL |
18 | #ifdef XILINX_FLASH_START |
| 19 | #define FLASH | |
| bcec8f49 | 20 | #undef SPIFLASH |
| 1fe7e8fa SL |
21 | #undef RAMENV /* hold environment in flash */ |
| 22 | #else | |
| bcec8f49 | 23 | #ifdef XILINX_SPI_FLASH_BASEADDR |
| 1fe7e8fa | 24 | #undef FLASH |
| bcec8f49 SL |
25 | #define SPIFLASH |
| 26 | #undef RAMENV /* hold environment in flash */ | |
| 27 | #else | |
| 28 | #undef FLASH | |
| 29 | #undef SPIFLASH | |
| 1fe7e8fa SL |
30 | #define RAMENV /* hold environment in RAM */ |
| 31 | #endif | |
| bcec8f49 | 32 | #endif |
| 1fe7e8fa | 33 | |
| 76316a31 | 34 | /* uart */ |
| af7ae1a4 | 35 | #ifdef XILINX_UARTLITE_BASEADDR |
| 4aecfb16 MS |
36 | # define CONFIG_XILINX_UARTLITE |
| 37 | # define CONFIG_SERIAL_BASE XILINX_UARTLITE_BASEADDR | |
| 38 | # define CONFIG_BAUDRATE XILINX_UARTLITE_BAUDRATE | |
| 39 | # define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE } | |
| 40 | # define CONSOLE_ARG "console=console=ttyUL0,115200\0" | |
| e7d591e8 | 41 | #elif XILINX_UART16550_BASEADDR |
| 4aecfb16 | 42 | # define CONFIG_SYS_NS16550_SERIAL |
| 1de55ef1 SL |
43 | # if defined(__MICROBLAZEEL__) |
| 44 | # define CONFIG_SYS_NS16550_REG_SIZE -4 | |
| 45 | # else | |
| 46 | # define CONFIG_SYS_NS16550_REG_SIZE 4 | |
| 47 | # endif | |
| 4aecfb16 MS |
48 | # define CONFIG_CONS_INDEX 1 |
| 49 | # define CONFIG_SYS_NS16550_COM1 \ | |
| 1de55ef1 | 50 | ((XILINX_UART16550_BASEADDR & ~0xF) + 0x1000) |
| 4aecfb16 MS |
51 | # define CONFIG_SYS_NS16550_CLK XILINX_UART16550_CLOCK_HZ |
| 52 | # define CONFIG_BAUDRATE 115200 | |
| 53 | ||
| 54 | /* The following table includes the supported baudrates */ | |
| 55 | # define CONFIG_SYS_BAUDRATE_TABLE \ | |
| 56 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} | |
| 57 | # define CONSOLE_ARG "console=console=ttyS0,115200\0" | |
| e7d591e8 | 58 | #else |
| 4aecfb16 | 59 | # error Undefined uart |
| af7ae1a4 | 60 | #endif |
| 76316a31 MS |
61 | |
| 62 | /* setting reset address */ | |
| 14d0a02a | 63 | /*#define CONFIG_SYS_RESET_ADDRESS CONFIG_SYS_TEXT_BASE*/ |
| 76316a31 | 64 | |
| 17980495 | 65 | /* ethernet */ |
| 1252df06 | 66 | #undef CONFIG_SYS_ENET |
| d1d37b5c | 67 | #if defined(XILINX_EMACLITE_BASEADDR) || defined(CONFIG_OF_CONTROL) |
| 8422a35e | 68 | # define CONFIG_XILINX_EMACLITE 1 |
| 4aecfb16 | 69 | # define CONFIG_SYS_ENET |
| 8422a35e | 70 | #endif |
| e634138e MS |
71 | #if defined(XILINX_AXIEMAC_BASEADDR) |
| 72 | # define CONFIG_XILINX_AXIEMAC 1 | |
| 73 | # define CONFIG_SYS_ENET | |
| 74 | #endif | |
| 330e5545 | 75 | |
| e5845e21 | 76 | #undef ET_DEBUG |
| 17980495 | 77 | |
| 76316a31 | 78 | /* gpio */ |
| 4c6a6f02 | 79 | #ifdef XILINX_GPIO_BASEADDR |
| 4e779ad2 | 80 | # define CONFIG_XILINX_GPIO |
| 4aecfb16 | 81 | # define CONFIG_SYS_GPIO_0_ADDR XILINX_GPIO_BASEADDR |
| 4c6a6f02 | 82 | #endif |
| 76316a31 MS |
83 | |
| 84 | /* interrupt controller */ | |
| 4d49b280 | 85 | #ifdef XILINX_INTC_BASEADDR |
| 4aecfb16 MS |
86 | # define CONFIG_SYS_INTC_0_ADDR XILINX_INTC_BASEADDR |
| 87 | # define CONFIG_SYS_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS | |
| 4d49b280 | 88 | #endif |
| 76316a31 MS |
89 | |
| 90 | /* timer */ | |
| bcbb046b | 91 | #if defined(XILINX_TIMER_BASEADDR) && defined(XILINX_TIMER_IRQ) |
| 4aecfb16 MS |
92 | # define CONFIG_SYS_TIMER_0_ADDR XILINX_TIMER_BASEADDR |
| 93 | # define CONFIG_SYS_TIMER_0_IRQ XILINX_TIMER_IRQ | |
| 4d49b280 | 94 | #endif |
| bcbb046b | 95 | |
| 0f21f98d MS |
96 | /* watchdog */ |
| 97 | #if defined(XILINX_WATCHDOG_BASEADDR) && defined(XILINX_WATCHDOG_IRQ) | |
| 98 | # define CONFIG_WATCHDOG_BASEADDR XILINX_WATCHDOG_BASEADDR | |
| 99 | # define CONFIG_WATCHDOG_IRQ XILINX_WATCHDOG_IRQ | |
| 100 | # define CONFIG_HW_WATCHDOG | |
| 101 | # define CONFIG_XILINX_TB_WATCHDOG | |
| 102 | #endif | |
| 103 | ||
| 0f925822 MY |
104 | #if !defined(CONFIG_OF_CONTROL) || \ |
| 105 | (defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_OF_CONTROL)) | |
| 76316a31 | 106 | /* ddr sdram - main memory */ |
| e945f6dc MS |
107 | # define CONFIG_SYS_SDRAM_BASE XILINX_RAM_START |
| 108 | # define CONFIG_SYS_SDRAM_SIZE XILINX_RAM_SIZE | |
| 109 | #endif | |
| 110 | ||
| 111 | #define CONFIG_SYS_MALLOC_LEN 0xC0000 | |
| 112 | ||
| 113 | /* Stack location before relocation */ | |
| 4fcd0b33 MS |
114 | #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_TEXT_BASE - \ |
| 115 | CONFIG_SYS_MALLOC_F_LEN) | |
| 76316a31 | 116 | |
| 8f371b18 SL |
117 | /* |
| 118 | * CFI flash memory layout - Example | |
| 119 | * CONFIG_SYS_FLASH_BASE = 0x2200_0000; | |
| 120 | * CONFIG_SYS_FLASH_SIZE = 0x0080_0000; 8MB | |
| 121 | * | |
| 122 | * SECT_SIZE = 0x20000; 128kB is one sector | |
| 123 | * CONFIG_ENV_SIZE = SECT_SIZE; 128kB environment store | |
| 124 | * | |
| 125 | * 0x2200_0000 CONFIG_SYS_FLASH_BASE | |
| 126 | * FREE 256kB | |
| 127 | * 0x2204_0000 CONFIG_ENV_ADDR | |
| 128 | * ENV_AREA 128kB | |
| 129 | * 0x2206_0000 | |
| 130 | * FREE | |
| 131 | * 0x2280_0000 CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE | |
| 132 | * | |
| 133 | */ | |
| 134 | ||
| 76316a31 | 135 | #ifdef FLASH |
| 4aecfb16 MS |
136 | # define CONFIG_SYS_FLASH_BASE XILINX_FLASH_START |
| 137 | # define CONFIG_SYS_FLASH_SIZE XILINX_FLASH_SIZE | |
| 138 | # define CONFIG_SYS_FLASH_CFI 1 | |
| 139 | # define CONFIG_FLASH_CFI_DRIVER 1 | |
| 140 | /* ?empty sector */ | |
| 141 | # define CONFIG_SYS_FLASH_EMPTY_INFO 1 | |
| 142 | /* max number of memory banks */ | |
| 143 | # define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
| 144 | /* max number of sectors on one chip */ | |
| 145 | # define CONFIG_SYS_MAX_FLASH_SECT 512 | |
| 146 | /* hardware flash protection */ | |
| 147 | # define CONFIG_SYS_FLASH_PROTECTION | |
| 22ff7f4d MS |
148 | /* use buffered writes (20x faster) */ |
| 149 | # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 | |
| 4aecfb16 MS |
150 | # ifdef RAMENV |
| 151 | # define CONFIG_ENV_IS_NOWHERE 1 | |
| 152 | # define CONFIG_ENV_SIZE 0x1000 | |
| 153 | # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE) | |
| 154 | ||
| bcec8f49 | 155 | # else /* FLASH && !RAMENV */ |
| 4aecfb16 MS |
156 | # define CONFIG_ENV_IS_IN_FLASH 1 |
| 157 | /* 128K(one sector) for env */ | |
| 158 | # define CONFIG_ENV_SECT_SIZE 0x20000 | |
| 159 | # define CONFIG_ENV_ADDR \ | |
| 160 | (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE)) | |
| 161 | # define CONFIG_ENV_SIZE 0x20000 | |
| bcec8f49 | 162 | # endif /* FLASH && !RAMBOOT */ |
| 76316a31 | 163 | #else /* !FLASH */ |
| bcec8f49 SL |
164 | |
| 165 | #ifdef SPIFLASH | |
| 166 | # define CONFIG_SYS_NO_FLASH 1 | |
| 167 | # define CONFIG_SYS_SPI_BASE XILINX_SPI_FLASH_BASEADDR | |
| bcec8f49 | 168 | # define CONFIG_SPI 1 |
| bcec8f49 SL |
169 | # define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 |
| 170 | # define CONFIG_SF_DEFAULT_SPEED XILINX_SPI_FLASH_MAX_FREQ | |
| 171 | # define CONFIG_SF_DEFAULT_CS XILINX_SPI_FLASH_CS | |
| 172 | ||
| 173 | # ifdef RAMENV | |
| 174 | # define CONFIG_ENV_IS_NOWHERE 1 | |
| 175 | # define CONFIG_ENV_SIZE 0x1000 | |
| 176 | # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE) | |
| 177 | ||
| 178 | # else /* SPIFLASH && !RAMENV */ | |
| 179 | # define CONFIG_ENV_IS_IN_SPI_FLASH 1 | |
| 180 | # define CONFIG_ENV_SPI_MODE SPI_MODE_3 | |
| 181 | # define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED | |
| 182 | # define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS | |
| 183 | /* 128K(two sectors) for env */ | |
| 184 | # define CONFIG_ENV_SECT_SIZE 0x10000 | |
| 185 | # define CONFIG_ENV_SIZE (2 * CONFIG_ENV_SECT_SIZE) | |
| 186 | /* Warning: adjust the offset in respect of other flash content and size */ | |
| 187 | # define CONFIG_ENV_OFFSET (128 * CONFIG_ENV_SECT_SIZE) /* at 8MB */ | |
| 188 | # endif /* SPIFLASH && !RAMBOOT */ | |
| 189 | #else /* !SPIFLASH */ | |
| 190 | ||
| 4aecfb16 MS |
191 | /* ENV in RAM */ |
| 192 | # define CONFIG_SYS_NO_FLASH 1 | |
| 193 | # define CONFIG_ENV_IS_NOWHERE 1 | |
| 194 | # define CONFIG_ENV_SIZE 0x1000 | |
| 195 | # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE) | |
| bcec8f49 | 196 | #endif /* !SPIFLASH */ |
| 76316a31 MS |
197 | #endif /* !FLASH */ |
| 198 | ||
| 853643d8 MS |
199 | /* system ace */ |
| 200 | #ifdef XILINX_SYSACE_BASEADDR | |
| 4aecfb16 MS |
201 | # define CONFIG_SYSTEMACE |
| 202 | /* #define DEBUG_SYSTEMACE */ | |
| 203 | # define SYSTEMACE_CONFIG_FPGA | |
| 204 | # define CONFIG_SYS_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR | |
| 205 | # define CONFIG_SYS_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH | |
| 206 | # define CONFIG_DOS_PARTITION | |
| 853643d8 MS |
207 | #endif |
| 208 | ||
| e9b737de | 209 | #if defined(XILINX_USE_ICACHE) |
| 4aecfb16 | 210 | # define CONFIG_ICACHE |
| e9b737de | 211 | #else |
| 4aecfb16 | 212 | # undef CONFIG_ICACHE |
| e9b737de MS |
213 | #endif |
| 214 | ||
| 215 | #if defined(XILINX_USE_DCACHE) | |
| 4aecfb16 | 216 | # define CONFIG_DCACHE |
| e9b737de | 217 | #else |
| 4aecfb16 | 218 | # undef CONFIG_DCACHE |
| e9b737de MS |
219 | #endif |
| 220 | ||
| 5811830f MS |
221 | #ifndef XILINX_DCACHE_BYTE_SIZE |
| 222 | #define XILINX_DCACHE_BYTE_SIZE 32768 | |
| 223 | #endif | |
| 224 | ||
| 079a136c JL |
225 | /* |
| 226 | * BOOTP options | |
| 227 | */ | |
| 228 | #define CONFIG_BOOTP_BOOTFILESIZE | |
| 229 | #define CONFIG_BOOTP_BOOTPATH | |
| 230 | #define CONFIG_BOOTP_GATEWAY | |
| 231 | #define CONFIG_BOOTP_HOSTNAME | |
| 76316a31 | 232 | |
| 5dc11a51 JL |
233 | /* |
| 234 | * Command line configuration. | |
| 235 | */ | |
| 5dc11a51 | 236 | #define CONFIG_CMD_ASKENV |
| 5dc11a51 | 237 | #define CONFIG_CMD_IRQ |
| 5dc11a51 | 238 | #define CONFIG_CMD_MFSL |
| 4d49b280 | 239 | |
| e9b737de | 240 | #if defined(CONFIG_DCACHE) || defined(CONFIG_ICACHE) |
| 4aecfb16 | 241 | # define CONFIG_CMD_CACHE |
| e9b737de | 242 | #else |
| 4aecfb16 | 243 | # undef CONFIG_CMD_CACHE |
| e9b737de MS |
244 | #endif |
| 245 | ||
| ef0f2f57 | 246 | #ifdef CONFIG_SYS_ENET |
| 4aecfb16 MS |
247 | # define CONFIG_CMD_PING |
| 248 | # define CONFIG_CMD_DHCP | |
| 4eb29cf0 | 249 | # define CONFIG_CMD_TFTPPUT |
| 4d49b280 | 250 | #endif |
| 853643d8 MS |
251 | |
| 252 | #if defined(CONFIG_SYSTEMACE) | |
| 4aecfb16 MS |
253 | # define CONFIG_CMD_EXT2 |
| 254 | # define CONFIG_CMD_FAT | |
| 853643d8 | 255 | #endif |
| 5dc11a51 JL |
256 | |
| 257 | #if defined(FLASH) | |
| 4aecfb16 | 258 | # define CONFIG_CMD_JFFS2 |
| 7cfb13a7 SL |
259 | # define CONFIG_CMD_UBI |
| 260 | # undef CONFIG_CMD_UBIFS | |
| 4aecfb16 | 261 | |
| bcec8f49 | 262 | # if !defined(RAMENV) |
| bcec8f49 SL |
263 | # define CONFIG_CMD_SAVES |
| 264 | # endif | |
| 265 | ||
| 266 | #else | |
| 267 | #if defined(SPIFLASH) | |
| 268 | # define CONFIG_CMD_SF | |
| 269 | ||
| 4aecfb16 | 270 | # if !defined(RAMENV) |
| 4aecfb16 MS |
271 | # define CONFIG_CMD_SAVES |
| 272 | # endif | |
| 853643d8 | 273 | #else |
| 4aecfb16 | 274 | # undef CONFIG_CMD_JFFS2 |
| 2cce2d32 SL |
275 | # undef CONFIG_CMD_UBI |
| 276 | # undef CONFIG_CMD_UBIFS | |
| 5dc11a51 | 277 | #endif |
| bcec8f49 | 278 | #endif |
| 76316a31 | 279 | |
| 5dc11a51 | 280 | #if defined(CONFIG_CMD_JFFS2) |
| 7cfb13a7 SL |
281 | # define CONFIG_MTD_PARTITIONS |
| 282 | #endif | |
| 283 | ||
| 284 | #if defined(CONFIG_CMD_UBIFS) | |
| 285 | # define CONFIG_CMD_UBI | |
| 286 | # define CONFIG_LZO | |
| 287 | #endif | |
| 288 | ||
| 289 | #if defined(CONFIG_CMD_UBI) | |
| 290 | # define CONFIG_MTD_PARTITIONS | |
| 291 | # define CONFIG_RBTREE | |
| 292 | #endif | |
| 293 | ||
| 294 | #if defined(CONFIG_MTD_PARTITIONS) | |
| 295 | /* MTD partitions */ | |
| 68d7d651 | 296 | #define CONFIG_CMD_MTDPARTS /* mtdparts command line support */ |
| 942556a9 SR |
297 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
| 298 | #define CONFIG_FLASH_CFI_MTD | |
| c82a541d | 299 | #define MTDIDS_DEFAULT "nor0=flash-0" |
| 144876a3 MS |
300 | |
| 301 | /* default mtd partition table */ | |
| c82a541d | 302 | #define MTDPARTS_DEFAULT "mtdparts=flash-0:256k(u-boot),"\ |
| 144876a3 MS |
303 | "256k(env),3m(kernel),1m(romfs),"\ |
| 304 | "1m(cramfs),-(jffs2)" | |
| 305 | #endif | |
| 306 | ||
| 4aecfb16 MS |
307 | /* size of console buffer */ |
| 308 | #define CONFIG_SYS_CBSIZE 512 | |
| 309 | /* print buffer size */ | |
| 310 | #define CONFIG_SYS_PBSIZE \ | |
| 311 | (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
| 312 | /* max number of command args */ | |
| 313 | #define CONFIG_SYS_MAXARGS 15 | |
| 6d0f6bcf | 314 | #define CONFIG_SYS_LONGHELP |
| 4aecfb16 MS |
315 | /* default load address */ |
| 316 | #define CONFIG_SYS_LOAD_ADDR XILINX_RAM_START | |
| 76316a31 | 317 | |
| 330e5545 | 318 | #define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ |
| 76316a31 | 319 | #define CONFIG_BOOTARGS "root=romfs" |
| 330e5545 | 320 | #define CONFIG_HOSTNAME XILINX_BOARD_NAME |
| 853643d8 | 321 | #define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm" |
| 76316a31 | 322 | #define CONFIG_IPADDR 192.168.0.3 |
| 853643d8 MS |
323 | #define CONFIG_SERVERIP 192.168.0.5 |
| 324 | #define CONFIG_GATEWAYIP 192.168.0.1 | |
| 76316a31 MS |
325 | |
| 326 | /* architecture dependent code */ | |
| 6d0f6bcf | 327 | #define CONFIG_SYS_USR_EXCEP /* user exception */ |
| 76316a31 | 328 | |
| 0900bee9 | 329 | #define CONFIG_PREBOOT "echo U-BOOT for ${hostname};setenv preboot;echo" |
| 144876a3 | 330 | |
| 4aecfb16 | 331 | #define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" \ |
| c82a541d SL |
332 | "nor0=flash-0\0"\ |
| 333 | "mtdparts=mtdparts=flash-0:"\ | |
| 144876a3 | 334 | "256k(u-boot),256k(env),3m(kernel),"\ |
| 78376452 MS |
335 | "1m(romfs),1m(cramfs),-(jffs2)\0"\ |
| 336 | "nc=setenv stdout nc;"\ | |
| 337 | "setenv stdin nc\0" \ | |
| 338 | "serial=setenv stdout serial;"\ | |
| 339 | "setenv stdin serial\0" | |
| 144876a3 | 340 | |
| 188dc16b | 341 | #define CONFIG_CMDLINE_EDITING |
| 188dc16b | 342 | |
| 78376452 MS |
343 | #define CONFIG_NETCONSOLE |
| 344 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV | |
| 345 | ||
| 0900bee9 MS |
346 | /* Use the HUSH parser */ |
| 347 | #define CONFIG_SYS_HUSH_PARSER | |
| 0900bee9 | 348 | |
| 37e892d9 MS |
349 | /* Enable flat device tree support */ |
| 350 | #define CONFIG_LMB 1 | |
| 351 | #define CONFIG_FIT 1 | |
| 352 | #define CONFIG_OF_LIBFDT 1 | |
| 353 | ||
| 4632b1ea | 354 | #if defined(CONFIG_XILINX_AXIEMAC) |
| f5e5e1ff SL |
355 | # define CONFIG_MII 1 |
| 356 | # define CONFIG_CMD_MII 1 | |
| 357 | # define CONFIG_PHY_GIGE 1 | |
| 358 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1 | |
| 359 | # define CONFIG_PHYLIB 1 | |
| 360 | # define CONFIG_PHY_ATHEROS 1 | |
| 361 | # define CONFIG_PHY_BROADCOM 1 | |
| 362 | # define CONFIG_PHY_DAVICOM 1 | |
| 363 | # define CONFIG_PHY_LXT 1 | |
| 364 | # define CONFIG_PHY_MARVELL 1 | |
| 365 | # define CONFIG_PHY_MICREL 1 | |
| 366 | # define CONFIG_PHY_NATSEMI 1 | |
| 367 | # define CONFIG_PHY_REALTEK 1 | |
| 368 | # define CONFIG_PHY_VITESSE 1 | |
| 369 | #else | |
| 370 | # undef CONFIG_MII | |
| 371 | # undef CONFIG_CMD_MII | |
| 372 | # undef CONFIG_PHYLIB | |
| 373 | #endif | |
| 374 | ||
| 9d242745 | 375 | /* SPL part */ |
| 9d242745 MS |
376 | #define CONFIG_CMD_SPL |
| 377 | #define CONFIG_SPL_FRAMEWORK | |
| 378 | #define CONFIG_SPL_LIBCOMMON_SUPPORT | |
| 379 | #define CONFIG_SPL_LIBGENERIC_SUPPORT | |
| 380 | #define CONFIG_SPL_SERIAL_SUPPORT | |
| 381 | #define CONFIG_SPL_BOARD_INIT | |
| 382 | ||
| 383 | #define CONFIG_SPL_LDSCRIPT "arch/microblaze/cpu/u-boot-spl.lds" | |
| 384 | ||
| 385 | #define CONFIG_SPL_RAM_DEVICE | |
| 4dd09742 MS |
386 | #ifdef CONFIG_SYS_FLASH_BASE |
| 387 | # define CONFIG_SPL_NOR_SUPPORT | |
| 388 | # define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_FLASH_BASE | |
| 389 | #endif | |
| 9d242745 MS |
390 | |
| 391 | /* for booting directly linux */ | |
| 392 | #define CONFIG_SPL_OS_BOOT | |
| 393 | ||
| 394 | #define CONFIG_SYS_OS_BASE (CONFIG_SYS_FLASH_BASE + \ | |
| 395 | 0x60000) | |
| 396 | #define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + \ | |
| 397 | 0x40000) | |
| 398 | #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_TEXT_BASE + \ | |
| 399 | 0x1000000) | |
| 400 | ||
| 401 | /* SP location before relocation, must use scratch RAM */ | |
| 402 | /* BRAM start */ | |
| 403 | #define CONFIG_SYS_INIT_RAM_ADDR 0x0 | |
| 404 | /* BRAM size - will be generated */ | |
| ca7d2266 | 405 | #define CONFIG_SYS_INIT_RAM_SIZE 0x100000 |
| 9d242745 | 406 | |
| ca7d2266 MS |
407 | # define CONFIG_SPL_STACK_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ |
| 408 | CONFIG_SYS_INIT_RAM_SIZE - \ | |
| 409 | CONFIG_SYS_MALLOC_F_LEN) | |
| 9d242745 MS |
410 | |
| 411 | /* Just for sure that there is a space for stack */ | |
| 412 | #define CONFIG_SPL_STACK_SIZE 0x100 | |
| 413 | ||
| 9d242745 MS |
414 | #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE |
| 415 | ||
| 416 | #define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_INIT_RAM_SIZE - \ | |
| 417 | CONFIG_SYS_INIT_RAM_ADDR - \ | |
| ca7d2266 | 418 | CONFIG_SYS_MALLOC_F_LEN - \ |
| 9d242745 MS |
419 | CONFIG_SPL_STACK_SIZE) |
| 420 | ||
| 76316a31 | 421 | #endif /* __CONFIG_H */ |