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bc8f8c26 IY |
1 | /* |
2 | * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. | |
3 | * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com | |
4 | * | |
5 | * | |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
bc8f8c26 IY |
7 | */ |
8 | ||
9 | #ifndef __CONFIG_H | |
10 | #define __CONFIG_H | |
11 | ||
12 | /* | |
13 | * High Level Configuration Options | |
14 | */ | |
15 | #define CONFIG_E300 1 /* E300 family */ | |
8afad91f | 16 | #define CONFIG_MPC830x 1 /* MPC830x family */ |
bc8f8c26 | 17 | #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ |
bc8f8c26 | 18 | |
2ae18241 WD |
19 | #ifndef CONFIG_SYS_TEXT_BASE |
20 | #define CONFIG_SYS_TEXT_BASE 0xFC000000 | |
21 | #endif | |
22 | ||
bc8f8c26 IY |
23 | /* |
24 | * On-board devices | |
25 | * | |
26 | * TSECs | |
27 | */ | |
28 | #define CONFIG_TSEC1 | |
29 | #define CONFIG_TSEC2 | |
30 | ||
31 | /* | |
32 | * System Clock Setup | |
33 | */ | |
34 | #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ | |
35 | #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN | |
36 | ||
37 | /* | |
38 | * Hardware Reset Configuration Word | |
39 | * if CLKIN is 66.66MHz, then | |
40 | * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz | |
41 | * We choose the A type silicon as default, so the core is 400Mhz. | |
42 | */ | |
43 | #define CONFIG_SYS_HRCW_LOW (\ | |
44 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ | |
45 | HRCWL_DDR_TO_SCB_CLK_2X1 |\ | |
46 | HRCWL_SVCOD_DIV_2 |\ | |
47 | HRCWL_CSB_TO_CLKIN_4X1 |\ | |
48 | HRCWL_CORE_TO_CSB_3X1) | |
49 | /* | |
50 | * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits | |
51 | * in 8308's HRCWH according to the manual, but original Freescale's | |
52 | * code has them and I've expirienced some problems using the board | |
53 | * with BDI3000 attached when I've tried to set these bits to zero | |
54 | * (UART doesn't work after the 'reset run' command). | |
55 | */ | |
56 | #define CONFIG_SYS_HRCW_HIGH (\ | |
57 | HRCWH_PCI_HOST |\ | |
58 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
59 | HRCWH_CORE_ENABLE |\ | |
60 | HRCWH_FROM_0X00000100 |\ | |
61 | HRCWH_BOOTSEQ_DISABLE |\ | |
62 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
63 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
64 | HRCWH_RL_EXT_LEGACY |\ | |
65 | HRCWH_TSEC1M_IN_MII |\ | |
66 | HRCWH_TSEC2M_IN_MII |\ | |
67 | HRCWH_BIG_ENDIAN) | |
68 | ||
69 | /* | |
70 | * System IO Config | |
71 | */ | |
72 | #define CONFIG_SYS_SICRH (\ | |
73 | SICRH_ESDHC_A_GPIO |\ | |
74 | SICRH_ESDHC_B_GPIO |\ | |
75 | SICRH_ESDHC_C_GTM |\ | |
76 | SICRH_GPIO_A_TSEC2 |\ | |
77 | SICRH_GPIO_B_TSEC2_TX_CLK |\ | |
78 | SICRH_IEEE1588_A_GPIO |\ | |
79 | SICRH_USB |\ | |
80 | SICRH_GTM_GPIO |\ | |
81 | SICRH_IEEE1588_B_GPIO |\ | |
82 | SICRH_ETSEC2_CRS |\ | |
83 | SICRH_GPIOSEL_1 |\ | |
84 | SICRH_TMROBI_V3P3 |\ | |
85 | SICRH_TSOBI1_V3P3 |\ | |
86 | SICRH_TSOBI2_V3P3) /* 0xf577d100 */ | |
87 | #define CONFIG_SYS_SICRL (\ | |
88 | SICRL_SPI_PF0 |\ | |
89 | SICRL_UART_PF0 |\ | |
90 | SICRL_IRQ_PF0 |\ | |
91 | SICRL_I2C2_PF0 |\ | |
92 | SICRL_ETSEC1_TX_CLK) /* 0x00000000 */ | |
93 | ||
94 | #define CONFIG_SYS_GPIO1_PRELIM | |
95 | /* GPIO Default input/output settings */ | |
96 | #define CONFIG_SYS_GPIO1_DIR 0x7AAF8C00 | |
97 | /* | |
98 | * Default GPIO values: | |
99 | * LED#1 enabled; WLAN enabled; Both COM LED on (orange) | |
100 | */ | |
101 | #define CONFIG_SYS_GPIO1_DAT 0x08008C00 | |
102 | ||
103 | /* | |
104 | * IMMR new address | |
105 | */ | |
106 | #define CONFIG_SYS_IMMR 0xE0000000 | |
107 | ||
108 | /* | |
109 | * SERDES | |
110 | */ | |
111 | #define CONFIG_FSL_SERDES | |
112 | #define CONFIG_FSL_SERDES1 0xe3000 | |
113 | ||
114 | /* | |
115 | * Arbiter Setup | |
116 | */ | |
117 | #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ | |
118 | #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ | |
119 | #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ | |
120 | ||
121 | /* | |
122 | * DDR Setup | |
123 | */ | |
124 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ | |
125 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
126 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
127 | #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 | |
128 | #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ | |
129 | | DDRCDR_PZ_LOZ \ | |
130 | | DDRCDR_NZ_LOZ \ | |
131 | | DDRCDR_ODT \ | |
132 | | DDRCDR_Q_DRN) | |
133 | /* 0x7b880001 */ | |
134 | /* | |
135 | * Manually set up DDR parameters | |
136 | * consist of two chips HY5PS12621BFP-C4 from HYNIX | |
137 | */ | |
138 | ||
139 | #define CONFIG_SYS_DDR_SIZE 128 /* MB */ | |
140 | ||
141 | #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 | |
142 | #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ | |
2fef4020 JH |
143 | | CSCONFIG_ODT_RD_NEVER \ |
144 | | CSCONFIG_ODT_WR_ONLY_CURRENT \ | |
145 | | CSCONFIG_ROW_BIT_13 \ | |
146 | | CSCONFIG_COL_BIT_10) | |
147 | /* 0x80010102 */ | |
bc8f8c26 IY |
148 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 |
149 | #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ | |
150 | | (0 << TIMING_CFG0_WRT_SHIFT) \ | |
151 | | (0 << TIMING_CFG0_RRT_SHIFT) \ | |
152 | | (0 << TIMING_CFG0_WWT_SHIFT) \ | |
153 | | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ | |
154 | | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ | |
155 | | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ | |
156 | | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) | |
157 | /* 0x00220802 */ | |
158 | #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ | |
159 | | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \ | |
160 | | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ | |
161 | | (5 << TIMING_CFG1_CASLAT_SHIFT) \ | |
162 | | (6 << TIMING_CFG1_REFREC_SHIFT) \ | |
163 | | (2 << TIMING_CFG1_WRREC_SHIFT) \ | |
164 | | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ | |
165 | | (2 << TIMING_CFG1_WRTORD_SHIFT)) | |
166 | /* 0x27256222 */ | |
167 | #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ | |
168 | | (4 << TIMING_CFG2_CPO_SHIFT) \ | |
169 | | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ | |
170 | | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ | |
171 | | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ | |
172 | | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ | |
173 | | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) | |
174 | /* 0x121048c5 */ | |
175 | #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \ | |
176 | | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) | |
177 | /* 0x03600100 */ | |
178 | #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ | |
179 | | SDRAM_CFG_SDRAM_TYPE_DDR2 \ | |
2fef4020 | 180 | | SDRAM_CFG_DBW_32) |
bc8f8c26 IY |
181 | /* 0x43080000 */ |
182 | ||
183 | #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ | |
184 | #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ | |
185 | | (0x0232 << SDRAM_MODE_SD_SHIFT)) | |
186 | /* ODT 150ohm CL=3, AL=1 on SDRAM */ | |
187 | #define CONFIG_SYS_DDR_MODE2 0x00000000 | |
188 | ||
189 | /* | |
190 | * Memory test | |
191 | */ | |
192 | #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ | |
193 | #define CONFIG_SYS_MEMTEST_END 0x07f00000 | |
194 | ||
195 | /* | |
196 | * The reserved memory | |
197 | */ | |
14d0a02a | 198 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
bc8f8c26 IY |
199 | |
200 | #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ | |
201 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ | |
202 | ||
203 | /* | |
204 | * Initial RAM Base Address Setup | |
205 | */ | |
206 | #define CONFIG_SYS_INIT_RAM_LOCK 1 | |
207 | #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ | |
80ae4df9 | 208 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ |
bc8f8c26 | 209 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
25ddd1fb | 210 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
bc8f8c26 IY |
211 | |
212 | /* | |
213 | * Local Bus Configuration & Clock Setup | |
214 | */ | |
215 | #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP | |
216 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 | |
217 | #define CONFIG_SYS_LBC_LBCR 0x00040000 | |
218 | ||
219 | /* | |
220 | * FLASH on the Local Bus | |
221 | */ | |
222 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ | |
223 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ | |
224 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT | |
225 | ||
226 | #define CONFIG_SYS_FLASH_BASE 0xFC000000 /* FLASH base address */ | |
227 | #define CONFIG_SYS_FLASH_SIZE 64 /* FLASH size is 64M */ | |
228 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ | |
229 | ||
230 | /* Window base at flash base */ | |
231 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE | |
232 | #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) | |
233 | ||
7d6a0982 JH |
234 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ |
235 | | BR_PS_16 /* 16 bit port */ \ | |
236 | | BR_MS_GPCM /* MSEL = GPCM */ \ | |
237 | | BR_V) /* valid */ | |
238 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ | |
bc8f8c26 IY |
239 | | OR_UPM_XAM \ |
240 | | OR_GPCM_CSNT \ | |
241 | | OR_GPCM_ACS_DIV2 \ | |
242 | | OR_GPCM_XACS \ | |
243 | | OR_GPCM_SCY_4 \ | |
7d6a0982 JH |
244 | | OR_GPCM_TRLX_SET \ |
245 | | OR_GPCM_EHTR_SET) | |
bc8f8c26 IY |
246 | |
247 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
248 | #define CONFIG_SYS_MAX_FLASH_SECT 512 | |
249 | ||
250 | /* Flash Erase Timeout (ms) */ | |
251 | #define CONFIG_SYS_FLASH_ERASE_TOUT (1000 * 1024) | |
252 | /* Flash Write Timeout (ms) */ | |
253 | #define CONFIG_SYS_FLASH_WRITE_TOUT (500 * 1024) | |
254 | ||
255 | /* | |
256 | * SJA1000 CAN controller on Local Bus | |
257 | */ | |
80ae4df9 JH |
258 | #define CONFIG_SYS_SJA1000_BASE 0xFBFF0000 |
259 | #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_SJA1000_BASE \ | |
7d6a0982 JH |
260 | | BR_PS_8 /* 8 bit port size */ \ |
261 | | BR_MS_GPCM /* MSEL = GPCM */ \ | |
262 | | BR_V) /* valid */ | |
263 | #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ | |
bc8f8c26 | 264 | | OR_GPCM_SCY_5 \ |
7d6a0982 | 265 | | OR_GPCM_EHTR_SET) |
bc8f8c26 IY |
266 | /* 0xFFFF8052 */ |
267 | ||
268 | #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_SJA1000_BASE | |
269 | #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) | |
270 | ||
271 | /* | |
272 | * CPLD on Local Bus | |
273 | */ | |
80ae4df9 JH |
274 | #define CONFIG_SYS_CPLD_BASE 0xFBFF8000 |
275 | #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_CPLD_BASE \ | |
7d6a0982 JH |
276 | | BR_PS_8 /* 8 bit port */ \ |
277 | | BR_MS_GPCM /* MSEL = GPCM */ \ | |
278 | | BR_V) /* valid */ | |
279 | #define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB \ | |
bc8f8c26 | 280 | | OR_GPCM_SCY_4 \ |
7d6a0982 | 281 | | OR_GPCM_EHTR_SET) |
bc8f8c26 IY |
282 | /* 0xFFFF8042 */ |
283 | ||
284 | #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_CPLD_BASE | |
285 | #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) | |
286 | ||
287 | /* | |
288 | * Serial Port | |
289 | */ | |
290 | #define CONFIG_CONS_INDEX 1 | |
291 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
bc8f8c26 IY |
292 | #define CONFIG_SYS_NS16550_SERIAL |
293 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
294 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
295 | ||
296 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
297 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
298 | ||
299 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) | |
300 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) | |
301 | ||
bc8f8c26 | 302 | /* I2C */ |
00f792e0 HS |
303 | #define CONFIG_SYS_I2C |
304 | #define CONFIG_SYS_I2C_FSL | |
305 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
306 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
307 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
308 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
309 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
310 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
bc8f8c26 IY |
311 | |
312 | /* | |
313 | * General PCI | |
314 | * Addresses are mapped 1-1. | |
315 | */ | |
316 | #define CONFIG_SYS_PCIE1_BASE 0xA0000000 | |
317 | #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 | |
318 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 | |
319 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 | |
320 | #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 | |
321 | #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 | |
322 | #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 | |
323 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 | |
324 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 | |
325 | ||
326 | /* enable PCIE clock */ | |
327 | #define CONFIG_SYS_SCCR_PCIEXP1CM 1 | |
328 | ||
842033e6 | 329 | #define CONFIG_PCI_INDIRECT_BRIDGE |
bc8f8c26 IY |
330 | #define CONFIG_PCIE |
331 | ||
bc8f8c26 IY |
332 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ |
333 | #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 | |
334 | ||
335 | /* | |
336 | * TSEC | |
337 | */ | |
bc8f8c26 IY |
338 | #define CONFIG_TSEC_ENET /* TSEC ethernet support */ |
339 | #define CONFIG_SYS_TSEC1_OFFSET 0x24000 | |
340 | #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) | |
341 | #define CONFIG_SYS_TSEC2_OFFSET 0x25000 | |
342 | #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) | |
343 | ||
344 | /* | |
345 | * TSEC ethernet configuration | |
346 | */ | |
347 | #define CONFIG_MII 1 /* MII PHY management */ | |
348 | #define CONFIG_TSEC1_NAME "eTSEC0" | |
349 | #define CONFIG_TSEC2_NAME "eTSEC1" | |
350 | #define TSEC1_PHY_ADDR 1 | |
351 | #define TSEC2_PHY_ADDR 2 | |
352 | #define TSEC1_PHYIDX 0 | |
353 | #define TSEC2_PHYIDX 0 | |
354 | #define TSEC1_FLAGS 0 | |
355 | #define TSEC2_FLAGS 0 | |
356 | ||
357 | /* Options are: eTSEC[0-1] */ | |
358 | #define CONFIG_ETHPRIME "eTSEC0" | |
359 | ||
360 | /* | |
361 | * Environment | |
362 | */ | |
bc8f8c26 IY |
363 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ |
364 | CONFIG_SYS_MONITOR_LEN) | |
365 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ | |
366 | #define CONFIG_ENV_SIZE 0x2000 | |
367 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) | |
368 | #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE | |
369 | ||
370 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
371 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
372 | ||
373 | /* | |
374 | * BOOTP options | |
375 | */ | |
376 | #define CONFIG_BOOTP_BOOTFILESIZE | |
377 | #define CONFIG_BOOTP_BOOTPATH | |
378 | #define CONFIG_BOOTP_GATEWAY | |
379 | #define CONFIG_BOOTP_HOSTNAME | |
380 | ||
381 | /* | |
382 | * Command line configuration. | |
383 | */ | |
bc8f8c26 IY |
384 | |
385 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
386 | ||
387 | /* | |
388 | * Miscellaneous configurable options | |
389 | */ | |
390 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
391 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
bc8f8c26 IY |
392 | |
393 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
394 | ||
bc8f8c26 IY |
395 | /* Boot Argument Buffer Size */ |
396 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
bc8f8c26 IY |
397 | |
398 | /* | |
399 | * For booting Linux, the board info and command line data | |
400 | * have to be in the first 8 MB of memory, since this is | |
401 | * the maximum mapped by the Linux kernel during initialization. | |
402 | */ | |
9eda770b | 403 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ |
bc8f8c26 IY |
404 | |
405 | /* | |
406 | * Core HID Setup | |
407 | */ | |
408 | #define CONFIG_SYS_HID0_INIT 0x000000000 | |
409 | #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ | |
410 | HID0_ENABLE_INSTRUCTION_CACHE | \ | |
411 | HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) | |
412 | #define CONFIG_SYS_HID2 HID2_HBE | |
413 | ||
414 | /* | |
415 | * MMU Setup | |
416 | */ | |
417 | ||
418 | /* DDR: cache cacheable */ | |
72cd4087 | 419 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ |
bc8f8c26 IY |
420 | BATL_MEMCOHERENCE) |
421 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ | |
422 | BATU_VS | BATU_VP) | |
423 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L | |
424 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
425 | ||
426 | /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ | |
72cd4087 | 427 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ |
bc8f8c26 IY |
428 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
429 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ | |
430 | BATU_VP) | |
431 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
432 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
433 | ||
434 | /* FLASH: icache cacheable, but dcache-inhibit and guarded */ | |
72cd4087 | 435 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ |
bc8f8c26 IY |
436 | BATL_MEMCOHERENCE) |
437 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ | |
438 | BATU_VS | BATU_VP) | |
72cd4087 | 439 | #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ |
bc8f8c26 IY |
440 | BATL_CACHEINHIBIT | \ |
441 | BATL_GUARDEDSTORAGE) | |
442 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
443 | ||
444 | /* Stack in dcache: cacheable, no memory coherence */ | |
72cd4087 | 445 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) |
bc8f8c26 IY |
446 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ |
447 | BATU_VS | BATU_VP) | |
448 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L | |
449 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
450 | ||
bc8f8c26 IY |
451 | /* |
452 | * Environment Configuration | |
453 | */ | |
454 | ||
455 | #define CONFIG_ENV_OVERWRITE | |
456 | ||
457 | #if defined(CONFIG_TSEC_ENET) | |
458 | #define CONFIG_HAS_ETH0 | |
459 | #define CONFIG_HAS_ETH1 | |
460 | #endif | |
461 | ||
bc8f8c26 IY |
462 | #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ |
463 | ||
bc8f8c26 | 464 | |
bc8f8c26 IY |
465 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
466 | "netdev=eth0\0" \ | |
467 | "consoledev=ttyS0\0" \ | |
468 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
469 | "nfsroot=${serverip}:${rootpath}\0" \ | |
470 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
471 | "addip=setenv bootargs ${bootargs} " \ | |
472 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
473 | ":${hostname}:${netdev}:off panic=1\0" \ | |
474 | "addtty=setenv bootargs ${bootargs}" \ | |
475 | " console=${consoledev},${baudrate}\0" \ | |
476 | "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ | |
477 | "addmisc=setenv bootargs ${bootargs}\0" \ | |
478 | "kernel_addr=FC0A0000\0" \ | |
479 | "fdt_addr=FC2A0000\0" \ | |
480 | "ramdisk_addr=FC2C0000\0" \ | |
481 | "u-boot=mpc8308_p1m/u-boot.bin\0" \ | |
482 | "kernel_addr_r=1000000\0" \ | |
483 | "fdt_addr_r=C00000\0" \ | |
484 | "hostname=mpc8308_p1m\0" \ | |
485 | "bootfile=mpc8308_p1m/uImage\0" \ | |
486 | "fdtfile=mpc8308_p1m/mpc8308_p1m.dtb\0" \ | |
487 | "rootpath=/opt/eldk-4.2/ppc_6xx\0" \ | |
488 | "flash_self=run ramargs addip addtty addmtd addmisc;" \ | |
489 | "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ | |
490 | "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ | |
491 | "bootm ${kernel_addr} - ${fdt_addr}\0" \ | |
492 | "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ | |
493 | "tftp ${fdt_addr_r} ${fdtfile};" \ | |
494 | "run nfsargs addip addtty addmtd addmisc;" \ | |
495 | "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ | |
496 | "bootcmd=run flash_self\0" \ | |
497 | "load=tftp ${loadaddr} ${u-boot}\0" \ | |
93ea89f0 MV |
498 | "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ |
499 | " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ | |
bc8f8c26 | 500 | " +${filesize};cp.b ${fileaddr} " \ |
93ea89f0 | 501 | __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ |
bc8f8c26 IY |
502 | "upd=run load update\0" \ |
503 | ||
504 | #endif /* __CONFIG_H */ |