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Commit | Line | Data |
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b2b5e2bb YS |
1 | /* |
2 | * Configuation settings for the Hitachi Solution Engine 7720 | |
3 | * | |
4 | * Copyright (C) 2007 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> | |
5 | * | |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
b2b5e2bb YS |
7 | */ |
8 | ||
9 | #ifndef __MS7720SE_H | |
10 | #define __MS7720SE_H | |
11 | ||
b2b5e2bb YS |
12 | #define CONFIG_SH 1 |
13 | #define CONFIG_SH3 1 | |
14 | #define CONFIG_CPU_SH7720 1 | |
15 | #define CONFIG_MS7720SE 1 | |
16 | ||
17 | #define CONFIG_CMD_FLASH | |
bdab39d3 | 18 | #define CONFIG_CMD_SAVEENV |
b2b5e2bb YS |
19 | #define CONFIG_CMD_SDRAM |
20 | #define CONFIG_CMD_MEMORY | |
21 | #define CONFIG_CMD_CACHE | |
22 | #define CONFIG_CMD_PCMCIA | |
23 | #define CONFIG_CMD_IDE | |
24 | #define CONFIG_CMD_EXT2 | |
25 | ||
b2b5e2bb YS |
26 | #define CONFIG_BAUDRATE 115200 |
27 | #define CONFIG_BOOTARGS "console=ttySC0,115200" | |
b3f44c21 | 28 | #define CONFIG_BOOTFILE "/boot/zImage" |
b2b5e2bb YS |
29 | #define CONFIG_LOADADDR 0x8E000000 |
30 | ||
31 | #define CONFIG_VERSION_VARIABLE | |
32 | #undef CONFIG_SHOW_BOOT_PROGRESS | |
33 | ||
34 | /* MEMORY */ | |
35 | #define MS7720SE_SDRAM_BASE 0x8C000000 | |
36 | #define MS7720SE_FLASH_BASE_1 0xA0000000 | |
37 | #define MS7720SE_FLASH_BANK_SIZE (8 * 1024 * 1024) | |
38 | ||
46198754 | 39 | #define CONFIG_SYS_TEXT_BASE 0x8FFC0000 |
6d0f6bcf | 40 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
6d0f6bcf JCPV |
41 | #define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */ |
42 | #define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ | |
43 | #define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */ | |
b2b5e2bb | 44 | /* Buffer size for Boot Arguments passed to kernel */ |
6d0f6bcf | 45 | #define CONFIG_SYS_BARGSIZE 512 |
b2b5e2bb | 46 | /* List of legal baudrate settings for this board */ |
6d0f6bcf | 47 | #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } |
b2b5e2bb YS |
48 | |
49 | /* SCIF */ | |
6c58a030 | 50 | #define CONFIG_SCIF_CONSOLE 1 |
b2b5e2bb YS |
51 | #define CONFIG_CONS_SCIF0 1 |
52 | ||
6d0f6bcf JCPV |
53 | #define CONFIG_SYS_MEMTEST_START MS7720SE_SDRAM_BASE |
54 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024)) | |
b2b5e2bb | 55 | |
6d0f6bcf JCPV |
56 | #define CONFIG_SYS_SDRAM_BASE MS7720SE_SDRAM_BASE |
57 | #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) | |
b2b5e2bb | 58 | |
6d0f6bcf JCPV |
59 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024) |
60 | #define CONFIG_SYS_MONITOR_BASE MS7720SE_FLASH_BASE_1 | |
61 | #define CONFIG_SYS_MONITOR_LEN (128 * 1024) | |
62 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) | |
6d0f6bcf | 63 | #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) |
b2b5e2bb YS |
64 | |
65 | ||
66 | /* FLASH */ | |
6d0f6bcf | 67 | #define CONFIG_SYS_FLASH_CFI |
00b1883a | 68 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
69 | #undef CONFIG_SYS_FLASH_QUIET_TEST |
70 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ | |
b2b5e2bb | 71 | |
6d0f6bcf | 72 | #define CONFIG_SYS_FLASH_BASE MS7720SE_FLASH_BASE_1 |
b2b5e2bb | 73 | |
6d0f6bcf JCPV |
74 | #define CONFIG_SYS_MAX_FLASH_SECT 150 |
75 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
76 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
b2b5e2bb | 77 | |
5a1aceb0 | 78 | #define CONFIG_ENV_IS_IN_FLASH |
0e8d1586 JCPV |
79 | #define CONFIG_ENV_SECT_SIZE (64 * 1024) |
80 | #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE | |
6d0f6bcf JCPV |
81 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
82 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 | |
83 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 | |
b2b5e2bb YS |
84 | |
85 | /* Board Clock */ | |
86 | #define CONFIG_SYS_CLK_FREQ 33333333 | |
684a501e NI |
87 | #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ |
88 | #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ | |
be45c632 | 89 | #define CONFIG_SYS_TMU_CLK_DIV 4 /* 4 (default), 16, 64, 256 or 1024 */ |
b2b5e2bb YS |
90 | |
91 | /* PCMCIA */ | |
92 | #define CONFIG_IDE_PCMCIA 1 | |
93 | #define CONFIG_MARUBUN_PCCARD 1 | |
94 | #define CONFIG_PCMCIA_SLOT_A 1 | |
6d0f6bcf JCPV |
95 | #define CONFIG_SYS_IDE_MAXDEVICE 1 |
96 | #define CONFIG_SYS_MARUBUN_MRSHPC 0xb83fffe0 | |
97 | #define CONFIG_SYS_MARUBUN_MW1 0xb8400000 | |
98 | #define CONFIG_SYS_MARUBUN_MW2 0xb8500000 | |
99 | #define CONFIG_SYS_MARUBUN_IO 0xb8600000 | |
100 | ||
101 | #define CONFIG_SYS_PIO_MODE 1 | |
102 | #define CONFIG_SYS_IDE_MAXBUS 1 | |
b2b5e2bb | 103 | #define CONFIG_DOS_PARTITION 1 |
6d0f6bcf JCPV |
104 | #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_MARUBUN_IO /* base address */ |
105 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */ | |
106 | #define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */ | |
107 | #define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */ | |
108 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */ | |
f2a37fcd | 109 | #define CONFIG_IDE_SWAP_IO |
b2b5e2bb YS |
110 | |
111 | #endif /* __MS7720SE_H */ |