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Commit | Line | Data |
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047375bf NI |
1 | /* |
2 | * Configuation settings for the Hitachi Solution Engine 7750 | |
3 | * | |
4 | * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> | |
5 | * | |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
047375bf NI |
7 | */ |
8 | ||
9 | #ifndef __MS7750SE_H | |
10 | #define __MS7750SE_H | |
69df3c4d | 11 | |
69df3c4d | 12 | #define CONFIG_CPU_SH7750 1 |
047375bf NI |
13 | /* #define CONFIG_CPU_SH7751 1 */ |
14 | /* #define CONFIG_CPU_TYPE_R 1 */ | |
69df3c4d NI |
15 | #define CONFIG_MS7750SE 1 |
16 | #define __LITTLE_ENDIAN__ 1 | |
17 | ||
18a40e84 VZ |
18 | #define CONFIG_DISPLAY_BOARDINFO |
19 | ||
047375bf NI |
20 | /* |
21 | * Command line configuration. | |
22 | */ | |
69df3c4d | 23 | #define CONFIG_CONS_SCIF1 1 |
69df3c4d | 24 | |
69df3c4d NI |
25 | #define CONFIG_ENV_OVERWRITE 1 |
26 | ||
047375bf | 27 | /* SDRAM */ |
6d0f6bcf JCPV |
28 | #define CONFIG_SYS_SDRAM_BASE (0x8C000000) |
29 | #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) | |
30 | ||
31 | #define CONFIG_SYS_LONGHELP | |
6d0f6bcf | 32 | #define CONFIG_SYS_PBSIZE 256 |
6d0f6bcf | 33 | #define CONFIG_SYS_BARGSIZE 512 |
69df3c4d | 34 | |
da8241ba | 35 | #define CONFIG_SYS_TEXT_BASE 0x8FFC0000 |
6d0f6bcf | 36 | #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) |
14d0a02a | 37 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000) |
69df3c4d | 38 | |
047375bf | 39 | /* NOR Flash */ |
6d0f6bcf JCPV |
40 | /* #define CONFIG_SYS_FLASH_BASE (0xA1000000)*/ |
41 | #define CONFIG_SYS_FLASH_BASE (0xA0000000) | |
42 | #define CONFIG_SYS_MAX_FLASH_BANKS (1) /* Max number of | |
53677ef1 WD |
43 | * Flash memory banks |
44 | */ | |
6d0f6bcf JCPV |
45 | #define CONFIG_SYS_MAX_FLASH_SECT 142 |
46 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
69df3c4d | 47 | |
6d0f6bcf JCPV |
48 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024) |
49 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) /* Address of u-boot image in Flash */ | |
50 | #define CONFIG_SYS_MONITOR_LEN (128 * 1024) | |
51 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */ | |
69df3c4d | 52 | |
6d0f6bcf JCPV |
53 | #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) |
54 | #define CONFIG_SYS_RX_ETH_BUFFER (8) | |
69df3c4d | 55 | |
6d0f6bcf | 56 | #define CONFIG_SYS_FLASH_CFI |
00b1883a | 57 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
58 | #undef CONFIG_SYS_FLASH_CFI_BROKEN_TABLE |
59 | #undef CONFIG_SYS_FLASH_QUIET_TEST | |
60 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ | |
69df3c4d | 61 | |
0e8d1586 JCPV |
62 | #define CONFIG_ENV_SECT_SIZE 0x20000 |
63 | #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) | |
6d0f6bcf JCPV |
64 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
65 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 | |
66 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 | |
69df3c4d | 67 | |
047375bf | 68 | /* Board Clock */ |
69df3c4d | 69 | #define CONFIG_SYS_CLK_FREQ 33333333 |
684a501e NI |
70 | #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ |
71 | #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ | |
be45c632 | 72 | #define CONFIG_SYS_TMU_CLK_DIV 4 |
69df3c4d | 73 | |
047375bf | 74 | #endif /* __MS7750SE_H */ |