[people/ms/u-boot.git] / include / configs / ms7750se.h

/*
 * Configuation settings for the Hitachi Solution Engine 7750
 *
 * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __MS7750SE_H
#define __MS7750SE_H

#define CONFIG_CPU_SH7750	1
/* #define CONFIG_CPU_SH7751	1 */
/* #define CONFIG_CPU_TYPE_R	1 */
#define CONFIG_MS7750SE		1
#define __LITTLE_ENDIAN__	1

#define CONFIG_DISPLAY_BOARDINFO

/*
 * Command line configuration.
 */
#define CONFIG_CONS_SCIF1	1

#define CONFIG_ENV_OVERWRITE	1

/* SDRAM */
#define CONFIG_SYS_SDRAM_BASE		(0x8C000000)
#define CONFIG_SYS_SDRAM_SIZE		(64 * 1024 * 1024)

#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_PBSIZE		256

#define CONFIG_SYS_TEXT_BASE		0x8FFC0000
#define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_TEXT_BASE - 0x100000)

/* NOR Flash */
/* #define CONFIG_SYS_FLASH_BASE		(0xA1000000)*/
#define CONFIG_SYS_FLASH_BASE		(0xA0000000)
#define CONFIG_SYS_MAX_FLASH_BANKS	(1)	/* Max number of
					 * Flash memory banks
					 */
#define CONFIG_SYS_MAX_FLASH_SECT	142
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }

#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE)	/* Address of u-boot image in Flash */
#define CONFIG_SYS_MONITOR_LEN		(128 * 1024)
#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)		/* Size of DRAM reserved for malloc() use */

#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
#define CONFIG_SYS_RX_ETH_BUFFER	(8)

#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#undef CONFIG_SYS_FLASH_CFI_BROKEN_TABLE
#undef  CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_SYS_FLASH_EMPTY_INFO				/* print 'E' for empty sector on flinfo */

#define CONFIG_ENV_SECT_SIZE	0x20000
#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_SYS_FLASH_ERASE_TOUT	120000
#define CONFIG_SYS_FLASH_WRITE_TOUT	500

/* Board Clock */
#define CONFIG_SYS_CLK_FREQ	33333333
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV		4

#endif /* __MS7750SE_H */
Commit	Line	Data
047375bf NI	1	/*
	2	* Configuation settings for the Hitachi Solution Engine 7750
	3	*
	4	* Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
047375bf NI	7	*/
	8
	9	#ifndef __MS7750SE_H
	10	#define __MS7750SE_H
69df3c4d	11
69df3c4d	12	#define CONFIG_CPU_SH7750 1
047375bf NI	13	/* #define CONFIG_CPU_SH7751 1 */
047375bf NI	14	/* #define CONFIG_CPU_TYPE_R 1 */
69df3c4d NI	15	#define CONFIG_MS7750SE 1
	16	#define __LITTLE_ENDIAN__ 1
	17
18a40e84 VZ	18	#define CONFIG_DISPLAY_BOARDINFO
18a40e84 VZ	19
047375bf NI	20	/*
	21	* Command line configuration.
	22	*/
69df3c4d	23	#define CONFIG_CONS_SCIF1 1
69df3c4d	24
69df3c4d NI	25	#define CONFIG_ENV_OVERWRITE 1
69df3c4d NI	26
047375bf	27	/* SDRAM */
6d0f6bcf JCPV	28	#define CONFIG_SYS_SDRAM_BASE (0x8C000000)
	29	#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
	30
	31	#define CONFIG_SYS_LONGHELP
6d0f6bcf	32	#define CONFIG_SYS_PBSIZE 256
69df3c4d	33
da8241ba	34	#define CONFIG_SYS_TEXT_BASE 0x8FFC0000
6d0f6bcf	35	#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
14d0a02a	36	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
69df3c4d	37
047375bf	38	/* NOR Flash */
6d0f6bcf JCPV	39	/* #define CONFIG_SYS_FLASH_BASE (0xA1000000)*/
	40	#define CONFIG_SYS_FLASH_BASE (0xA0000000)
	41	#define CONFIG_SYS_MAX_FLASH_BANKS (1) /* Max number of
53677ef1 WD	42	* Flash memory banks
53677ef1 WD	43	*/
6d0f6bcf JCPV	44	#define CONFIG_SYS_MAX_FLASH_SECT 142
6d0f6bcf JCPV	45	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
69df3c4d	46
6d0f6bcf JCPV	47	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
	48	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) /* Address of u-boot image in Flash */
	49	#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
	50	#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */
69df3c4d	51
6d0f6bcf JCPV	52	#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
6d0f6bcf JCPV	53	#define CONFIG_SYS_RX_ETH_BUFFER (8)
69df3c4d	54
6d0f6bcf	55	#define CONFIG_SYS_FLASH_CFI
00b1883a	56	#define CONFIG_FLASH_CFI_DRIVER
6d0f6bcf JCPV	57	#undef CONFIG_SYS_FLASH_CFI_BROKEN_TABLE
	58	#undef CONFIG_SYS_FLASH_QUIET_TEST
	59	#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
69df3c4d	60
0e8d1586 JCPV	61	#define CONFIG_ENV_SECT_SIZE 0x20000
0e8d1586 JCPV	62	#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
6d0f6bcf JCPV	63	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
	64	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
	65	#define CONFIG_SYS_FLASH_WRITE_TOUT 500
69df3c4d	66
047375bf	67	/* Board Clock */
69df3c4d	68	#define CONFIG_SYS_CLK_FREQ 33333333
684a501e NI	69	#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
684a501e NI	70	#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
be45c632	71	#define CONFIG_SYS_TMU_CLK_DIV 4
69df3c4d	72
047375bf	73	#endif /* __MS7750SE_H */