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[people/ms/u-boot.git] / include / configs / mx31ads.h
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1/*
2 * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
3 *
4 * Configuration settings for the MX31ADS Freescale board.
5 *
3765b3e7 6 * SPDX-License-Identifier: GPL-2.0+
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7 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
86271115 12#include <asm/arch/imx-regs.h>
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13
14 /* High Level Configuration Options */
3fd968e9 15#define CONFIG_MX31 1 /* This is a mx31 */
b5dc9b30 16
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17#define CONFIG_SYS_GENERIC_BOARD
18
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19#define CONFIG_DISPLAY_CPUINFO
20#define CONFIG_DISPLAY_BOARDINFO
21
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22#define CONFIG_SYS_TEXT_BASE 0xA0000000
23
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24#define CONFIG_MACH_TYPE MACH_TYPE_MX31ADS
25
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26/*
27 * Disabled for now due to build problems under Debian and a significant increase
28 * in the final file size: 144260 vs. 109536 Bytes.
29 */
30#if 0
31#define CONFIG_OF_LIBFDT 1
32#define CONFIG_FIT 1
33#define CONFIG_FIT_VERBOSE 1
34#endif
35
36#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
37#define CONFIG_SETUP_MEMORY_TAGS 1
38#define CONFIG_INITRD_TAG 1
39
40/*
41 * Size of malloc() pool
42 */
6d0f6bcf 43#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
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44
45/*
46 * Hardware drivers
47 */
48
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49#define CONFIG_MXC_UART
50#define CONFIG_MXC_UART_BASE UART1_BASE
b5dc9b30 51
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52#define CONFIG_HARD_SPI 1
53#define CONFIG_MXC_SPI 1
d255bb0e 54#define CONFIG_DEFAULT_SPI_BUS 1
9f481e95 55#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
5bd9a9b0 56#define CONFIG_MXC_GPIO
0a0b606f 57
d7d6780f 58/* PMIC Controller */
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59#define CONFIG_POWER
60#define CONFIG_POWER_SPI
61#define CONFIG_POWER_FSL
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62#define CONFIG_FSL_PMIC_BUS 1
63#define CONFIG_FSL_PMIC_CS 0
64#define CONFIG_FSL_PMIC_CLK 1000000
9f481e95 65#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
d7d6780f 66#define CONFIG_FSL_PMIC_BITLEN 32
4e8b7544 67#define CONFIG_RTC_MC13XXX
0a0b606f 68
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69/* allow to overwrite serial and ethaddr */
70#define CONFIG_ENV_OVERWRITE
71#define CONFIG_CONS_INDEX 1
72#define CONFIG_BAUDRATE 115200
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73
74/***********************************************************
75 * Command definition
76 ***********************************************************/
b5dc9b30 77#define CONFIG_CMD_PING
7602ed50 78#define CONFIG_CMD_DHCP
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79#define CONFIG_CMD_SPI
80#define CONFIG_CMD_DATE
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81
82#define CONFIG_BOOTDELAY 3
83
7602ed50 84#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
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85
86#define CONFIG_EXTRA_ENV_SETTINGS \
87 "netdev=eth0\0" \
88 "uboot_addr=0xa0000000\0" \
89 "uboot=mx31ads/u-boot.bin\0" \
90 "kernel=mx31ads/uImage\0" \
91 "nfsroot=/opt/eldk/arm\0" \
92 "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \
93 "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " \
94 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
95 "bootcmd=run bootcmd_net\0" \
96 "bootcmd_net=run bootargs_base bootargs_nfs; " \
97 "tftpboot ${loadaddr} ${kernel}; bootm\0" \
98 "prg_uboot=tftpboot ${loadaddr} ${uboot}; " \
99 "protect off ${uboot_addr} 0xa003ffff; " \
100 "erase ${uboot_addr} 0xa003ffff; " \
101 "cp.b ${loadaddr} ${uboot_addr} ${filesize}; " \
102 "setenv filesize; saveenv\0"
b5dc9b30 103
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104#define CONFIG_CS8900
105#define CONFIG_CS8900_BASE 0xb4020300
106#define CONFIG_CS8900_BUS16 1 /* follow the Linux driver */
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107
108/*
109 * The MX31ADS board seems to have a hardware "peculiarity" confirmed under
110 * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A
111 * controller inverted. The controller is capable of detecting and correcting
112 * this, but it needs 4 network packets for that. Which means, at startup, you
113 * will not receive answers to the first 4 packest, unless there have been some
114 * broadcasts on the network, or your board is on a hub. Reducing the ARP
115 * timeout from default 5 seconds to 200ms we speed up the initial TFTP
116 * transfer, should the user wish one, significantly.
117 */
118#define CONFIG_ARP_TIMEOUT 200UL
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119
120/*
121 * Miscellaneous configurable options
122 */
6d0f6bcf 123#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf 124#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
b5dc9b30 125/* Print Buffer Size */
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126#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
127#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
128#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
b5dc9b30 129
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130#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
131#define CONFIG_SYS_MEMTEST_END 0x10000
b5dc9b30 132
6d0f6bcf 133#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
b5dc9b30 134
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135#define CONFIG_CMDLINE_EDITING 1
136
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137/*-----------------------------------------------------------------------
138 * Physical Memory Map
139 */
140#define CONFIG_NR_DRAM_BANKS 1
141#define PHYS_SDRAM_1 CSD0_BASE
142#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
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143#define CONFIG_BOARD_EARLY_INIT_F
144
145#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
146#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
147#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
148#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
149 GENERATED_GBL_DATA_SIZE)
150#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
151 CONFIG_SYS_GBL_DATA_OFFSET)
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152
153/*-----------------------------------------------------------------------
154 * FLASH and environment organization
155 */
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156#define CONFIG_SYS_FLASH_BASE CS0_BASE
157#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
158#define CONFIG_SYS_MAX_FLASH_SECT 262 /* max number of sectors on one chip */
159#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */
160#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256KiB */
b5dc9b30 161
5a1aceb0 162#define CONFIG_ENV_IS_IN_FLASH 1
ba8dcca7 163#define CONFIG_ENV_SECT_SIZE (128 * 1024)
0e8d1586 164#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
ba8dcca7 165#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
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166
167/* Address and size of Redundant Environment Sector */
ba8dcca7 168#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
0e8d1586 169#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
d23ff682 170
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171
172/*-----------------------------------------------------------------------
173 * CFI FLASH driver setup
174 */
6d0f6bcf 175#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */
00b1883a 176#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
d23ff682 177#define CONFIG_FLASH_SPANSION_S29WS_N 1 /* A non-standard buffered write algorithm */
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178#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
179#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */
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180
181/*
182 * JFFS2 partitions
183 */
68d7d651 184#undef CONFIG_CMD_MTDPARTS
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185#define CONFIG_JFFS2_DEV "nor0"
186
187#endif /* __CONFIG_H */