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d5914017 MV |
1 | /* |
2 | * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> | |
3 | * | |
4 | * (C) Copyright 2009 Freescale Semiconductor, Inc. | |
5 | * | |
6 | * Configuration settings for the MX51EVK Board | |
7 | * | |
3765b3e7 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
d5914017 MV |
9 | */ |
10 | ||
11 | #ifndef __CONFIG_H | |
12 | #define __CONFIG_H | |
13 | ||
14 | #include <config_cmd_default.h> | |
15 | ||
16 | /* | |
17 | * High Level Board Configuration Options | |
18 | */ | |
19 | /* An i.MX51 CPU */ | |
20 | #define CONFIG_MX51 | |
af708cba MV |
21 | |
22 | #define machine_is_efikamx() (CONFIG_MACH_TYPE == MACH_TYPE_MX51_EFIKAMX) | |
23 | #define machine_is_efikasb() (CONFIG_MACH_TYPE == MACH_TYPE_MX51_EFIKASB) | |
24 | ||
d5914017 MV |
25 | #include <asm/arch/imx-regs.h> |
26 | ||
d5914017 MV |
27 | #define CONFIG_DISPLAY_CPUINFO |
28 | #define CONFIG_DISPLAY_BOARDINFO | |
29 | ||
745525f6 JR |
30 | #define CONFIG_SYS_TEXT_BASE 0x97800000 |
31 | ||
d98d8bc1 MV |
32 | #define CONFIG_L2_OFF |
33 | #define CONFIG_SYS_ICACHE_OFF | |
34 | #define CONFIG_SYS_DCACHE_OFF | |
35 | ||
d5914017 MV |
36 | /* |
37 | * Bootloader Components Configuration | |
38 | */ | |
39 | #define CONFIG_CMD_SPI | |
40 | #define CONFIG_CMD_SF | |
41 | #define CONFIG_CMD_MMC | |
42 | #define CONFIG_CMD_FAT | |
4e0499eb | 43 | #define CONFIG_CMD_EXT2 |
d5914017 | 44 | #define CONFIG_CMD_IDE |
d98d8bc1 MV |
45 | #define CONFIG_CMD_NET |
46 | #define CONFIG_CMD_DATE | |
d5914017 MV |
47 | #undef CONFIG_CMD_IMLS |
48 | ||
49 | /* | |
50 | * Environmental settings | |
51 | */ | |
52 | ||
53 | #define CONFIG_ENV_OFFSET (6 * 64 * 1024) | |
54 | #define CONFIG_ENV_SECT_SIZE (1 * 64 * 1024) | |
55 | #define CONFIG_ENV_SIZE (4 * 1024) | |
56 | ||
57 | /* | |
58 | * ATAG setup | |
59 | */ | |
60 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ | |
61 | #define CONFIG_REVISION_TAG | |
62 | #define CONFIG_SETUP_MEMORY_TAGS | |
63 | #define CONFIG_INITRD_TAG | |
64 | ||
2fa8ca98 GL |
65 | #define CONFIG_OF_LIBFDT 1 |
66 | ||
d5914017 MV |
67 | /* |
68 | * Size of malloc() pool | |
69 | */ | |
70 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) | |
71 | ||
72 | #define CONFIG_BOARD_EARLY_INIT_F | |
9660e442 | 73 | #define CONFIG_BOARD_LATE_INIT |
d5914017 MV |
74 | |
75 | /* | |
76 | * Hardware drivers | |
77 | */ | |
78 | #define CONFIG_MXC_UART | |
40f6fffe | 79 | #define CONFIG_MXC_UART_BASE UART1_BASE |
d5914017 MV |
80 | #define CONFIG_CONS_INDEX 1 |
81 | #define CONFIG_BAUDRATE 115200 | |
d5914017 MV |
82 | |
83 | #define CONFIG_MXC_GPIO | |
84 | ||
85 | /* | |
86 | * SPI Interface | |
87 | */ | |
88 | #ifdef CONFIG_CMD_SPI | |
89 | ||
90 | #define CONFIG_HARD_SPI | |
91 | #define CONFIG_MXC_SPI | |
92 | #define CONFIG_DEFAULT_SPI_BUS 1 | |
93 | #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) | |
94 | ||
95 | /* SPI FLASH */ | |
96 | #ifdef CONFIG_CMD_SF | |
97 | ||
98 | #define CONFIG_SPI_FLASH | |
99 | #define CONFIG_SPI_FLASH_SST | |
94f0003f | 100 | #define CONFIG_SF_DEFAULT_CS (1 | 121 << 8) |
d5914017 MV |
101 | #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) |
102 | #define CONFIG_SF_DEFAULT_SPEED 25000000 | |
103 | ||
104 | #define CONFIG_ENV_SPI_CS (1 | 121 << 8) | |
105 | #define CONFIG_ENV_SPI_BUS 0 | |
106 | #define CONFIG_ENV_SPI_MAX_HZ 25000000 | |
107 | #define CONFIG_ENV_SPI_MODE (SPI_MODE_0) | |
108 | #define CONFIG_FSL_ENV_IN_SF | |
109 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
110 | #define CONFIG_SYS_NO_FLASH | |
111 | ||
112 | #else | |
113 | #define CONFIG_ENV_IS_NOWHERE | |
114 | #endif | |
115 | ||
116 | /* SPI PMIC */ | |
be3b51aa ŁM |
117 | #define CONFIG_POWER |
118 | #define CONFIG_POWER_SPI | |
119 | #define CONFIG_POWER_FSL | |
d5914017 MV |
120 | #define CONFIG_FSL_PMIC_BUS 0 |
121 | #define CONFIG_FSL_PMIC_CS (0 | 120 << 8) | |
122 | #define CONFIG_FSL_PMIC_CLK 25000000 | |
123 | #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) | |
9c38f7df | 124 | #define CONFIG_FSL_PMIC_BITLEN 32 |
4e8b7544 | 125 | #define CONFIG_RTC_MC13XXX |
d5914017 MV |
126 | #endif |
127 | ||
128 | /* | |
129 | * MMC Configs | |
130 | */ | |
131 | #ifdef CONFIG_CMD_MMC | |
132 | #define CONFIG_MMC | |
133 | #define CONFIG_GENERIC_MMC | |
134 | #define CONFIG_FSL_ESDHC | |
135 | #define CONFIG_SYS_FSL_ESDHC_ADDR 0 | |
136 | #define CONFIG_SYS_FSL_ESDHC_NUM 2 | |
137 | #endif | |
138 | ||
139 | /* | |
140 | * ATA/IDE | |
141 | */ | |
142 | #ifdef CONFIG_CMD_IDE | |
143 | #define CONFIG_LBA48 | |
144 | #undef CONFIG_IDE_LED | |
145 | #undef CONFIG_IDE_RESET | |
146 | ||
147 | #define CONFIG_MX51_PATA | |
148 | ||
149 | #define __io | |
150 | ||
151 | #define CONFIG_SYS_IDE_MAXBUS 1 | |
152 | #define CONFIG_SYS_IDE_MAXDEVICE 1 | |
153 | ||
154 | #define CONFIG_SYS_ATA_BASE_ADDR 0x83fe0000 | |
155 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0 | |
156 | ||
157 | #define CONFIG_SYS_ATA_DATA_OFFSET 0xa0 | |
158 | #define CONFIG_SYS_ATA_REG_OFFSET 0xa0 | |
159 | #define CONFIG_SYS_ATA_ALT_OFFSET 0xd8 | |
160 | ||
161 | #define CONFIG_SYS_ATA_STRIDE 4 | |
162 | ||
163 | #define CONFIG_IDE_PREINIT | |
164 | #define CONFIG_MXC_ATA_PIO_MODE 4 | |
165 | #endif | |
166 | ||
d98d8bc1 MV |
167 | /* |
168 | * USB | |
169 | */ | |
170 | #define CONFIG_CMD_USB | |
171 | #ifdef CONFIG_CMD_USB | |
172 | #define CONFIG_USB_EHCI /* Enable EHCI USB support */ | |
173 | #define CONFIG_USB_EHCI_MX5 | |
174 | #define CONFIG_USB_ULPI | |
175 | #define CONFIG_USB_ULPI_VIEWPORT | |
176 | #define CONFIG_MXC_USB_PORT 1 | |
177 | #if (CONFIG_MXC_USB_PORT == 0) | |
178 | #define CONFIG_MXC_USB_PORTSC (1 << 28) | |
179 | #define CONFIG_MXC_USB_FLAGS MXC_EHCI_INTERNAL_PHY | |
180 | #else | |
181 | #define CONFIG_MXC_USB_PORTSC (2 << 30) | |
182 | #define CONFIG_MXC_USB_FLAGS 0 | |
183 | #endif | |
184 | #define CONFIG_EHCI_IS_TDI | |
185 | #define CONFIG_USB_STORAGE | |
186 | #define CONFIG_USB_HOST_ETHER | |
187 | #define CONFIG_USB_KEYBOARD | |
188 | #define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP | |
189 | #define CONFIG_PREBOOT | |
190 | /* USB NET */ | |
191 | #ifdef CONFIG_CMD_NET | |
192 | #define CONFIG_USB_ETHER_ASIX | |
d98d8bc1 MV |
193 | #define CONFIG_CMD_PING |
194 | #define CONFIG_CMD_DHCP | |
195 | #endif | |
196 | #endif /* CONFIG_CMD_USB */ | |
197 | ||
d5914017 MV |
198 | /* |
199 | * Filesystems | |
200 | */ | |
201 | #ifdef CONFIG_CMD_FAT | |
202 | #define CONFIG_DOS_PARTITION | |
d98d8bc1 MV |
203 | #ifdef CONFIG_CMD_NET |
204 | #define CONFIG_CMD_NFS | |
205 | #endif | |
d5914017 | 206 | #endif |
d5914017 MV |
207 | |
208 | /* | |
209 | * Miscellaneous configurable options | |
210 | */ | |
211 | #define CONFIG_ENV_OVERWRITE | |
212 | #define CONFIG_BOOTDELAY 3 | |
213 | #define CONFIG_LOADADDR 0x90800000 | |
214 | ||
215 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
216 | #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ | |
d5914017 MV |
217 | #define CONFIG_SYS_PROMPT "Efika> " |
218 | #define CONFIG_AUTO_COMPLETE | |
219 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
220 | /* Print Buffer Size */ | |
221 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
222 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
223 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
224 | ||
225 | #define CONFIG_SYS_MEMTEST_START 0x90000000 | |
f361a5c0 | 226 | #define CONFIG_SYS_MEMTEST_END 0x90010000 |
d5914017 MV |
227 | |
228 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR | |
229 | ||
d5914017 MV |
230 | #define CONFIG_CMDLINE_EDITING |
231 | ||
d5914017 MV |
232 | /*----------------------------------------------------------------------- |
233 | * Physical Memory Map | |
234 | */ | |
235 | #define CONFIG_NR_DRAM_BANKS 1 | |
236 | #define PHYS_SDRAM_1 CSD0_BASE_ADDR | |
237 | #define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) | |
238 | ||
239 | #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) | |
240 | #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) | |
241 | #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) | |
242 | ||
243 | #define CONFIG_SYS_INIT_SP_OFFSET \ | |
244 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
245 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
246 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
247 | ||
248 | #define CONFIG_SYS_DDR_CLKSEL 0 | |
b7171d92 | 249 | #define CONFIG_SYS_CLKTL_CBCDR 0x59E35145 |
39e85761 | 250 | #define CONFIG_SYS_MAIN_PWR_ON |
d5914017 MV |
251 | |
252 | #endif |