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1/*
2 * Copyright (C) 2010 Freescale Semiconductor, Inc.
3 *
4 * Configuration settings for the MX53-EVK Freescale board.
5 *
3765b3e7 6 * SPDX-License-Identifier: GPL-2.0+
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7 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
12#define CONFIG_MX53
94391fbc 13
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14#define CONFIG_MACH_TYPE MACH_TYPE_MX53_EVK
15
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16#include <asm/arch/imx-regs.h>
17
a7abca01 18#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
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19#define CONFIG_SETUP_MEMORY_TAGS
20#define CONFIG_INITRD_TAG
fd622f23 21#define CONFIG_REVISION_TAG
94391fbc 22
18fb0e3c 23#define CONFIG_SYS_FSL_CLK
851f556a 24
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25/* Size of malloc() pool */
26#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
27
28#define CONFIG_BOARD_EARLY_INIT_F
9660e442 29#define CONFIG_BOARD_LATE_INIT
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30#define CONFIG_MXC_GPIO
31
32#define CONFIG_MXC_UART
40f6fffe 33#define CONFIG_MXC_UART_BASE UART1_BASE
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34
35/* I2C Configs */
b089d039 36#define CONFIG_SYS_I2C
37#define CONFIG_SYS_I2C_MXC
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38#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
39#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
f8cb101e 40#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
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41
42/* PMIC Configs */
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43#define CONFIG_POWER
44#define CONFIG_POWER_I2C
45#define CONFIG_POWER_FSL
94391fbc 46#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 8
913702ca 47#define CONFIG_POWER_FSL_MC13892
4f97c88e 48#define CONFIG_RTC_MC13XXX
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49
50/* MMC Configs */
51#define CONFIG_FSL_ESDHC
52#define CONFIG_SYS_FSL_ESDHC_ADDR 0
53#define CONFIG_SYS_FSL_ESDHC_NUM 2
54
55#define CONFIG_MMC
94391fbc 56#define CONFIG_GENERIC_MMC
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57#define CONFIG_DOS_PARTITION
58
59/* Eth Configs */
94391fbc 60#define CONFIG_MII
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61
62#define CONFIG_FEC_MXC
63#define IMX_FEC_BASE FEC_BASE_ADDR
64#define CONFIG_FEC_MXC_PHYADDR 0x1F
65
4f97c88e 66#define CONFIG_CMD_DATE
94391fbc 67
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68/* Miscellaneous commands */
69#define CONFIG_CMD_BMODE
70
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71/* allow to overwrite serial and ethaddr */
72#define CONFIG_ENV_OVERWRITE
73#define CONFIG_CONS_INDEX 1
74#define CONFIG_BAUDRATE 115200
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75
76/* Command definition */
94391fbc 77
28b119e9 78#define CONFIG_ETHPRIME "FEC0"
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79
80#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */
81#define CONFIG_SYS_TEXT_BASE 0x77800000
82
83#define CONFIG_EXTRA_ENV_SETTINGS \
84 "script=boot.scr\0" \
85 "uimage=uImage\0" \
86 "mmcdev=0\0" \
87 "mmcpart=2\0" \
88 "mmcroot=/dev/mmcblk0p3 rw\0" \
89 "mmcrootfstype=ext3 rootwait\0" \
90 "mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \
91 "root=${mmcroot} " \
92 "rootfstype=${mmcrootfstype}\0" \
93 "loadbootscript=" \
94 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
95 "bootscript=echo Running bootscript from mmc ...; " \
96 "source\0" \
97 "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
98 "mmcboot=echo Booting from mmc ...; " \
99 "run mmcargs; " \
100 "bootm\0" \
101 "netargs=setenv bootargs console=ttymxc0,${baudrate} " \
102 "root=/dev/nfs " \
103 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
104 "netboot=echo Booting from net ...; " \
105 "run netargs; " \
106 "dhcp ${uimage}; bootm\0" \
107
108#define CONFIG_BOOTCOMMAND \
66968110 109 "mmc dev ${mmcdev}; if mmc rescan; then " \
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110 "if run loadbootscript; then " \
111 "run bootscript; " \
112 "else " \
113 "if run loaduimage; then " \
114 "run mmcboot; " \
115 "else run netboot; " \
116 "fi; " \
117 "fi; " \
118 "else run netboot; fi"
119
120#define CONFIG_ARP_TIMEOUT 200UL
121
122/* Miscellaneous configurable options */
123#define CONFIG_SYS_LONGHELP /* undef to save memory */
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124#define CONFIG_AUTO_COMPLETE
125#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
126
127/* Print Buffer Size */
128#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
129#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
130#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
131
132#define CONFIG_SYS_MEMTEST_START 0x70000000
bc9d5ef1 133#define CONFIG_SYS_MEMTEST_END 0x70010000
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134
135#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
136
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137#define CONFIG_CMDLINE_EDITING
138
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139/* Physical Memory Map */
140#define CONFIG_NR_DRAM_BANKS 1
141#define PHYS_SDRAM_1 CSD0_BASE_ADDR
142#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
143
144#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
145#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
146#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
147
148#define CONFIG_SYS_INIT_SP_OFFSET \
149 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
150#define CONFIG_SYS_INIT_SP_ADDR \
151 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
152
153/* FLASH and environment organization */
154#define CONFIG_SYS_NO_FLASH
155
156#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
157#define CONFIG_ENV_SIZE (8 * 1024)
158#define CONFIG_ENV_IS_IN_MMC
159#define CONFIG_SYS_MMC_ENV_DEV 0
160
161#endif /* __CONFIG_H */