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1/*
2 * Copyright (C) 2011 Freescale Semiconductor, Inc.
3 * Jason Liu <r64343@freescale.com>
4 *
5 * Configuration settings for Freescale MX53 low cost board.
6 *
3765b3e7 7 * SPDX-License-Identifier: GPL-2.0+
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8 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13#define CONFIG_MX53
14
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15#define CONFIG_MACH_TYPE MACH_TYPE_MX53_LOCO
16
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17#include <asm/arch/imx-regs.h>
18
19#define CONFIG_CMDLINE_TAG
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20#define CONFIG_SETUP_MEMORY_TAGS
21#define CONFIG_INITRD_TAG
22
18fb0e3c 23#define CONFIG_SYS_FSL_CLK
6ca896f9 24
938080dc 25/* Size of malloc() pool */
f714b0a9 26#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
938080dc 27
938080dc 28#define CONFIG_MXC_GPIO
54cd1dee 29#define CONFIG_REVISION_TAG
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30
31#define CONFIG_MXC_UART
40f6fffe 32#define CONFIG_MXC_UART_BASE UART1_BASE
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33
34/* MMC Configs */
35#define CONFIG_FSL_ESDHC
36#define CONFIG_SYS_FSL_ESDHC_ADDR 0
37#define CONFIG_SYS_FSL_ESDHC_NUM 2
38
938080dc 39#define CONFIG_GENERIC_MMC
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40#define CONFIG_DOS_PARTITION
41
42/* Eth Configs */
938080dc 43#define CONFIG_MII
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44
45#define CONFIG_FEC_MXC
46#define IMX_FEC_BASE FEC_BASE_ADDR
47#define CONFIG_FEC_MXC_PHYADDR 0x1F
48
45cf6ada 49/* USB Configs */
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50#define CONFIG_USB_EHCI
51#define CONFIG_USB_EHCI_MX5
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52#define CONFIG_USB_HOST_ETHER
53#define CONFIG_USB_ETHER_ASIX
a743415f 54#define CONFIG_USB_ETHER_MCS7830
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55#define CONFIG_USB_ETHER_SMSC95XX
56#define CONFIG_MXC_USB_PORT 1
57#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
58#define CONFIG_MXC_USB_FLAGS 0
59
e7e33722 60/* I2C Configs */
b089d039 61#define CONFIG_SYS_I2C
62#define CONFIG_SYS_I2C_MXC
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63#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
64#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
f8cb101e 65#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
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66
67/* PMIC Controller */
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68#define CONFIG_POWER
69#define CONFIG_POWER_I2C
2988e866 70#define CONFIG_DIALOG_POWER
be3b51aa 71#define CONFIG_POWER_FSL
913702ca 72#define CONFIG_POWER_FSL_MC13892
e7e33722 73#define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48
5b547f3c 74#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8
e7e33722 75
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76/* allow to overwrite serial and ethaddr */
77#define CONFIG_ENV_OVERWRITE
78#define CONFIG_CONS_INDEX 1
79#define CONFIG_BAUDRATE 115200
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80
81/* Command definition */
ec62c07a 82#define CONFIG_SUPPORT_RAW_INITRD
938080dc 83
938080dc 84
28b119e9 85#define CONFIG_ETHPRIME "FEC0"
938080dc 86
fe51f787 87#define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */
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88#define CONFIG_SYS_TEXT_BASE 0x77800000
89
90#define CONFIG_EXTRA_ENV_SETTINGS \
91 "script=boot.scr\0" \
f28154b5 92 "image=zImage\0" \
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93 "fdt_addr=0x71000000\0" \
94 "boot_fdt=try\0" \
95 "ip_dyn=yes\0" \
938080dc 96 "mmcdev=0\0" \
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97 "mmcpart=1\0" \
98 "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
e0df5353 99 "mmcargs=setenv bootargs console=ttymxc0,${baudrate} root=${mmcroot}\0" \
938080dc 100 "loadbootscript=" \
54e0f96f 101 "load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
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102 "bootscript=echo Running bootscript from mmc ...; " \
103 "source\0" \
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104 "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
105 "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
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106 "mmcboot=echo Booting from mmc ...; " \
107 "run mmcargs; " \
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108 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
109 "if run loadfdt; then " \
f28154b5 110 "bootz ${loadaddr} - ${fdt_addr}; " \
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111 "else " \
112 "if test ${boot_fdt} = try; then " \
f28154b5 113 "bootz; " \
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114 "else " \
115 "echo WARN: Cannot load the DT; " \
116 "fi; " \
117 "fi; " \
118 "else " \
f28154b5 119 "bootz; " \
e0df5353 120 "fi;\0" \
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121 "netargs=setenv bootargs console=ttymxc0,${baudrate} " \
122 "root=/dev/nfs " \
123 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
124 "netboot=echo Booting from net ...; " \
125 "run netargs; " \
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126 "if test ${ip_dyn} = yes; then " \
127 "setenv get_cmd dhcp; " \
128 "else " \
129 "setenv get_cmd tftp; " \
130 "fi; " \
f28154b5 131 "${get_cmd} ${image}; " \
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132 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
133 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
f28154b5 134 "bootz ${loadaddr} - ${fdt_addr}; " \
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135 "else " \
136 "if test ${boot_fdt} = try; then " \
f28154b5 137 "bootz; " \
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138 "else " \
139 "echo ERROR: Cannot load the DT; " \
140 "exit; " \
141 "fi; " \
142 "fi; " \
143 "else " \
f28154b5 144 "bootz; " \
e0df5353 145 "fi;\0"
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146
147#define CONFIG_BOOTCOMMAND \
66968110 148 "mmc dev ${mmcdev}; if mmc rescan; then " \
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149 "if run loadbootscript; then " \
150 "run bootscript; " \
151 "else " \
f28154b5 152 "if run loadimage; then " \
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153 "run mmcboot; " \
154 "else run netboot; " \
155 "fi; " \
156 "fi; " \
157 "else run netboot; fi"
158
159#define CONFIG_ARP_TIMEOUT 200UL
160
161/* Miscellaneous configurable options */
162#define CONFIG_SYS_LONGHELP /* undef to save memory */
938080dc 163#define CONFIG_AUTO_COMPLETE
e0df5353 164#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
938080dc 165
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166#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
167#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
168
169#define CONFIG_SYS_MEMTEST_START 0x70000000
170#define CONFIG_SYS_MEMTEST_END 0x70010000
171
172#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
173
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174#define CONFIG_CMDLINE_EDITING
175
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176/* Physical Memory Map */
177#define CONFIG_NR_DRAM_BANKS 2
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178#define PHYS_SDRAM_1 CSD0_BASE_ADDR
179#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size)
180#define PHYS_SDRAM_2 CSD1_BASE_ADDR
181#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size)
182#define PHYS_SDRAM_SIZE (gd->ram_size)
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183
184#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
185#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
186#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
187
188#define CONFIG_SYS_INIT_SP_OFFSET \
189 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
190#define CONFIG_SYS_INIT_SP_ADDR \
191 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
192
193/* FLASH and environment organization */
194#define CONFIG_SYS_NO_FLASH
195
196#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
197#define CONFIG_ENV_SIZE (8 * 1024)
198#define CONFIG_ENV_IS_IN_MMC
199#define CONFIG_SYS_MMC_ENV_DEV 0
200
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201#define CONFIG_CMD_SATA
202#ifdef CONFIG_CMD_SATA
203 #define CONFIG_DWC_AHSATA
204 #define CONFIG_SYS_SATA_MAX_DEVICE 1
205 #define CONFIG_DWC_AHSATA_PORT_ID 0
206 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR
207 #define CONFIG_LBA48
208 #define CONFIG_LIBATA
209#endif
210
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211/* Framebuffer and LCD */
212#define CONFIG_PREBOOT
695af9ab 213#define CONFIG_VIDEO_IPUV3
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214#define CONFIG_VIDEO_BMP_RLE8
215#define CONFIG_SPLASH_SCREEN
216#define CONFIG_BMP_16BPP
217#define CONFIG_VIDEO_LOGO
c606608a 218#define CONFIG_IPUV3_CLK 200000000
f714b0a9 219
938080dc 220#endif /* __CONFIG_H */