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938080dc JL |
1 | /* |
2 | * Copyright (C) 2011 Freescale Semiconductor, Inc. | |
3 | * Jason Liu <r64343@freescale.com> | |
4 | * | |
5 | * Configuration settings for Freescale MX53 low cost board. | |
6 | * | |
3765b3e7 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
938080dc JL |
8 | */ |
9 | ||
10 | #ifndef __CONFIG_H | |
11 | #define __CONFIG_H | |
12 | ||
13 | #define CONFIG_MX53 | |
14 | ||
9df82896 FE |
15 | #define CONFIG_MACH_TYPE MACH_TYPE_MX53_LOCO |
16 | ||
938080dc JL |
17 | #include <asm/arch/imx-regs.h> |
18 | ||
19 | #define CONFIG_CMDLINE_TAG | |
938080dc JL |
20 | #define CONFIG_SETUP_MEMORY_TAGS |
21 | #define CONFIG_INITRD_TAG | |
22 | ||
18fb0e3c | 23 | #define CONFIG_SYS_FSL_CLK |
6ca896f9 | 24 | |
938080dc | 25 | /* Size of malloc() pool */ |
f714b0a9 | 26 | #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) |
938080dc JL |
27 | |
28 | #define CONFIG_BOARD_EARLY_INIT_F | |
29 | #define CONFIG_MXC_GPIO | |
54cd1dee | 30 | #define CONFIG_REVISION_TAG |
938080dc JL |
31 | |
32 | #define CONFIG_MXC_UART | |
40f6fffe | 33 | #define CONFIG_MXC_UART_BASE UART1_BASE |
938080dc JL |
34 | |
35 | /* MMC Configs */ | |
36 | #define CONFIG_FSL_ESDHC | |
37 | #define CONFIG_SYS_FSL_ESDHC_ADDR 0 | |
38 | #define CONFIG_SYS_FSL_ESDHC_NUM 2 | |
39 | ||
938080dc | 40 | #define CONFIG_GENERIC_MMC |
938080dc JL |
41 | #define CONFIG_DOS_PARTITION |
42 | ||
43 | /* Eth Configs */ | |
938080dc | 44 | #define CONFIG_MII |
938080dc JL |
45 | |
46 | #define CONFIG_FEC_MXC | |
47 | #define IMX_FEC_BASE FEC_BASE_ADDR | |
48 | #define CONFIG_FEC_MXC_PHYADDR 0x1F | |
49 | ||
45cf6ada | 50 | /* USB Configs */ |
45cf6ada WG |
51 | #define CONFIG_USB_EHCI |
52 | #define CONFIG_USB_EHCI_MX5 | |
45cf6ada WG |
53 | #define CONFIG_USB_HOST_ETHER |
54 | #define CONFIG_USB_ETHER_ASIX | |
a743415f | 55 | #define CONFIG_USB_ETHER_MCS7830 |
45cf6ada WG |
56 | #define CONFIG_USB_ETHER_SMSC95XX |
57 | #define CONFIG_MXC_USB_PORT 1 | |
58 | #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) | |
59 | #define CONFIG_MXC_USB_FLAGS 0 | |
60 | ||
e7e33722 | 61 | /* I2C Configs */ |
b089d039 | 62 | #define CONFIG_SYS_I2C |
63 | #define CONFIG_SYS_I2C_MXC | |
03544c66 AA |
64 | #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ |
65 | #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ | |
f8cb101e | 66 | #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ |
e7e33722 FE |
67 | |
68 | /* PMIC Controller */ | |
be3b51aa ŁM |
69 | #define CONFIG_POWER |
70 | #define CONFIG_POWER_I2C | |
2988e866 | 71 | #define CONFIG_DIALOG_POWER |
be3b51aa | 72 | #define CONFIG_POWER_FSL |
913702ca | 73 | #define CONFIG_POWER_FSL_MC13892 |
e7e33722 | 74 | #define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48 |
5b547f3c | 75 | #define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8 |
e7e33722 | 76 | |
938080dc JL |
77 | /* allow to overwrite serial and ethaddr */ |
78 | #define CONFIG_ENV_OVERWRITE | |
79 | #define CONFIG_CONS_INDEX 1 | |
80 | #define CONFIG_BAUDRATE 115200 | |
938080dc JL |
81 | |
82 | /* Command definition */ | |
ec62c07a | 83 | #define CONFIG_SUPPORT_RAW_INITRD |
938080dc | 84 | |
938080dc | 85 | |
28b119e9 | 86 | #define CONFIG_ETHPRIME "FEC0" |
938080dc | 87 | |
fe51f787 | 88 | #define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */ |
938080dc JL |
89 | #define CONFIG_SYS_TEXT_BASE 0x77800000 |
90 | ||
91 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
92 | "script=boot.scr\0" \ | |
f28154b5 | 93 | "image=zImage\0" \ |
e0df5353 OS |
94 | "fdt_addr=0x71000000\0" \ |
95 | "boot_fdt=try\0" \ | |
96 | "ip_dyn=yes\0" \ | |
938080dc | 97 | "mmcdev=0\0" \ |
254fd8da OS |
98 | "mmcpart=1\0" \ |
99 | "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \ | |
e0df5353 | 100 | "mmcargs=setenv bootargs console=ttymxc0,${baudrate} root=${mmcroot}\0" \ |
938080dc | 101 | "loadbootscript=" \ |
54e0f96f | 102 | "load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ |
938080dc JL |
103 | "bootscript=echo Running bootscript from mmc ...; " \ |
104 | "source\0" \ | |
54e0f96f GG |
105 | "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ |
106 | "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ | |
938080dc JL |
107 | "mmcboot=echo Booting from mmc ...; " \ |
108 | "run mmcargs; " \ | |
e0df5353 OS |
109 | "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ |
110 | "if run loadfdt; then " \ | |
f28154b5 | 111 | "bootz ${loadaddr} - ${fdt_addr}; " \ |
e0df5353 OS |
112 | "else " \ |
113 | "if test ${boot_fdt} = try; then " \ | |
f28154b5 | 114 | "bootz; " \ |
e0df5353 OS |
115 | "else " \ |
116 | "echo WARN: Cannot load the DT; " \ | |
117 | "fi; " \ | |
118 | "fi; " \ | |
119 | "else " \ | |
f28154b5 | 120 | "bootz; " \ |
e0df5353 | 121 | "fi;\0" \ |
938080dc JL |
122 | "netargs=setenv bootargs console=ttymxc0,${baudrate} " \ |
123 | "root=/dev/nfs " \ | |
124 | "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ | |
125 | "netboot=echo Booting from net ...; " \ | |
126 | "run netargs; " \ | |
e0df5353 OS |
127 | "if test ${ip_dyn} = yes; then " \ |
128 | "setenv get_cmd dhcp; " \ | |
129 | "else " \ | |
130 | "setenv get_cmd tftp; " \ | |
131 | "fi; " \ | |
f28154b5 | 132 | "${get_cmd} ${image}; " \ |
e0df5353 OS |
133 | "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ |
134 | "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ | |
f28154b5 | 135 | "bootz ${loadaddr} - ${fdt_addr}; " \ |
e0df5353 OS |
136 | "else " \ |
137 | "if test ${boot_fdt} = try; then " \ | |
f28154b5 | 138 | "bootz; " \ |
e0df5353 OS |
139 | "else " \ |
140 | "echo ERROR: Cannot load the DT; " \ | |
141 | "exit; " \ | |
142 | "fi; " \ | |
143 | "fi; " \ | |
144 | "else " \ | |
f28154b5 | 145 | "bootz; " \ |
e0df5353 | 146 | "fi;\0" |
938080dc JL |
147 | |
148 | #define CONFIG_BOOTCOMMAND \ | |
66968110 | 149 | "mmc dev ${mmcdev}; if mmc rescan; then " \ |
938080dc JL |
150 | "if run loadbootscript; then " \ |
151 | "run bootscript; " \ | |
152 | "else " \ | |
f28154b5 | 153 | "if run loadimage; then " \ |
938080dc JL |
154 | "run mmcboot; " \ |
155 | "else run netboot; " \ | |
156 | "fi; " \ | |
157 | "fi; " \ | |
158 | "else run netboot; fi" | |
159 | ||
160 | #define CONFIG_ARP_TIMEOUT 200UL | |
161 | ||
162 | /* Miscellaneous configurable options */ | |
163 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
938080dc | 164 | #define CONFIG_AUTO_COMPLETE |
e0df5353 | 165 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ |
938080dc | 166 | |
938080dc JL |
167 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
168 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
169 | ||
170 | #define CONFIG_SYS_MEMTEST_START 0x70000000 | |
171 | #define CONFIG_SYS_MEMTEST_END 0x70010000 | |
172 | ||
173 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR | |
174 | ||
938080dc JL |
175 | #define CONFIG_CMDLINE_EDITING |
176 | ||
938080dc JL |
177 | /* Physical Memory Map */ |
178 | #define CONFIG_NR_DRAM_BANKS 2 | |
31c832f9 MV |
179 | #define PHYS_SDRAM_1 CSD0_BASE_ADDR |
180 | #define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size) | |
181 | #define PHYS_SDRAM_2 CSD1_BASE_ADDR | |
182 | #define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) | |
183 | #define PHYS_SDRAM_SIZE (gd->ram_size) | |
938080dc JL |
184 | |
185 | #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) | |
186 | #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) | |
187 | #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) | |
188 | ||
189 | #define CONFIG_SYS_INIT_SP_OFFSET \ | |
190 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
191 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
192 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
193 | ||
194 | /* FLASH and environment organization */ | |
195 | #define CONFIG_SYS_NO_FLASH | |
196 | ||
197 | #define CONFIG_ENV_OFFSET (6 * 64 * 1024) | |
198 | #define CONFIG_ENV_SIZE (8 * 1024) | |
199 | #define CONFIG_ENV_IS_IN_MMC | |
200 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
201 | ||
f92e4e6c SB |
202 | #define CONFIG_CMD_SATA |
203 | #ifdef CONFIG_CMD_SATA | |
204 | #define CONFIG_DWC_AHSATA | |
205 | #define CONFIG_SYS_SATA_MAX_DEVICE 1 | |
206 | #define CONFIG_DWC_AHSATA_PORT_ID 0 | |
207 | #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR | |
208 | #define CONFIG_LBA48 | |
209 | #define CONFIG_LIBATA | |
210 | #endif | |
211 | ||
f714b0a9 FE |
212 | /* Framebuffer and LCD */ |
213 | #define CONFIG_PREBOOT | |
695af9ab | 214 | #define CONFIG_VIDEO_IPUV3 |
f714b0a9 FE |
215 | #define CONFIG_VIDEO_BMP_RLE8 |
216 | #define CONFIG_SPLASH_SCREEN | |
217 | #define CONFIG_BMP_16BPP | |
218 | #define CONFIG_VIDEO_LOGO | |
c606608a | 219 | #define CONFIG_IPUV3_CLK 200000000 |
f714b0a9 | 220 | |
938080dc | 221 | #endif /* __CONFIG_H */ |