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938080dc JL |
1 | /* |
2 | * Copyright (C) 2011 Freescale Semiconductor, Inc. | |
3 | * Jason Liu <r64343@freescale.com> | |
4 | * | |
5 | * Configuration settings for Freescale MX53 low cost board. | |
6 | * | |
3765b3e7 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
938080dc JL |
8 | */ |
9 | ||
10 | #ifndef __CONFIG_H | |
11 | #define __CONFIG_H | |
12 | ||
9df82896 FE |
13 | #define CONFIG_MACH_TYPE MACH_TYPE_MX53_LOCO |
14 | ||
938080dc JL |
15 | #include <asm/arch/imx-regs.h> |
16 | ||
17 | #define CONFIG_CMDLINE_TAG | |
938080dc JL |
18 | #define CONFIG_SETUP_MEMORY_TAGS |
19 | #define CONFIG_INITRD_TAG | |
20 | ||
18fb0e3c | 21 | #define CONFIG_SYS_FSL_CLK |
6ca896f9 | 22 | |
938080dc | 23 | /* Size of malloc() pool */ |
f714b0a9 | 24 | #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) |
938080dc | 25 | |
54cd1dee | 26 | #define CONFIG_REVISION_TAG |
938080dc JL |
27 | |
28 | #define CONFIG_MXC_UART | |
40f6fffe | 29 | #define CONFIG_MXC_UART_BASE UART1_BASE |
938080dc JL |
30 | |
31 | /* MMC Configs */ | |
32 | #define CONFIG_FSL_ESDHC | |
33 | #define CONFIG_SYS_FSL_ESDHC_ADDR 0 | |
34 | #define CONFIG_SYS_FSL_ESDHC_NUM 2 | |
35 | ||
938080dc | 36 | /* Eth Configs */ |
938080dc | 37 | #define CONFIG_MII |
938080dc JL |
38 | |
39 | #define CONFIG_FEC_MXC | |
40 | #define IMX_FEC_BASE FEC_BASE_ADDR | |
41 | #define CONFIG_FEC_MXC_PHYADDR 0x1F | |
42 | ||
45cf6ada | 43 | /* USB Configs */ |
45cf6ada | 44 | #define CONFIG_USB_EHCI_MX5 |
45cf6ada WG |
45 | #define CONFIG_MXC_USB_PORT 1 |
46 | #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) | |
47 | #define CONFIG_MXC_USB_FLAGS 0 | |
48 | ||
e7e33722 | 49 | /* I2C Configs */ |
b089d039 | 50 | #define CONFIG_SYS_I2C |
51 | #define CONFIG_SYS_I2C_MXC | |
03544c66 AA |
52 | #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ |
53 | #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ | |
f8cb101e | 54 | #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ |
e7e33722 FE |
55 | |
56 | /* PMIC Controller */ | |
be3b51aa ŁM |
57 | #define CONFIG_POWER |
58 | #define CONFIG_POWER_I2C | |
2988e866 | 59 | #define CONFIG_DIALOG_POWER |
be3b51aa | 60 | #define CONFIG_POWER_FSL |
913702ca | 61 | #define CONFIG_POWER_FSL_MC13892 |
e7e33722 | 62 | #define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48 |
5b547f3c | 63 | #define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8 |
e7e33722 | 64 | |
938080dc JL |
65 | /* allow to overwrite serial and ethaddr */ |
66 | #define CONFIG_ENV_OVERWRITE | |
67 | #define CONFIG_CONS_INDEX 1 | |
938080dc JL |
68 | |
69 | /* Command definition */ | |
938080dc | 70 | |
938080dc | 71 | |
28b119e9 | 72 | #define CONFIG_ETHPRIME "FEC0" |
938080dc | 73 | |
fe51f787 | 74 | #define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */ |
938080dc JL |
75 | |
76 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
77 | "script=boot.scr\0" \ | |
f28154b5 | 78 | "image=zImage\0" \ |
e0df5353 OS |
79 | "fdt_addr=0x71000000\0" \ |
80 | "boot_fdt=try\0" \ | |
81 | "ip_dyn=yes\0" \ | |
938080dc | 82 | "mmcdev=0\0" \ |
254fd8da OS |
83 | "mmcpart=1\0" \ |
84 | "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \ | |
e0df5353 | 85 | "mmcargs=setenv bootargs console=ttymxc0,${baudrate} root=${mmcroot}\0" \ |
938080dc | 86 | "loadbootscript=" \ |
54e0f96f | 87 | "load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ |
938080dc JL |
88 | "bootscript=echo Running bootscript from mmc ...; " \ |
89 | "source\0" \ | |
54e0f96f GG |
90 | "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ |
91 | "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ | |
938080dc JL |
92 | "mmcboot=echo Booting from mmc ...; " \ |
93 | "run mmcargs; " \ | |
e0df5353 OS |
94 | "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ |
95 | "if run loadfdt; then " \ | |
f28154b5 | 96 | "bootz ${loadaddr} - ${fdt_addr}; " \ |
e0df5353 OS |
97 | "else " \ |
98 | "if test ${boot_fdt} = try; then " \ | |
f28154b5 | 99 | "bootz; " \ |
e0df5353 OS |
100 | "else " \ |
101 | "echo WARN: Cannot load the DT; " \ | |
102 | "fi; " \ | |
103 | "fi; " \ | |
104 | "else " \ | |
f28154b5 | 105 | "bootz; " \ |
e0df5353 | 106 | "fi;\0" \ |
938080dc JL |
107 | "netargs=setenv bootargs console=ttymxc0,${baudrate} " \ |
108 | "root=/dev/nfs " \ | |
109 | "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ | |
110 | "netboot=echo Booting from net ...; " \ | |
111 | "run netargs; " \ | |
e0df5353 OS |
112 | "if test ${ip_dyn} = yes; then " \ |
113 | "setenv get_cmd dhcp; " \ | |
114 | "else " \ | |
115 | "setenv get_cmd tftp; " \ | |
116 | "fi; " \ | |
f28154b5 | 117 | "${get_cmd} ${image}; " \ |
e0df5353 OS |
118 | "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ |
119 | "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ | |
f28154b5 | 120 | "bootz ${loadaddr} - ${fdt_addr}; " \ |
e0df5353 OS |
121 | "else " \ |
122 | "if test ${boot_fdt} = try; then " \ | |
f28154b5 | 123 | "bootz; " \ |
e0df5353 OS |
124 | "else " \ |
125 | "echo ERROR: Cannot load the DT; " \ | |
126 | "exit; " \ | |
127 | "fi; " \ | |
128 | "fi; " \ | |
129 | "else " \ | |
f28154b5 | 130 | "bootz; " \ |
e0df5353 | 131 | "fi;\0" |
938080dc JL |
132 | |
133 | #define CONFIG_BOOTCOMMAND \ | |
66968110 | 134 | "mmc dev ${mmcdev}; if mmc rescan; then " \ |
938080dc JL |
135 | "if run loadbootscript; then " \ |
136 | "run bootscript; " \ | |
137 | "else " \ | |
f28154b5 | 138 | "if run loadimage; then " \ |
938080dc JL |
139 | "run mmcboot; " \ |
140 | "else run netboot; " \ | |
141 | "fi; " \ | |
142 | "fi; " \ | |
143 | "else run netboot; fi" | |
144 | ||
145 | #define CONFIG_ARP_TIMEOUT 200UL | |
146 | ||
147 | /* Miscellaneous configurable options */ | |
e0df5353 | 148 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ |
938080dc | 149 | |
938080dc JL |
150 | #define CONFIG_SYS_MEMTEST_START 0x70000000 |
151 | #define CONFIG_SYS_MEMTEST_END 0x70010000 | |
152 | ||
153 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR | |
154 | ||
938080dc JL |
155 | /* Physical Memory Map */ |
156 | #define CONFIG_NR_DRAM_BANKS 2 | |
31c832f9 MV |
157 | #define PHYS_SDRAM_1 CSD0_BASE_ADDR |
158 | #define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size) | |
159 | #define PHYS_SDRAM_2 CSD1_BASE_ADDR | |
160 | #define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) | |
161 | #define PHYS_SDRAM_SIZE (gd->ram_size) | |
938080dc JL |
162 | |
163 | #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) | |
164 | #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) | |
165 | #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) | |
166 | ||
167 | #define CONFIG_SYS_INIT_SP_OFFSET \ | |
168 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
169 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
170 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
171 | ||
e856bdcf | 172 | /* environment organization */ |
938080dc JL |
173 | #define CONFIG_ENV_OFFSET (6 * 64 * 1024) |
174 | #define CONFIG_ENV_SIZE (8 * 1024) | |
938080dc JL |
175 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
176 | ||
f92e4e6c | 177 | #ifdef CONFIG_CMD_SATA |
f92e4e6c SB |
178 | #define CONFIG_SYS_SATA_MAX_DEVICE 1 |
179 | #define CONFIG_DWC_AHSATA_PORT_ID 0 | |
180 | #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR | |
181 | #define CONFIG_LBA48 | |
f92e4e6c SB |
182 | #endif |
183 | ||
f714b0a9 FE |
184 | /* Framebuffer and LCD */ |
185 | #define CONFIG_PREBOOT | |
695af9ab | 186 | #define CONFIG_VIDEO_IPUV3 |
f714b0a9 FE |
187 | #define CONFIG_VIDEO_BMP_RLE8 |
188 | #define CONFIG_SPLASH_SCREEN | |
189 | #define CONFIG_BMP_16BPP | |
190 | #define CONFIG_VIDEO_LOGO | |
191 | ||
938080dc | 192 | #endif /* __CONFIG_H */ |