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1/*
2 * Copyright (C) 2011 Freescale Semiconductor, Inc.
3 * Jason Liu <r64343@freescale.com>
4 *
5 * Configuration settings for Freescale MX53 low cost board.
6 *
3765b3e7 7 * SPDX-License-Identifier: GPL-2.0+
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8 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13#define CONFIG_MX53
14
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15#define CONFIG_MACH_TYPE MACH_TYPE_MX53_LOCO
16
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17#include <asm/arch/imx-regs.h>
18
19#define CONFIG_CMDLINE_TAG
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20#define CONFIG_SETUP_MEMORY_TAGS
21#define CONFIG_INITRD_TAG
22
18fb0e3c 23#define CONFIG_SYS_FSL_CLK
6ca896f9 24
938080dc 25/* Size of malloc() pool */
f714b0a9 26#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
938080dc 27
938080dc 28#define CONFIG_MXC_GPIO
54cd1dee 29#define CONFIG_REVISION_TAG
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30
31#define CONFIG_MXC_UART
40f6fffe 32#define CONFIG_MXC_UART_BASE UART1_BASE
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33
34/* MMC Configs */
35#define CONFIG_FSL_ESDHC
36#define CONFIG_SYS_FSL_ESDHC_ADDR 0
37#define CONFIG_SYS_FSL_ESDHC_NUM 2
38
938080dc 39/* Eth Configs */
938080dc 40#define CONFIG_MII
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41
42#define CONFIG_FEC_MXC
43#define IMX_FEC_BASE FEC_BASE_ADDR
44#define CONFIG_FEC_MXC_PHYADDR 0x1F
45
45cf6ada 46/* USB Configs */
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47#define CONFIG_USB_EHCI
48#define CONFIG_USB_EHCI_MX5
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49#define CONFIG_USB_HOST_ETHER
50#define CONFIG_USB_ETHER_ASIX
a743415f 51#define CONFIG_USB_ETHER_MCS7830
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52#define CONFIG_USB_ETHER_SMSC95XX
53#define CONFIG_MXC_USB_PORT 1
54#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
55#define CONFIG_MXC_USB_FLAGS 0
56
e7e33722 57/* I2C Configs */
b089d039 58#define CONFIG_SYS_I2C
59#define CONFIG_SYS_I2C_MXC
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60#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
61#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
f8cb101e 62#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
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63
64/* PMIC Controller */
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65#define CONFIG_POWER
66#define CONFIG_POWER_I2C
2988e866 67#define CONFIG_DIALOG_POWER
be3b51aa 68#define CONFIG_POWER_FSL
913702ca 69#define CONFIG_POWER_FSL_MC13892
e7e33722 70#define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48
5b547f3c 71#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8
e7e33722 72
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73/* allow to overwrite serial and ethaddr */
74#define CONFIG_ENV_OVERWRITE
75#define CONFIG_CONS_INDEX 1
76#define CONFIG_BAUDRATE 115200
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77
78/* Command definition */
ec62c07a 79#define CONFIG_SUPPORT_RAW_INITRD
938080dc 80
938080dc 81
28b119e9 82#define CONFIG_ETHPRIME "FEC0"
938080dc 83
fe51f787 84#define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */
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85#define CONFIG_SYS_TEXT_BASE 0x77800000
86
87#define CONFIG_EXTRA_ENV_SETTINGS \
88 "script=boot.scr\0" \
f28154b5 89 "image=zImage\0" \
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90 "fdt_addr=0x71000000\0" \
91 "boot_fdt=try\0" \
92 "ip_dyn=yes\0" \
938080dc 93 "mmcdev=0\0" \
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94 "mmcpart=1\0" \
95 "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
e0df5353 96 "mmcargs=setenv bootargs console=ttymxc0,${baudrate} root=${mmcroot}\0" \
938080dc 97 "loadbootscript=" \
54e0f96f 98 "load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
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99 "bootscript=echo Running bootscript from mmc ...; " \
100 "source\0" \
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101 "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
102 "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
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103 "mmcboot=echo Booting from mmc ...; " \
104 "run mmcargs; " \
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105 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
106 "if run loadfdt; then " \
f28154b5 107 "bootz ${loadaddr} - ${fdt_addr}; " \
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108 "else " \
109 "if test ${boot_fdt} = try; then " \
f28154b5 110 "bootz; " \
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111 "else " \
112 "echo WARN: Cannot load the DT; " \
113 "fi; " \
114 "fi; " \
115 "else " \
f28154b5 116 "bootz; " \
e0df5353 117 "fi;\0" \
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118 "netargs=setenv bootargs console=ttymxc0,${baudrate} " \
119 "root=/dev/nfs " \
120 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
121 "netboot=echo Booting from net ...; " \
122 "run netargs; " \
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123 "if test ${ip_dyn} = yes; then " \
124 "setenv get_cmd dhcp; " \
125 "else " \
126 "setenv get_cmd tftp; " \
127 "fi; " \
f28154b5 128 "${get_cmd} ${image}; " \
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129 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
130 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
f28154b5 131 "bootz ${loadaddr} - ${fdt_addr}; " \
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132 "else " \
133 "if test ${boot_fdt} = try; then " \
f28154b5 134 "bootz; " \
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135 "else " \
136 "echo ERROR: Cannot load the DT; " \
137 "exit; " \
138 "fi; " \
139 "fi; " \
140 "else " \
f28154b5 141 "bootz; " \
e0df5353 142 "fi;\0"
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143
144#define CONFIG_BOOTCOMMAND \
66968110 145 "mmc dev ${mmcdev}; if mmc rescan; then " \
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146 "if run loadbootscript; then " \
147 "run bootscript; " \
148 "else " \
f28154b5 149 "if run loadimage; then " \
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150 "run mmcboot; " \
151 "else run netboot; " \
152 "fi; " \
153 "fi; " \
154 "else run netboot; fi"
155
156#define CONFIG_ARP_TIMEOUT 200UL
157
158/* Miscellaneous configurable options */
159#define CONFIG_SYS_LONGHELP /* undef to save memory */
938080dc 160#define CONFIG_AUTO_COMPLETE
e0df5353 161#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
938080dc 162
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163#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
164#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
165
166#define CONFIG_SYS_MEMTEST_START 0x70000000
167#define CONFIG_SYS_MEMTEST_END 0x70010000
168
169#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
170
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171#define CONFIG_CMDLINE_EDITING
172
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173/* Physical Memory Map */
174#define CONFIG_NR_DRAM_BANKS 2
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175#define PHYS_SDRAM_1 CSD0_BASE_ADDR
176#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size)
177#define PHYS_SDRAM_2 CSD1_BASE_ADDR
178#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size)
179#define PHYS_SDRAM_SIZE (gd->ram_size)
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180
181#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
182#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
183#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
184
185#define CONFIG_SYS_INIT_SP_OFFSET \
186 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
187#define CONFIG_SYS_INIT_SP_ADDR \
188 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
189
e856bdcf 190/* environment organization */
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191#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
192#define CONFIG_ENV_SIZE (8 * 1024)
193#define CONFIG_ENV_IS_IN_MMC
194#define CONFIG_SYS_MMC_ENV_DEV 0
195
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196#define CONFIG_CMD_SATA
197#ifdef CONFIG_CMD_SATA
198 #define CONFIG_DWC_AHSATA
199 #define CONFIG_SYS_SATA_MAX_DEVICE 1
200 #define CONFIG_DWC_AHSATA_PORT_ID 0
201 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR
202 #define CONFIG_LBA48
203 #define CONFIG_LIBATA
204#endif
205
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206/* Framebuffer and LCD */
207#define CONFIG_PREBOOT
695af9ab 208#define CONFIG_VIDEO_IPUV3
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209#define CONFIG_VIDEO_BMP_RLE8
210#define CONFIG_SPLASH_SCREEN
211#define CONFIG_BMP_16BPP
212#define CONFIG_VIDEO_LOGO
c606608a 213#define CONFIG_IPUV3_CLK 200000000
f714b0a9 214
938080dc 215#endif /* __CONFIG_H */