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ac7eb8a3 WD |
1 | /* |
2 | * (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl | |
3 | * | |
4 | * Configuation settings for the TI OMAP NetStar board. | |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | ||
25 | #ifndef __CONFIG_H | |
26 | #define __CONFIG_H | |
27 | ||
28 | #include <configs/omap1510.h> | |
29 | ||
30 | /* | |
31 | * High Level Configuration Options | |
32 | * (easy to change) | |
33 | */ | |
34 | #define CONFIG_ARM925T 1 /* This is an arm925t CPU */ | |
35 | #define CONFIG_OMAP 1 /* in a TI OMAP core */ | |
36 | #define CONFIG_OMAP1510 1 /* which is in a 5910 */ | |
37 | ||
38 | /* Input clock of PLL */ | |
39 | #define CONFIG_SYS_CLK_FREQ 150000000 /* 150MHz input clock */ | |
40 | #define CONFIG_XTAL_FREQ 12000000 | |
41 | ||
42 | #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ | |
43 | ||
44 | #define CONFIG_MISC_INIT_R /* There is nothing to really init */ | |
45 | #define BOARD_LATE_INIT /* but we flash the LEDs here */ | |
46 | ||
47 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ | |
48 | #define CONFIG_SETUP_MEMORY_TAGS 1 | |
49 | #define CONFIG_INITRD_TAG 1 | |
50 | ||
ac7eb8a3 | 51 | #define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */ |
6d0f6bcf | 52 | #define CONFIG_SYS_CONSOLE_INFO_QUIET |
ac7eb8a3 WD |
53 | |
54 | /* | |
55 | * Physical Memory Map | |
56 | */ | |
57 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ | |
58 | #define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ | |
f4e7cbfc | 59 | #define PHYS_SDRAM_1_SIZE (64 * 1024 * 1024) |
ac7eb8a3 WD |
60 | #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ |
61 | ||
27057d41 | 62 | #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 |
6d0f6bcf | 63 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) |
ac7eb8a3 WD |
64 | |
65 | /* | |
66 | * Environment settings | |
67 | */ | |
5a1aceb0 | 68 | #define CONFIG_ENV_IS_IN_FLASH |
0e8d1586 JCPV |
69 | #define CONFIG_ENV_ADDR 0x4000 |
70 | #define CONFIG_ENV_SIZE (8 * 1024) | |
71 | #define CONFIG_ENV_SECT_SIZE (8 * 1024) | |
72 | #define CONFIG_ENV_ADDR_REDUND 0x6000 | |
73 | #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE | |
ac7eb8a3 WD |
74 | #define CONFIG_ENV_OVERWRITE |
75 | ||
76 | /* | |
77 | * Size of malloc() pool | |
78 | */ | |
6d0f6bcf JCPV |
79 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
80 | #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) | |
ac7eb8a3 WD |
81 | |
82 | /* | |
83 | * The stack size is set up in start.S using the settings below | |
84 | */ | |
f4e7cbfc | 85 | #define CONFIG_STACKSIZE (1 * 1024 * 1024) /* regular stack */ |
ac7eb8a3 WD |
86 | |
87 | /* | |
88 | * Hardware drivers | |
89 | */ | |
6d0f6bcf JCPV |
90 | #define CONFIG_SYS_NS16550 |
91 | #define CONFIG_SYS_NS16550_SERIAL | |
92 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) | |
93 | #define CONFIG_SYS_NS16550_CLK (CONFIG_XTAL_FREQ) /* can be 12M/32Khz or 48Mhz */ | |
27057d41 LM |
94 | #define CONFIG_SYS_NS16550_COM1 OMAP1510_UART1_BASE /* uart1 */ |
95 | ||
7194ab80 BW |
96 | #define CONFIG_NET_MULTI |
97 | #define CONFIG_SMC91111 | |
27057d41 LM |
98 | #define CONFIG_SMC91111_BASE 0x04000300 |
99 | ||
71f7bd30 LM |
100 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
101 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
102 | #define CONFIG_SYS_MAX_FLASH_SECT 19 | |
103 | ||
104 | #define CONFIG_SYS_FLASH_CFI | |
105 | #define CONFIG_FLASH_CFI_DRIVER | |
106 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT | |
107 | #define CONFIG_FLASH_CFI_LEGACY | |
108 | #define CONFIG_SYS_FLASH_LEGACY_512Kx16 | |
109 | ||
27057d41 LM |
110 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
111 | #define CONFIG_SYS_NAND_BASE 0x04000000 + (2 << 23) | |
112 | #define NAND_ALLOW_ERASE_ALL 1 | |
113 | ||
04531f3c LM |
114 | #define CONFIG_HARD_I2C |
115 | #define CONFIG_SYS_I2C_SPEED 100000 | |
116 | #define CONFIG_SYS_I2C_SLAVE 1 | |
117 | #define CONFIG_DRIVER_OMAP1510_I2C | |
118 | ||
119 | #define CONFIG_RTC_DS1307 | |
120 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
121 | ||
ac7eb8a3 | 122 | |
27057d41 LM |
123 | #define CONFIG_CONS_INDEX 1 |
124 | #define CONFIG_BAUDRATE 115200 | |
6d0f6bcf | 125 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
ac7eb8a3 WD |
126 | |
127 | /*#define CONFIG_SKIP_RELOCATE_UBOOT*/ | |
128 | /*#define CONFIG_SKIP_LOWLEVEL_INIT */ | |
129 | ||
ac7eb8a3 | 130 | /* |
f4e7cbfc | 131 | * partitions (mtdparts command line support) |
ac7eb8a3 | 132 | */ |
68d7d651 | 133 | #define CONFIG_CMD_MTDPARTS |
942556a9 SR |
134 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
135 | #define CONFIG_FLASH_CFI_MTD | |
ac7eb8a3 | 136 | #define MTDIDS_DEFAULT "nor0=omapflash.0,nand0=omapnand.0" |
f4e7cbfc PP |
137 | #define MTDPARTS_DEFAULT "mtdparts=" \ |
138 | "omapflash.0:8k@16k(env),8k(r_env),448k@576k(u-boot);" \ | |
139 | "omapnand.0:4M(kernel0),40M(rootfs0),4M(kernel1),40M(rootfs1),-(data)" | |
ac7eb8a3 | 140 | |
ac7eb8a3 | 141 | |
929a2bfd JL |
142 | /* |
143 | * Command line configuration. | |
144 | */ | |
929a2bfd JL |
145 | #define CONFIG_CMD_BDI |
146 | #define CONFIG_CMD_BOOTD | |
04531f3c | 147 | #define CONFIG_CMD_DATE |
929a2bfd | 148 | #define CONFIG_CMD_DHCP |
bdab39d3 | 149 | #define CONFIG_CMD_SAVEENV |
929a2bfd JL |
150 | #define CONFIG_CMD_FLASH |
151 | #define CONFIG_CMD_IMI | |
929a2bfd JL |
152 | #define CONFIG_CMD_LOADB |
153 | #define CONFIG_CMD_MEMORY | |
154 | #define CONFIG_CMD_NAND | |
155 | #define CONFIG_CMD_NET | |
156 | #define CONFIG_CMD_PING | |
157 | #define CONFIG_CMD_RUN | |
158 | ||
d3b8c1a7 JL |
159 | /* |
160 | * BOOTP options | |
161 | */ | |
162 | #define CONFIG_BOOTP_SUBNETMASK | |
163 | #define CONFIG_BOOTP_GATEWAY | |
164 | #define CONFIG_BOOTP_HOSTNAME | |
165 | #define CONFIG_BOOTP_BOOTPATH | |
166 | ||
ac7eb8a3 WD |
167 | #define CONFIG_LOOPW |
168 | ||
ac7eb8a3 WD |
169 | #define CONFIG_BOOTDELAY 3 |
170 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* allow to break in always */ | |
171 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ | |
6d0f6bcf | 172 | #define CONFIG_SYS_AUTOLOAD "n" /* No autoload */ |
f4e7cbfc | 173 | #define CONFIG_BOOTCOMMAND "run fboot" |
ac7eb8a3 | 174 | #define CONFIG_PREBOOT "run setup" |
de9a1e0d LM |
175 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
176 | "autostart=yes\0" \ | |
177 | "ospart=0\0" \ | |
178 | "setup=setenv bootargs console=ttyS0,$baudrate $mtdparts\0" \ | |
179 | "setpart=" \ | |
180 | "if test -n $swapos; then " \ | |
181 | "setenv swapos; saveenv; " \ | |
182 | "if test $ospart -eq 0; then " \ | |
183 | "setenv ospart 1; " \ | |
184 | "else " \ | |
185 | "setenv ospart 0; " \ | |
186 | "fi; " \ | |
187 | "fi\0" \ | |
188 | "nfsargs=setenv bootargs $bootargs " \ | |
189 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \ | |
190 | "nfsroot=$rootpath root=/dev/nfs\0" \ | |
191 | "flashargs=run setpart;setenv bootargs $bootargs " \ | |
192 | "root=mtd:rootfs$ospart ro " \ | |
193 | "rootfstype=jffs2\0" \ | |
194 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \ | |
195 | "fboot=run flashargs;nboot kernel$ospart\0" \ | |
f4e7cbfc | 196 | "nboot=bootp;run nfsargs;tftp\0" |
ac7eb8a3 WD |
197 | |
198 | #if 0 /* feel free to disable for development */ | |
199 | #define CONFIG_AUTOBOOT_KEYED /* Enable password protection */ | |
f2302d44 SR |
200 | #define CONFIG_AUTOBOOT_PROMPT \ |
201 | "\nNetStar PBX - boot in %d secs...\n", bootdelay | |
f4e7cbfc | 202 | #define CONFIG_AUTOBOOT_DELAY_STR "." /* 1st "password" */ |
ac7eb8a3 WD |
203 | #endif |
204 | ||
205 | /* | |
206 | * Miscellaneous configurable options | |
207 | */ | |
6d0f6bcf JCPV |
208 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
209 | #define CONFIG_SYS_PROMPT "# " /* Monitor Command Prompt */ | |
210 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
211 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
212 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
213 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
214 | ||
215 | #define CONFIG_SYS_HUSH_PARSER | |
216 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
ac7eb8a3 WD |
217 | #define CONFIG_AUTO_COMPLETE |
218 | ||
6d0f6bcf JCPV |
219 | #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 |
220 | #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE - \ | |
221 | (CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_MALLOC_LEN + CONFIG_STACKSIZE) | |
ac7eb8a3 | 222 | |
6d0f6bcf | 223 | #define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1 + 0x400000 /* default load address */ |
ac7eb8a3 | 224 | |
3791a118 | 225 | /* The 1510 has 3 timers, they can be driven by the RefClk (12MHz) or by DPLL1. |
ac7eb8a3 WD |
226 | * This time is further subdivided by a local divisor. |
227 | */ | |
6d0f6bcf | 228 | #define CONFIG_SYS_TIMERBASE OMAP1510_TIMER1_BASE |
3791a118 LM |
229 | #define CONFIG_SYS_PTV 7 |
230 | #define CONFIG_SYS_HZ 1000 | |
ac7eb8a3 WD |
231 | |
232 | #define OMAP5910_DPLL_DIV 1 | |
233 | #define OMAP5910_DPLL_MUL ((CONFIG_SYS_CLK_FREQ * \ | |
234 | (1 << OMAP5910_DPLL_DIV)) / CONFIG_XTAL_FREQ) | |
235 | ||
236 | #define OMAP5910_ARM_PER_DIV 2 /* CKL/4 */ | |
237 | #define OMAP5910_LCD_DIV 2 /* CKL/4 */ | |
238 | #define OMAP5910_ARM_DIV 0 /* CKL/1 */ | |
239 | #define OMAP5910_DSP_DIV 0 /* CKL/1 */ | |
240 | #define OMAP5910_TC_DIV 1 /* CKL/2 */ | |
241 | #define OMAP5910_DSP_MMU_DIV 1 /* CKL/2 */ | |
242 | #define OMAP5910_ARM_TIM_SEL 1 /* CKL used for MPU timers */ | |
243 | ||
244 | #define OMAP5910_ARM_EN_CLK 0x03d6 /* 0000 0011 1101 0110b Clock Enable */ | |
245 | #define OMAP5910_ARM_CKCTL ((OMAP5910_ARM_PER_DIV) | \ | |
246 | (OMAP5910_LCD_DIV << 2) | \ | |
247 | (OMAP5910_ARM_DIV << 4) | \ | |
248 | (OMAP5910_DSP_DIV << 6) | \ | |
249 | (OMAP5910_TC_DIV << 8) | \ | |
250 | (OMAP5910_DSP_MMU_DIV << 10) | \ | |
251 | (OMAP5910_ARM_TIM_SEL << 12)) | |
252 | ||
253 | #endif /* __CONFIG_H */ |