[people/ms/u-boot.git] / include / configs / o2dnt-common.h

/*
 *  Common configuration options for ifm camera boards
 *
 * (C) Copyright 2005
 * Sebastien Cazaux, ifm electronic gmbh
 *
 * (C) Copyright 2012
 * DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __O2D_CONFIG_H
#define __O2D_CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
#define CONFIG_MPC5200

#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* running at 33.000000MHz */

#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
#if defined(CONFIG_CMD_KGDB)
/* log base 2 of the above value */
#define CONFIG_SYS_CACHELINE_SHIFT	5
#endif

/*
#define CONFIG_POST	(CONFIG_SYS_POST_MEMORY | \
			 CONFIG_SYS_POST_I2C)
*/

#ifdef CONFIG_POST
/* preserve space for the post_word at end of on-chip SRAM */
#define MPC5XXX_SRAM_POST_SIZE	(MPC5XXX_SRAM_SIZE - 4)
#endif

/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	5	/* console is on PSC5 */
#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
#define CONFIG_SYS_BAUDRATE_TABLE \
	{ 9600, 19200, 38400, 57600, 115200, 230400 }

/*
 * PCI Mapping:
 * 0x40000000 - 0x4fffffff - PCI Memory
 * 0x50000000 - 0x50ffffff - PCI IO Space
 */
#undef CONFIG_PCI
#define CONFIG_PCI_PNP		1

#define CONFIG_PCI_MEM_BUS	0x40000000
#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE	0x10000000

#define CONFIG_PCI_IO_BUS	0x50000000
#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE	0x01000000

#define CONFIG_SYS_XLB_PIPELINING	1

/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION

#define CONFIG_TIMESTAMP	/* Print image info with timestamp */

#define CONFIG_SYS_ALT_MEMTEST	/* Much more complex memory test */

/*
 * Supported commands
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#ifdef CONFIG_PCI
#define CONFIG_CMD_PCI
#endif
#ifdef CONFIG_POST
#define CONFIG_CMD_DIAG
#endif

#if (CONFIG_SYS_TEXT_BASE == 0xFC000000) || (CONFIG_SYS_TEXT_BASE == 0xFF000000)
/* Boot low with 16 or 32 MB Flash */
#define CONFIG_SYS_LOWBOOT	1
#elif (CONFIG_SYS_TEXT_BASE != 0x00100000)
#error "CONFIG_SYS_TEXT_BASE value is invalid"
#endif

/*
 * Autobooting
 * Be selective on what keys can delay or stop the autoboot process
 * To stop use: "++++++++++"
 */
#define CONFIG_AUTOBOOT_KEYED
#define CONFIG_AUTOBOOT_PROMPT	"Autobooting in %d seconds, " \
				"press password to stop\n", bootdelay
#define CONFIG_AUTOBOOT_STOP_STR	"++++++++++"
#undef CONFIG_AUTOBOOT_DELAY_STR
#define DEBUG_BOOTKEYS		0

#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */

#define CONFIG_PREBOOT	"run master"

#undef	CONFIG_BOOTARGS

#define xstr(s) str(s)
#define str(s)  #s

#if !defined(CONFIG_CONSOLE_DEV)
#define CONFIG_CONSOLE_DEV	"ttyPSC1"
#endif

/*
 * Default environment for booting old and new kernel versions
 */
#define CONFIG_IFM_DEFAULT_ENV_OLD					\
	"flash_self_old=run ramargs addip addmem;"			\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"flash_nfs_old=run nfsargs addip addmem;"			\
		"bootm ${kernel_addr}\0"				\
	"net_nfs_old=tftp ${kernel_addr_r} ${bootfile};"		\
		"run nfsargs addip addmem;"				\
		"bootm ${kernel_addr_r}\0"

#define CONFIG_IFM_DEFAULT_ENV_NEW					\
	"fdt_addr_r=900000\0"						\
	"fdt_file="CONFIG_BOARD_NAME"/"CONFIG_BOARD_NAME".dtb\0"	\
	"flash_self=run ramargs addip addtty addmisc;"			\
		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
	"flash_nfs=run nfsargs addip addtty addmisc;"			\
		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
		"tftp ${fdt_addr_r} ${fdt_file}; "			\
		"run nfsargs addip addtty addmisc;"			\
		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\

#define	CONFIG_IFM_DEFAULT_ENV_SETTINGS					\
	"IOpin=0x64\0"							\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addmem=setenv bootargs ${bootargs} ${memlimit}\0"		\
	"addmisc=sete bootargs ${bootargs} ${miscargs}\0"		\
	"addtty=sete bootargs ${bootargs} console="			\
		CONFIG_CONSOLE_DEV ",${baudrate}\0"			\
	"bootfile="CONFIG_BOARD_NAME"/uImage_"CONFIG_BOARD_NAME"_act\0"	\
	"kernel_addr_r=600000\0"					\
	"initrd_high=0x03e00000\0"					\
	"memlimit=mem="CONFIG_BOARD_MEM_LIMIT"M\0"			\
	"memtest=mtest 0x00100000 "xstr(CONFIG_SYS_MEMTEST_END)" 0 1\0"	\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"linuxname="CONFIG_BOARD_NAME"/uImage_"CONFIG_BOARD_NAME"_act\0"\
	"progLinux=tftp 200000 ${linuxname};erase ${linbot} ${lintop};" \
		"cp.b ${fileaddr} ${linbot} ${filesize}\0"		\
	"ramname="CONFIG_BOARD_NAME"/uRamdisk_"CONFIG_BOARD_NAME"_act\0"\
	"progRam=tftp 200000 ${ramname};erase ${rambot} ${ramtop};"	\
		"cp.b ${fileaddr} ${rambot} ${filesize}\0"		\
	"jffname="CONFIG_BOARD_NAME"/uJFFS2_"CONFIG_BOARD_NAME"_act\0"	\
	"progJff=tftp 200000 ${jffname};erase ${jffbot} ${jfftop};"	\
		"cp.b ${fileaddr} ${jffbot} ${filesize}\0"		\
	"rootpath=/opt/eldk/ppc_6xx\0"					\
	"uboname=" CONFIG_BOARD_NAME					\
		"/u-boot.bin_" CONFIG_BOARD_NAME "_act\0"		\
	"progubo=tftp 200000 ${uboname};"				\
		"protect off ${ubobot} ${ubotop};"			\
		"erase ${ubobot} ${ubotop};"				\
		"cp.b ${fileaddr} ${ubobot} ${filesize}\0"		\
	"unlock=yes\0"							\
	"post=echo !!! "CONFIG_BOARD_NAME" POWER ON SELF TEST !!!;"	\
		"setenv bootdelay 1;"					\
		"crc32 "xstr(CONFIG_SYS_TEXT_BASE)" "			\
			BOARD_POST_CRC32_END";"				\
		"setenv bootcmd "CONFIG_BOARD_BOOTCMD";saveenv;reset\0"

#define CONFIG_BOOTCOMMAND	"run post"

/*
 * IPB Bus clocking configuration.
 */
#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */

#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
/*
 * PCI Bus clocking configuration
 *
 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
 * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
 * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
 */
#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2	/* define for 66MHz speed */
#endif

/*
 * I2C configuration
 */
#define CONFIG_HARD_I2C			1	/* I2C with hardware support */
#define CONFIG_SYS_I2C_MODULE		1	/* Select I2C module #1 or #2 */
#define CONFIG_SYS_I2C_SPEED		100000	/* 100 kHz */
#define CONFIG_SYS_I2C_SLAVE		0x7F

/*
 * EEPROM configuration:
 *
 * O2DNT board is equiped with Ramtron FRAM device FM24CL16
 * 16 Kib Ferroelectric Nonvolatile serial RAM memory
 * organized as 2048 x 8 bits and addressable as eight I2C devices
 * 0x50 ... 0x57 each 256 bytes in size
 *
 */
#define CONFIG_SYS_I2C_FRAM
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
/*
 * There is no write delay with FRAM, write operations are performed at bus
 * speed. Thus, no status polling or write delay is needed.
 */

/*
 * Flash configuration
 */
#define CONFIG_SYS_FLASH_CFI		1
#define CONFIG_FLASH_CFI_DRIVER		1
#define CONFIG_FLASH_16BIT
#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
#define CONFIG_SYS_FLASH_CFI_AMD_RESET
#define CONFIG_SYS_FLASH_EMPTY_INFO

#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks */
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Erase Timeout (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Write Timeout (in ms) */
/* Timeout for Flash Clear Lock Bits (in ms) */
#define CONFIG_SYS_FLASH_UNLOCK_TOUT	10000
/* "Real" (hardware) sectors protection */
#define CONFIG_SYS_FLASH_PROTECTION

/*
 * Environment settings
 */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_SIZE		0x20000
#define CONFIG_ENV_SECT_SIZE	0x20000
#define CONFIG_ENV_OVERWRITE	1
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00040000)

/*
 * Memory map
 */
#define CONFIG_SYS_MBAR		0xF0000000
#define CONFIG_SYS_SDRAM_BASE	0x00000000
#define CONFIG_SYS_DEFAULT_MBAR	0x80000000

/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
#ifdef CONFIG_POST
/* preserve space for the post_word at end of on-chip SRAM */
#define CONFIG_SYS_INIT_RAM_END		MPC5XXX_SRAM_POST_SIZE
#else
/* End of used area in DPRAM */
#define CONFIG_SYS_INIT_RAM_END		MPC5XXX_SRAM_SIZE
#endif

/* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_SIZE	128
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - \
					 CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN		(192 << 10) /* 192 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN		(128 << 10) /* 128 kB for malloc() */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)   /* Initial map for Linux */

#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT		1
#endif

/*
 * Ethernet configuration
 */
#define CONFIG_MPC5xxx_FEC
#define CONFIG_MPC5xxx_FEC_MII100
#define CONFIG_PHY_ADDR			0x00
#define CONFIG_RESET_PHY_R

/*
 * GPIO configuration
 */
#define CONFIG_SYS_GPIO_DATADIR		0x00000064 /* PSC1_2, PSC2_1,2 output */
#define CONFIG_SYS_GPIO_OPENDRAIN	0x00000000 /* No open drain */
#define CONFIG_SYS_GPIO_DATAVALUE	0x00000000 /* PSC1_1 to 1, rest to 0 */
#define CONFIG_SYS_GPIO_ENABLE		0x00000064 /* PSC1_2, PSC2_1,2 enable */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_HUSH_PARSER

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
#else
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
#endif
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					 sizeof(CONFIG_SYS_PROMPT) + 16)
/* max number of command args */
#define CONFIG_SYS_MAXARGS		16
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE

/* default load address */
#define CONFIG_SYS_LOAD_ADDR		0x100000

/* decrementer freq: 1 ms ticks */

/*
 * Various low-level settings
 */
#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL		HID0_ICE

#define CONFIG_SYS_BOOTCS_START		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE

#define CONFIG_BOARD_EARLY_INIT_R

#define CONFIG_SYS_CS_BURST		0x00000000
#define CONFIG_SYS_CS_DEADCYCLE		0x33333333

/*
 * DT support
 */
#define CONFIG_OF_LIBFDT	1
#define CONFIG_OF_BOARD_SETUP	1

#define OF_CPU			"PowerPC,5200@0"
#define OF_SOC			"soc5200@f0000000"
#define OF_TBCLK		(bd->bi_busfreq / 4)

#endif /* __O2D_CONFIG_H */
Commit	Line	Data
4387cf1a AG	1	/*
	2	* Common configuration options for ifm camera boards
	3	*
	4	* (C) Copyright 2005
	5	* Sebastien Cazaux, ifm electronic gmbh
	6	*
	7	* (C) Copyright 2012
	8	* DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
	9	*
3765b3e7	10	* SPDX-License-Identifier: GPL-2.0+
4387cf1a AG	11	*/
	12
	13	#ifndef __O2D_CONFIG_H
	14	#define __O2D_CONFIG_H
	15
	16	/*
	17	* High Level Configuration Options
	18	*/
	19	#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
	20	#define CONFIG_MPC5200
	21
	22	#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* running at 33.000000MHz */
	23
	24	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
	25	#if defined(CONFIG_CMD_KGDB)
	26	/* log base 2 of the above value */
	27	#define CONFIG_SYS_CACHELINE_SHIFT 5
	28	#endif
	29
	30	/*
	31	#define CONFIG_POST (CONFIG_SYS_POST_MEMORY \| \
	32	CONFIG_SYS_POST_I2C)
	33	*/
	34
	35	#ifdef CONFIG_POST
	36	/* preserve space for the post_word at end of on-chip SRAM */
	37	#define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4)
	38	#endif
	39
	40	/*
	41	* Serial console configuration
	42	*/
	43	#define CONFIG_PSC_CONSOLE 5 /* console is on PSC5 */
	44	#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
	45	#define CONFIG_SYS_BAUDRATE_TABLE \
	46	{ 9600, 19200, 38400, 57600, 115200, 230400 }
	47
	48	/*
	49	* PCI Mapping:
	50	* 0x40000000 - 0x4fffffff - PCI Memory
	51	* 0x50000000 - 0x50ffffff - PCI IO Space
	52	*/
	53	#undef CONFIG_PCI
	54	#define CONFIG_PCI_PNP 1
	55
	56	#define CONFIG_PCI_MEM_BUS 0x40000000
	57	#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
	58	#define CONFIG_PCI_MEM_SIZE 0x10000000
	59
	60	#define CONFIG_PCI_IO_BUS 0x50000000
	61	#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
	62	#define CONFIG_PCI_IO_SIZE 0x01000000
	63
	64	#define CONFIG_SYS_XLB_PIPELINING 1
	65
	66	/* Partitions */
	67	#define CONFIG_MAC_PARTITION
	68	#define CONFIG_DOS_PARTITION
	69	#define CONFIG_ISO_PARTITION
	70
	71	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
	72
	73	#define CONFIG_SYS_ALT_MEMTEST /* Much more complex memory test */
	74
75	/*
76	* Supported commands
77	*/
78	#include <config_cmd_default.h>
79
80	#define CONFIG_CMD_EEPROM
81	#define CONFIG_CMD_FAT
82	#define CONFIG_CMD_I2C
83	#define CONFIG_CMD_MII
84	#define CONFIG_CMD_PING
85	#define CONFIG_CMD_DHCP
86	#ifdef CONFIG_PCI
87	#define CONFIG_CMD_PCI
88	#endif
89	#ifdef CONFIG_POST
90	#define CONFIG_CMD_DIAG
91	#endif
92
93	#if (CONFIG_SYS_TEXT_BASE == 0xFC000000) \|\| (CONFIG_SYS_TEXT_BASE == 0xFF000000)
94	/* Boot low with 16 or 32 MB Flash */
95	#define CONFIG_SYS_LOWBOOT 1
96	#elif (CONFIG_SYS_TEXT_BASE != 0x00100000)
97	#error "CONFIG_SYS_TEXT_BASE value is invalid"
98	#endif
99
100	/*
101	* Autobooting
102	* Be selective on what keys can delay or stop the autoboot process
103	* To stop use: "++++++++++"
104	*/
105	#define CONFIG_AUTOBOOT_KEYED
106	#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, " \
107	"press password to stop\n", bootdelay
108	#define CONFIG_AUTOBOOT_STOP_STR "++++++++++"
109	#undef CONFIG_AUTOBOOT_DELAY_STR
110	#define DEBUG_BOOTKEYS 0
111
112	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
113
114	#define CONFIG_PREBOOT "run master"
115
116	#undef CONFIG_BOOTARGS
117
118	#define xstr(s) str(s)
119	#define str(s) #s
120
121	#if !defined(CONFIG_CONSOLE_DEV)
122	#define CONFIG_CONSOLE_DEV "ttyPSC1"
123	#endif
124
125	/*
126	* Default environment for booting old and new kernel versions
127	*/
128	#define CONFIG_IFM_DEFAULT_ENV_OLD \
129	"flash_self_old=run ramargs addip addmem;" \
130	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
131	"flash_nfs_old=run nfsargs addip addmem;" \
132	"bootm ${kernel_addr}\0" \
133	"net_nfs_old=tftp ${kernel_addr_r} ${bootfile};" \
134	"run nfsargs addip addmem;" \
135	"bootm ${kernel_addr_r}\0"
136
137	#define CONFIG_IFM_DEFAULT_ENV_NEW \
138	"fdt_addr_r=900000\0" \
139	"fdt_file="CONFIG_BOARD_NAME"/"CONFIG_BOARD_NAME".dtb\0" \
140	"flash_self=run ramargs addip addtty addmisc;" \
141	"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
142	"flash_nfs=run nfsargs addip addtty addmisc;" \
143	"bootm ${kernel_addr} - ${fdt_addr}\0" \
144	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
145	"tftp ${fdt_addr_r} ${fdt_file}; " \
146	"run nfsargs addip addtty addmisc;" \
147	"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
148
149	#define CONFIG_IFM_DEFAULT_ENV_SETTINGS \
150	"IOpin=0x64\0" \
151	"addip=setenv bootargs ${bootargs} " \
152	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
153	":${hostname}:${netdev}:off panic=1\0" \
154	"addmem=setenv bootargs ${bootargs} ${memlimit}\0" \
155	"addmisc=sete bootargs ${bootargs} ${miscargs}\0" \
156	"addtty=sete bootargs ${bootargs} console=" \
157	CONFIG_CONSOLE_DEV ",${baudrate}\0" \
158	"bootfile="CONFIG_BOARD_NAME"/uImage_"CONFIG_BOARD_NAME"_act\0" \
159	"kernel_addr_r=600000\0" \
160	"initrd_high=0x03e00000\0" \
161	"memlimit=mem="CONFIG_BOARD_MEM_LIMIT"M\0" \
162	"memtest=mtest 0x00100000 "xstr(CONFIG_SYS_MEMTEST_END)" 0 1\0" \
163	"netdev=eth0\0" \
164	"nfsargs=setenv bootargs root=/dev/nfs rw " \
165	"nfsroot=${serverip}:${rootpath}\0" \
166	"ramargs=setenv bootargs root=/dev/ram rw\0" \
167	"linuxname="CONFIG_BOARD_NAME"/uImage_"CONFIG_BOARD_NAME"_act\0"\
168	"progLinux=tftp 200000 ${linuxname};erase ${linbot} ${lintop};" \
169	"cp.b ${fileaddr} ${linbot} ${filesize}\0" \
170	"ramname="CONFIG_BOARD_NAME"/uRamdisk_"CONFIG_BOARD_NAME"_act\0"\
171	"progRam=tftp 200000 ${ramname};erase ${rambot} ${ramtop};" \
172	"cp.b ${fileaddr} ${rambot} ${filesize}\0" \
173	"jffname="CONFIG_BOARD_NAME"/uJFFS2_"CONFIG_BOARD_NAME"_act\0" \
174	"progJff=tftp 200000 ${jffname};erase ${jffbot} ${jfftop};" \
175	"cp.b ${fileaddr} ${jffbot} ${filesize}\0" \
176	"rootpath=/opt/eldk/ppc_6xx\0" \
177	"uboname=" CONFIG_BOARD_NAME \
178	"/u-boot.bin_" CONFIG_BOARD_NAME "_act\0" \
179	"progubo=tftp 200000 ${uboname};" \
180	"protect off ${ubobot} ${ubotop};" \
181	"erase ${ubobot} ${ubotop};" \
182	"cp.b ${fileaddr} ${ubobot} ${filesize}\0" \
183	"unlock=yes\0" \
184	"post=echo !!! "CONFIG_BOARD_NAME" POWER ON SELF TEST !!!;" \
185	"setenv bootdelay 1;" \
186	"crc32 "xstr(CONFIG_SYS_TEXT_BASE)" " \
187	BOARD_POST_CRC32_END";" \
188	"setenv bootcmd "CONFIG_BOARD_BOOTCMD";saveenv;reset\0"
189
190	#define CONFIG_BOOTCOMMAND "run post"
191
192	/*
193	* IPB Bus clocking configuration.
194	*/
195	#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
196
197	#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
198	/*
199	* PCI Bus clocking configuration
200	*
201	* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
202	* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
203	* of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
204	*/
205	#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
206	#endif
207
208	/*
209	* I2C configuration
210	*/
211	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
212	#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 or #2 */
213	#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
214	#define CONFIG_SYS_I2C_SLAVE 0x7F
215
216	/*
217	* EEPROM configuration:
218	*
219	* O2DNT board is equiped with Ramtron FRAM device FM24CL16
220	* 16 Kib Ferroelectric Nonvolatile serial RAM memory
221	* organized as 2048 x 8 bits and addressable as eight I2C devices
222	* 0x50 ... 0x57 each 256 bytes in size
223	*
224	*/
225	#define CONFIG_SYS_I2C_FRAM
226	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
227	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
228	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
229	/*
230	* There is no write delay with FRAM, write operations are performed at bus
231	* speed. Thus, no status polling or write delay is needed.
232	*/
233
234	/*
235	* Flash configuration
236	*/
237	#define CONFIG_SYS_FLASH_CFI 1
238	#define CONFIG_FLASH_CFI_DRIVER 1
239	#define CONFIG_FLASH_16BIT
240	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
241	#define CONFIG_SYS_FLASH_CFI_AMD_RESET
242	#define CONFIG_SYS_FLASH_EMPTY_INFO
243
244	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
245	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
246	#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Erase Timeout (in ms) */
247	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (in ms) */
248	/* Timeout for Flash Clear Lock Bits (in ms) */
249	#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000
250	/* "Real" (hardware) sectors protection */
251	#define CONFIG_SYS_FLASH_PROTECTION
252
253	/*
254	* Environment settings
255	*/
256	#define CONFIG_ENV_IS_IN_FLASH 1
257	#define CONFIG_ENV_SIZE 0x20000
258	#define CONFIG_ENV_SECT_SIZE 0x20000
259	#define CONFIG_ENV_OVERWRITE 1
260	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
261
262	/*
263	* Memory map
264	*/
265	#define CONFIG_SYS_MBAR 0xF0000000
266	#define CONFIG_SYS_SDRAM_BASE 0x00000000
267	#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
268
269	/* Use SRAM until RAM will be available */
270	#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
271	#ifdef CONFIG_POST
272	/* preserve space for the post_word at end of on-chip SRAM */
273	#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
274	#else
275	/* End of used area in DPRAM */
276	#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
277	#endif
278
279	/* size in bytes reserved for initial data */
280	#define CONFIG_SYS_GBL_DATA_SIZE 128
281	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
282	CONFIG_SYS_GBL_DATA_SIZE)
283	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
284
285	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
286	#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* 192 kB for Monitor */
287	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* 128 kB for malloc() */
288	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial map for Linux */
289
290	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
291	#define CONFIG_SYS_RAMBOOT 1
292	#endif
293
294	/*
295	* Ethernet configuration
296	*/
297	#define CONFIG_MPC5xxx_FEC
298	#define CONFIG_MPC5xxx_FEC_MII100
299	#define CONFIG_PHY_ADDR 0x00
300	#define CONFIG_RESET_PHY_R
301
302	/*
303	* GPIO configuration
304	*/
305	#define CONFIG_SYS_GPIO_DATADIR 0x00000064 /* PSC1_2, PSC2_1,2 output */
306	#define CONFIG_SYS_GPIO_OPENDRAIN 0x00000000 /* No open drain */
307	#define CONFIG_SYS_GPIO_DATAVALUE 0x00000000 /* PSC1_1 to 1, rest to 0 */
308	#define CONFIG_SYS_GPIO_ENABLE 0x00000064 /* PSC1_2, PSC2_1,2 enable */
309
310	/*
311	* Miscellaneous configurable options
312	*/
313	#define CONFIG_SYS_LONGHELP /* undef to save memory */
4387cf1a AG	314	#define CONFIG_CMDLINE_EDITING
	315	#define CONFIG_SYS_HUSH_PARSER
	316
	317	#if defined(CONFIG_CMD_KGDB)
	318	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
	319	#else
	320	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	321	#endif
	322	/* Print Buffer Size */
	323	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	324	sizeof(CONFIG_SYS_PROMPT) + 16)
	325	/* max number of command args */
	326	#define CONFIG_SYS_MAXARGS 16
	327	/* Boot Argument Buffer Size */
	328	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	329
	330	/* default load address */
	331	#define CONFIG_SYS_LOAD_ADDR 0x100000
	332
	333	/* decrementer freq: 1 ms ticks */
4387cf1a AG	334
	335	/*
	336	* Various low-level settings
	337	*/
	338	#define CONFIG_SYS_HID0_INIT HID0_ICE \| HID0_ICFI
	339	#define CONFIG_SYS_HID0_FINAL HID0_ICE
	340
	341	#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
	342	#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
	343	#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
	344	#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
	345
	346	#define CONFIG_BOARD_EARLY_INIT_R
	347
	348	#define CONFIG_SYS_CS_BURST 0x00000000
	349	#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
	350
	351	/*
	352	* DT support
	353	*/
	354	#define CONFIG_OF_LIBFDT 1
	355	#define CONFIG_OF_BOARD_SETUP 1
	356
	357	#define OF_CPU "PowerPC,5200@0"
	358	#define OF_SOC "soc5200@f0000000"
	359	#define OF_TBCLK (bd->bi_busfreq / 4)
	360
	361	#endif /* __O2D_CONFIG_H */