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Commit | Line | Data |
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2be2c6cc | 1 | /* |
73225245 GI |
2 | * (C) Copyright 2008-2010 |
3 | * GraÅžvydas Ignotas <notasas@gmail.com> | |
2be2c6cc DB |
4 | * |
5 | * Configuration settings for the OMAP3 Pandora. | |
6 | * | |
3765b3e7 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
2be2c6cc DB |
8 | */ |
9 | ||
10 | #ifndef __CONFIG_H | |
11 | #define __CONFIG_H | |
2be2c6cc | 12 | |
76375454 GI |
13 | #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ |
14 | #define CONFIG_NAND | |
2be2c6cc | 15 | |
76375454 GI |
16 | /* override base for compatibility with MLO the device ships with */ |
17 | #define CONFIG_SYS_TEXT_BASE 0x80008000 | |
cae377b5 | 18 | |
76375454 | 19 | #include <configs/ti_omap3_common.h> |
2be2c6cc | 20 | |
2be2c6cc | 21 | #define CONFIG_MISC_INIT_R |
2be2c6cc DB |
22 | #define CONFIG_REVISION_TAG 1 |
23 | ||
9c44ddcc | 24 | #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ |
76375454 | 25 | |
76375454 | 26 | #define CONFIG_SYS_DEVICE_NULLDEV 1 |
2be2c6cc DB |
27 | |
28 | /* | |
29 | * Hardware drivers | |
30 | */ | |
31 | ||
76375454 GI |
32 | /* I2C Support */ |
33 | #define CONFIG_SYS_I2C_OMAP34XX | |
73225245 | 34 | |
76375454 GI |
35 | /* TWL4030 LED */ |
36 | #define CONFIG_TWL4030_LED | |
73225245 | 37 | |
76375454 GI |
38 | /* Initialize GPIOs by default */ |
39 | #define CONFIG_OMAP3_GPIO_4 /* GPIO96..127 is in GPIO Bank 4 */ | |
40 | #define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO Bank 6 */ | |
73225245 | 41 | |
2be2c6cc DB |
42 | /* |
43 | * NS16550 Configuration | |
44 | */ | |
c7b9686d | 45 | #undef CONFIG_SYS_NS16550_CLK |
2be2c6cc DB |
46 | #define CONFIG_SYS_NS16550_SERIAL |
47 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) | |
48 | #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK | |
2be2c6cc DB |
49 | #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 |
50 | #define CONFIG_SERIAL3 3 | |
51 | ||
2be2c6cc | 52 | /* commands to include */ |
2be2c6cc | 53 | |
2be2c6cc DB |
54 | /* |
55 | * Board NAND Info. | |
56 | */ | |
2be2c6cc DB |
57 | #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ |
58 | /* to access nand */ | |
55f1b39f | 59 | #define CONFIG_SYS_NAND_BUSWIDTH_16BIT |
76375454 GI |
60 | #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW |
61 | #define CONFIG_SYS_NAND_PAGE_SIZE 2048 | |
62 | #define CONFIG_SYS_NAND_OOBSIZE 64 | |
63 | ||
64 | #ifdef CONFIG_NAND | |
76375454 GI |
65 | #define CONFIG_CMD_UBIFS /* Read-only UBI volume operations */ |
66 | ||
67 | #define CONFIG_RBTREE /* required by CONFIG_CMD_UBI */ | |
68 | #define CONFIG_LZO /* required by CONFIG_CMD_UBIFS */ | |
69 | ||
70 | #define CONFIG_MTD_PARTITIONS /* required for UBI partition support */ | |
71 | ||
72 | #define MTDIDS_DEFAULT "nand0=omap2-nand.0" | |
73 | #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(xloader),"\ | |
73225245 GI |
74 | "1920k(uboot),128k(uboot-env),"\ |
75 | "10m(boot),-(rootfs)" | |
76 | #else | |
77 | #define MTDPARTS_DEFAULT | |
78 | #endif | |
2be2c6cc | 79 | |
2be2c6cc DB |
80 | |
81 | #define CONFIG_BOOTCOMMAND \ | |
40abfeec | 82 | "run distro_bootcmd; " \ |
db18a24f | 83 | "setenv bootargs ${bootargs_ubi}; " \ |
4667c833 | 84 | "if mmc rescan && load mmc 0:1 ${loadaddr} autoboot.scr; then " \ |
73225245 GI |
85 | "source ${loadaddr}; " \ |
86 | "fi; " \ | |
949a7710 JH |
87 | "ubi part boot && ubifsmount ubi:boot && " \ |
88 | "ubifsload ${loadaddr} uImage && bootm ${loadaddr}" | |
2be2c6cc | 89 | |
40abfeec VC |
90 | #define BOOT_TARGET_DEVICES(func) \ |
91 | func(MMC, mmc, 0) \ | |
92 | ||
93 | #include <config_distro_bootcmd.h> | |
94 | ||
95 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
96 | DEFAULT_LINUX_BOOT_ENV \ | |
97 | "usbtty=cdc_acm\0" \ | |
db18a24f | 98 | "bootargs_ubi=ubi.mtd=4 ubi.mtd=3 root=ubi0:rootfs rootfstype=ubifs " \ |
40abfeec VC |
99 | "rw rootflags=bulk_read vram=6272K omapfb.vram=0:3000K\0" \ |
100 | "mtdparts=" MTDPARTS_DEFAULT "\0" \ | |
101 | BOOTENV \ | |
102 | ||
2be2c6cc DB |
103 | /* memtest works on */ |
104 | #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) | |
105 | #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ | |
106 | 0x01F00000) /* 31MB */ | |
107 | ||
76375454 | 108 | #if defined(CONFIG_NAND) |
222a3113 | 109 | #define CONFIG_SYS_FLASH_BASE NAND_BASE |
6cbec7b3 | 110 | #endif |
2be2c6cc DB |
111 | |
112 | /* Monitor at start of flash */ | |
113 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
2be2c6cc DB |
114 | |
115 | #define CONFIG_ENV_IS_IN_NAND 1 | |
73225245 | 116 | #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ |
2be2c6cc | 117 | |
6cbec7b3 LC |
118 | #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ |
119 | #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET | |
2be2c6cc DB |
120 | #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET |
121 | ||
2be2c6cc | 122 | #endif /* __CONFIG_H */ |