[people/ms/u-boot.git] / include / configs / omap3_zoom1.h

/*
 * (C) Copyright 2006-2008
 * Texas Instruments.
 * Richard Woodruff <r-woodruff2@ti.com>
 * Syed Mohammed Khasim <x0khasim@ti.com>
 * Nishanth Menon <nm@ti.com>
 *
 * Configuration settings for the TI OMAP3430 Zoom MDK board.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_OMAP		1	/* in a TI OMAP core */
#define CONFIG_OMAP34XX		1	/* which is a 34XX */
#define CONFIG_OMAP3_ZOOM1	1	/* working with Zoom MDK Rev1 */
#define CONFIG_OMAP_COMMON

#define CONFIG_SDRC	/* The chip has SDRC controller */

#include <asm/arch/cpu.h>		/* get chip and board defs */
#include <asm/arch/omap3.h>

/*
 * Display CPU and Board information
 */
#define CONFIG_DISPLAY_CPUINFO		1
#define CONFIG_DISPLAY_BOARDINFO	1

/* Clock Defines */
#define V_OSCK			26000000	/* Clock output from T2 */
#define V_SCLK			(V_OSCK >> 1)

#define CONFIG_MISC_INIT_R

#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS	1
#define CONFIG_INITRD_TAG		1
#define CONFIG_REVISION_TAG		1

#define CONFIG_OF_LIBFDT		1

/*
 * Size of malloc() pool
 */
#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
						/* Sector */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))

/*
 * Hardware drivers
 */

/*
 * NS16550 Configuration
 */
#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */

#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK

/*
 * select serial console configuration
 */
#define CONFIG_CONS_INDEX		3
#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
#define CONFIG_SERIAL3			3	/* UART3 */

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
					115200}
#define CONFIG_GENERIC_MMC		1
#define CONFIG_MMC			1
#define CONFIG_OMAP_HSMMC		1
#define CONFIG_DOS_PARTITION		1

/* USB */
#define CONFIG_MUSB_UDC			1
#define CONFIG_USB_OMAP3		1
#define CONFIG_TWL4030_USB		1

/* USB device configuration */
#define CONFIG_USB_DEVICE		1
#define CONFIG_USB_TTY			1
#define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
/* Change these to suit your needs */
#define CONFIG_USBD_VENDORID		0x0451
#define CONFIG_USBD_PRODUCTID		0x5678
#define CONFIG_USBD_MANUFACTURER	"Texas Instruments"
#define CONFIG_USBD_PRODUCT_NAME	"Zoom1"

/* commands to include */
#include <config_cmd_default.h>

#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
#define CONFIG_CMD_FAT		/* FAT support			*/
#define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/

#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
#define CONFIG_CMD_MMC		/* MMC support			*/
#define CONFIG_CMD_NAND		/* NAND support			*/
#define CONFIG_CMD_NAND_LOCK_UNLOCK /* Enable lock/unlock support */

#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
#undef CONFIG_CMD_IMI		/* iminfo			*/
#undef CONFIG_CMD_IMLS		/* List all found images	*/
#undef CONFIG_CMD_NET		/* bootp, tftpboot, rarpboot	*/
#undef CONFIG_CMD_NFS		/* NFS support			*/

#define CONFIG_SYS_NO_FLASH
#define CONFIG_HARD_I2C			1
#define CONFIG_SYS_I2C_SPEED		100000
#define CONFIG_SYS_I2C_SLAVE		1
#define CONFIG_DRIVER_OMAP34XX_I2C	1

/*
 * TWL4030
 */
#define CONFIG_TWL4030_POWER		1
#define CONFIG_TWL4030_LED		1

/*
 * Board NAND Info.
 */
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
							/* to access nand */
#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
							/* to access nand at */
							/* CS0 */
#define GPMC_NAND_ECC_LP_x16_LAYOUT	1

#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
							/* devices */
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV		"nand0"
/* start of jffs2 partition */
#define CONFIG_JFFS2_PART_OFFSET	0x680000
#define CONFIG_JFFS2_PART_SIZE		0xf980000	/* size of jffs2 */
							/* partition */

/* Environment information */
#define CONFIG_BOOTDELAY		10

#define CONFIG_EXTRA_ENV_SETTINGS \
	"loadaddr=0x82000000\0" \
	"usbtty=cdc_acm\0" \
	"console=ttyS2,115200n8\0" \
	"mmcdev=0\0" \
	"videomode=1024x768@60,vxres=1024,vyres=768\0" \
	"videospec=omapfb:vram:2M,vram:4M\0" \
	"mmcargs=setenv bootargs console=${console} " \
		"video=${videospec},mode:${videomode} " \
		"root=/dev/mmcblk0p2 rw " \
		"rootfstype=ext3 rootwait\0" \
	"nandargs=setenv bootargs console=${console} " \
		"video=${videospec},mode:${videomode} " \
		"root=/dev/mtdblock4 rw " \
		"rootfstype=jffs2\0" \
	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
	"bootscript=echo Running bootscript from mmc ...; " \
		"source ${loadaddr}\0" \
	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
	"mmcboot=echo Booting from mmc ...; " \
		"run mmcargs; " \
		"bootm ${loadaddr}\0" \
	"nandboot=echo Booting from nand ...; " \
		"run nandargs; " \
		"nand read ${loadaddr} 280000 400000; " \
		"bootm ${loadaddr}\0" \

#define CONFIG_BOOTCOMMAND \
	"mmc dev ${mmcdev}; if mmc rescan; then " \
		"if run loadbootscript; then " \
			"run bootscript; " \
		"else " \
			"if run loaduimage; then " \
				"run mmcboot; " \
			"else run nandboot; " \
			"fi; " \
		"fi; " \
	"else run nandboot; fi"

#define CONFIG_AUTO_COMPLETE		1
/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
#define CONFIG_SYS_PROMPT		"OMAP3 Zoom1 # "
#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)

#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)	/* memtest */
								/* works on */
#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
					0x01F00000) /* 31MB */

#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0)	/* default */
							/* load address */

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE	0x800
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - \
					 GENERATED_GBL_DATA_SIZE)
/*
 * OMAP3 has 12 GP timers, they can be driven by the system clock
 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 * This rate is divided by a local divisor.
 */
#define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */

/* **** PISMO SUPPORT *** */

/* Configure the PISMO */
#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M

#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */

#if defined(CONFIG_CMD_NAND)
#define CONFIG_SYS_FLASH_BASE		PISMO1_NAND_BASE
#endif

/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP

#define CONFIG_ENV_IS_IN_NAND		1
#define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */

#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET

#define CONFIG_SYS_CACHELINE_SIZE	64

#endif				/* __CONFIG_H */
Commit	Line	Data
7379f45a DB	1	/*
	2	* (C) Copyright 2006-2008
	3	* Texas Instruments.
	4	* Richard Woodruff <r-woodruff2@ti.com>
	5	* Syed Mohammed Khasim <x0khasim@ti.com>
	6	* Nishanth Menon <nm@ti.com>
	7	*
	8	* Configuration settings for the TI OMAP3430 Zoom MDK board.
	9	*
3765b3e7	10	* SPDX-License-Identifier: GPL-2.0+
7379f45a DB	11	*/
	12
	13	#ifndef __CONFIG_H
	14	#define __CONFIG_H
7379f45a DB	15
	16	/*
	17	* High Level Configuration Options
	18	*/
7379f45a DB	19	#define CONFIG_OMAP 1 /* in a TI OMAP core */
7379f45a DB	20	#define CONFIG_OMAP34XX 1 /* which is a 34XX */
7379f45a	21	#define CONFIG_OMAP3_ZOOM1 1 /* working with Zoom MDK Rev1 */
806d2792	22	#define CONFIG_OMAP_COMMON
7379f45a	23
cae377b5 VH	24	#define CONFIG_SDRC /* The chip has SDRC controller */
cae377b5 VH	25
7379f45a DB	26	#include <asm/arch/cpu.h> /* get chip and board defs */
	27	#include <asm/arch/omap3.h>
	28
6a6b62e3 SP	29	/*
	30	* Display CPU and Board information
	31	*/
	32	#define CONFIG_DISPLAY_CPUINFO 1
	33	#define CONFIG_DISPLAY_BOARDINFO 1
	34
7379f45a DB	35	/* Clock Defines */
	36	#define V_OSCK 26000000 /* Clock output from T2 */
	37	#define V_SCLK (V_OSCK >> 1)
	38
7379f45a DB	39	#define CONFIG_MISC_INIT_R
	40
	41	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
	42	#define CONFIG_SETUP_MEMORY_TAGS 1
	43	#define CONFIG_INITRD_TAG 1
	44	#define CONFIG_REVISION_TAG 1
	45
2fa8ca98 GL	46	#define CONFIG_OF_LIBFDT 1
2fa8ca98 GL	47
7379f45a DB	48	/*
	49	* Size of malloc() pool
	50	*/
9c44ddcc	51	#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
7379f45a	52	/* Sector */
9c44ddcc	53	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
7379f45a DB	54
	55	/*
	56	* Hardware drivers
	57	*/
	58
	59	/*
	60	* NS16550 Configuration
	61	*/
	62	#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
	63
	64	#define CONFIG_SYS_NS16550
	65	#define CONFIG_SYS_NS16550_SERIAL
	66	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	67	#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
	68
	69	/*
	70	* select serial console configuration
	71	*/
	72	#define CONFIG_CONS_INDEX 3
	73	#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
	74	#define CONFIG_SERIAL3 3 /* UART3 */
	75
	76	/* allow to overwrite serial and ethaddr */
	77	#define CONFIG_ENV_OVERWRITE
	78	#define CONFIG_BAUDRATE 115200
	79	#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
	80	115200}
d6906cb8	81	#define CONFIG_GENERIC_MMC 1
7379f45a	82	#define CONFIG_MMC 1
d6906cb8	83	#define CONFIG_OMAP_HSMMC 1
7379f45a DB	84	#define CONFIG_DOS_PARTITION 1
7379f45a DB	85
05be5a60 TR	86	/* USB */
	87	#define CONFIG_MUSB_UDC 1
	88	#define CONFIG_USB_OMAP3 1
	89	#define CONFIG_TWL4030_USB 1
	90
	91	/* USB device configuration */
	92	#define CONFIG_USB_DEVICE 1
	93	#define CONFIG_USB_TTY 1
	94	#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
	95	/* Change these to suit your needs */
	96	#define CONFIG_USBD_VENDORID 0x0451
	97	#define CONFIG_USBD_PRODUCTID 0x5678
	98	#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
	99	#define CONFIG_USBD_PRODUCT_NAME "Zoom1"
	100
7379f45a DB	101	/* commands to include */
	102	#include <config_cmd_default.h>
	103
	104	#define CONFIG_CMD_EXT2 /* EXT2 Support */
	105	#define CONFIG_CMD_FAT /* FAT support */
	106	#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
	107
	108	#define CONFIG_CMD_I2C /* I2C serial bus support */
	109	#define CONFIG_CMD_MMC /* MMC support */
	110	#define CONFIG_CMD_NAND /* NAND support */
e7deec1b	111	#define CONFIG_CMD_NAND_LOCK_UNLOCK /* Enable lock/unlock support */
7379f45a DB	112
	113	#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
	114	#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
	115	#undef CONFIG_CMD_IMI /* iminfo */
	116	#undef CONFIG_CMD_IMLS /* List all found images */
	117	#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
	118	#undef CONFIG_CMD_NFS /* NFS support */
	119
	120	#define CONFIG_SYS_NO_FLASH
0297ec7e	121	#define CONFIG_HARD_I2C 1
7379f45a DB	122	#define CONFIG_SYS_I2C_SPEED 100000
7379f45a DB	123	#define CONFIG_SYS_I2C_SLAVE 1
7379f45a DB	124	#define CONFIG_DRIVER_OMAP34XX_I2C 1
7379f45a DB	125
cd782635 TR	126	/*
	127	* TWL4030
	128	*/
	129	#define CONFIG_TWL4030_POWER 1
2c155130	130	#define CONFIG_TWL4030_LED 1
cd782635	131
7379f45a DB	132	/*
	133	* Board NAND Info.
	134	*/
	135	#define CONFIG_NAND_OMAP_GPMC
	136	#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
	137	/* to access nand */
	138	#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
	139	/* to access nand at */
	140	/* CS0 */
	141	#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
	142
	143	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
	144	/* devices */
7379f45a DB	145	#define CONFIG_JFFS2_NAND
	146	/* nand device jffs2 lives on */
	147	#define CONFIG_JFFS2_DEV "nand0"
	148	/* start of jffs2 partition */
	149	#define CONFIG_JFFS2_PART_OFFSET 0x680000
	150	#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
	151	/* partition */
	152
	153	/* Environment information */
	154	#define CONFIG_BOOTDELAY 10
	155
	156	#define CONFIG_EXTRA_ENV_SETTINGS \
	157	"loadaddr=0x82000000\0" \
05be5a60	158	"usbtty=cdc_acm\0" \
7379f45a	159	"console=ttyS2,115200n8\0" \
d6906cb8	160	"mmcdev=0\0" \
7379f45a DB	161	"videomode=1024x768@60,vxres=1024,vyres=768\0" \
	162	"videospec=omapfb:vram:2M,vram:4M\0" \
	163	"mmcargs=setenv bootargs console=${console} " \
	164	"video=${videospec},mode:${videomode} " \
	165	"root=/dev/mmcblk0p2 rw " \
	166	"rootfstype=ext3 rootwait\0" \
	167	"nandargs=setenv bootargs console=${console} " \
	168	"video=${videospec},mode:${videomode} " \
	169	"root=/dev/mtdblock4 rw " \
	170	"rootfstype=jffs2\0" \
d6906cb8	171	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
7379f45a	172	"bootscript=echo Running bootscript from mmc ...; " \
74de7aef	173	"source ${loadaddr}\0" \
d6906cb8	174	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
7379f45a DB	175	"mmcboot=echo Booting from mmc ...; " \
	176	"run mmcargs; " \
	177	"bootm ${loadaddr}\0" \
	178	"nandboot=echo Booting from nand ...; " \
	179	"run nandargs; " \
	180	"nand read ${loadaddr} 280000 400000; " \
	181	"bootm ${loadaddr}\0" \
	182
	183	#define CONFIG_BOOTCOMMAND \
66968110	184	"mmc dev ${mmcdev}; if mmc rescan; then " \
7379f45a DB	185	"if run loadbootscript; then " \
	186	"run bootscript; " \
	187	"else " \
	188	"if run loaduimage; then " \
	189	"run mmcboot; " \
	190	"else run nandboot; " \
	191	"fi; " \
	192	"fi; " \
	193	"else run nandboot; fi"
	194
	195	#define CONFIG_AUTO_COMPLETE 1
	196	/*
	197	* Miscellaneous configurable options
	198	*/
7379f45a DB	199	#define CONFIG_SYS_LONGHELP /* undef to save memory */
7379f45a DB	200	#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
1270ec13	201	#define CONFIG_SYS_PROMPT "OMAP3 Zoom1 # "
f62b1257	202	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
7379f45a DB	203	/* Print Buffer Size */
	204	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	205	sizeof(CONFIG_SYS_PROMPT) + 16)
	206	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	207	/* Boot Argument Buffer Size */
	208	#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
	209
	210	#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
	211	/* works on */
	212	#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
	213	0x01F00000) /* 31MB */
	214
7379f45a DB	215	#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
	216	/* load address */
	217
25435c6c DB	218	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	219	#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
	220	#define CONFIG_SYS_INIT_RAM_SIZE 0x800
	221	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
	222	CONFIG_SYS_INIT_RAM_SIZE - \
	223	GENERATED_GBL_DATA_SIZE)
7379f45a	224	/*
d3a513c2 MP	225	* OMAP3 has 12 GP timers, they can be driven by the system clock
	226	* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
	227	* This rate is divided by a local divisor.
7379f45a	228	*/
d3a513c2 MP	229	#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
d3a513c2 MP	230	#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
7379f45a	231
7379f45a DB	232	/*-----------------------------------------------------------------------
	233	* Physical Memory Map
	234	*/
	235	#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
	236	#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
7379f45a DB	237	#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
7379f45a DB	238
7379f45a DB	239	/*-----------------------------------------------------------------------
	240	* FLASH and environment organization
	241	*/
	242
	243	/* ** PISMO SUPPORT * */
	244
	245	/* Configure the PISMO */
	246	#define PISMO1_NAND_SIZE GPMC_SIZE_128M
	247	#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
	248
9c44ddcc	249	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
7379f45a	250
6cbec7b3 LC	251	#if defined(CONFIG_CMD_NAND)
	252	#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
	253	#endif
7379f45a DB	254
	255	/* Monitor at start of flash */
	256	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	257	#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
	258
	259	#define CONFIG_ENV_IS_IN_NAND 1
	260	#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
	261	#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
	262
6cbec7b3 LC	263	#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
6cbec7b3 LC	264	#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
7379f45a DB	265	#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
7379f45a DB	266
8e40852f A	267	#define CONFIG_SYS_CACHELINE_SIZE 64
8e40852f A	268
7379f45a	269	#endif /* __CONFIG_H */