[people/ms/u-boot.git] / include / configs / origen.h

/*
 * Copyright (C) 2011 Samsung Electronics
 *
 * Configuration settings for the SAMSUNG ORIGEN (EXYNOS4210) board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* High Level Configuration Options */
#define CONFIG_SAMSUNG			1	/* SAMSUNG core */
#define CONFIG_S5P			1	/* S5P Family */
#define CONFIG_EXYNOS4210		1	/* which is a EXYNOS4210 SoC */
#define CONFIG_ORIGEN			1	/* working with ORIGEN*/

#include <asm/arch/cpu.h>		/* get chip and board defs */

#define CONFIG_ARCH_CPU_INIT
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO

/* Keep L2 Cache Disabled */
#define CONFIG_L2_OFF			1
#define CONFIG_SYS_DCACHE_OFF		1

#define CONFIG_SYS_SDRAM_BASE		0x40000000
#define CONFIG_SYS_TEXT_BASE		0x43E00000

/* input clock of PLL: ORIGEN has 24MHz input clock */
#define CONFIG_SYS_CLK_FREQ		24000000

#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_CMDLINE_TAG
#define CONFIG_INITRD_TAG
#define CONFIG_CMDLINE_EDITING

#define CONFIG_MACH_TYPE		MACH_TYPE_ORIGEN

/* Power Down Modes */
#define S5P_CHECK_SLEEP			0x00000BAD
#define S5P_CHECK_DIDLE			0xBAD00000
#define S5P_CHECK_LPA			0xABAD0000

/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (1 << 20))

/* select serial console configuration */
#define CONFIG_SERIAL2			1	/* use SERIAL 2 */
#define CONFIG_BAUDRATE			115200
#define EXYNOS4_DEFAULT_UART_OFFSET	0x020000

/* SD/MMC configuration */
#define CONFIG_GENERIC_MMC
#define CONFIG_MMC
#define CONFIG_SDHCI
#define CONFIG_S5P_SDHCI

/* PWM */
#define CONFIG_PWM			1

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE

/* Command definition*/
#include <config_cmd_default.h>

#undef CONFIG_CMD_PING
#define CONFIG_CMD_ELF
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MMC
#define CONFIG_CMD_FAT
#undef CONFIG_CMD_NET
#undef CONFIG_CMD_NFS

#define CONFIG_BOOTDELAY		3
#define CONFIG_ZERO_BOOTDELAY_CHECK
/* MMC SPL */
#define CONFIG_SPL
#define COPY_BL2_FNPTR_ADDR	0x02020030

#define CONFIG_SPL_TEXT_BASE	0x02021410

#define CONFIG_BOOTCOMMAND	"fatload mmc 0 40007000 uImage; bootm 40007000"

/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser	*/
#define CONFIG_SYS_PROMPT		"ORIGEN # "
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size*/
#define CONFIG_SYS_PBSIZE		384	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC2,115200n8\0"
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
/* memtest works on */
#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x6000000)
#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x3E00000)

#define CONFIG_SYS_HZ			1000

/* ORIGEN has 4 bank of DRAM */
#define CONFIG_NR_DRAM_BANKS	4
#define SDRAM_BANK_SIZE		(256UL << 20UL)	/* 256 MB */
#define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE
#define PHYS_SDRAM_1_SIZE	SDRAM_BANK_SIZE
#define PHYS_SDRAM_2		(CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
#define PHYS_SDRAM_2_SIZE	SDRAM_BANK_SIZE
#define PHYS_SDRAM_3		(CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_3_SIZE	SDRAM_BANK_SIZE
#define PHYS_SDRAM_4		(CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_4_SIZE	SDRAM_BANK_SIZE

/* FLASH and environment organization */
#define CONFIG_SYS_NO_FLASH		1
#undef CONFIG_CMD_IMLS
#define CONFIG_IDENT_STRING		" for ORIGEN"

#define CONFIG_CLK_1000_400_200

/* MIU (Memory Interleaving Unit) */
#define CONFIG_MIU_2BIT_21_7_INTERLEAVED

#define CONFIG_ENV_IS_IN_MMC		1
#define CONFIG_SYS_MMC_ENV_DEV		0
#define CONFIG_ENV_SIZE			(16 << 10)	/* 16 KB */
#define RESERVE_BLOCK_SIZE		(512)
#define BL1_SIZE			(16 << 10) /*16 K reserved for BL1*/
#define CONFIG_ENV_OFFSET		(RESERVE_BLOCK_SIZE + BL1_SIZE)
#define CONFIG_DOS_PARTITION		1

#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE)

/* U-boot copy size from boot Media to DRAM.*/
#define COPY_BL2_SIZE		0x80000
#define BL2_START_OFFSET	((CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)/512)
#define BL2_SIZE_BLOC_COUNT	(COPY_BL2_SIZE/512)

/* Enable devicetree support */
#define CONFIG_OF_LIBFDT
#endif	/* __CONFIG_H */
Commit	Line	Data
b9a1ef21 CK	1	/*
	2	* Copyright (C) 2011 Samsung Electronics
	3	*
393cb361	4	* Configuration settings for the SAMSUNG ORIGEN (EXYNOS4210) board.
b9a1ef21 CK	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	#ifndef __CONFIG_H
	26	#define __CONFIG_H
	27
	28	/* High Level Configuration Options */
	29	#define CONFIG_SAMSUNG 1 /* SAMSUNG core */
	30	#define CONFIG_S5P 1 /* S5P Family */
393cb361	31	#define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */
b9a1ef21 CK	32	#define CONFIG_ORIGEN 1 /* working with ORIGEN*/
	33
	34	#include <asm/arch/cpu.h> /* get chip and board defs */
	35
	36	#define CONFIG_ARCH_CPU_INIT
	37	#define CONFIG_DISPLAY_CPUINFO
	38	#define CONFIG_DISPLAY_BOARDINFO
	39
	40	/* Keep L2 Cache Disabled */
	41	#define CONFIG_L2_OFF 1
	42	#define CONFIG_SYS_DCACHE_OFF 1
	43
	44	#define CONFIG_SYS_SDRAM_BASE 0x40000000
	45	#define CONFIG_SYS_TEXT_BASE 0x43E00000
	46
	47	/* input clock of PLL: ORIGEN has 24MHz input clock */
	48	#define CONFIG_SYS_CLK_FREQ 24000000
	49
	50	#define CONFIG_SETUP_MEMORY_TAGS
	51	#define CONFIG_CMDLINE_TAG
	52	#define CONFIG_INITRD_TAG
	53	#define CONFIG_CMDLINE_EDITING
	54
b9a1ef21 CK	55	#define CONFIG_MACH_TYPE MACH_TYPE_ORIGEN
	56
	57	/* Power Down Modes */
	58	#define S5P_CHECK_SLEEP 0x00000BAD
	59	#define S5P_CHECK_DIDLE 0xBAD00000
	60	#define S5P_CHECK_LPA 0xABAD0000
	61
	62	/* Size of malloc() pool */
	63	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
	64
	65	/* select serial console configuration */
b9a1ef21 CK	66	#define CONFIG_SERIAL2 1 /* use SERIAL 2 */
b9a1ef21 CK	67	#define CONFIG_BAUDRATE 115200
393cb361	68	#define EXYNOS4_DEFAULT_UART_OFFSET 0x020000
b9a1ef21 CK	69
b9a1ef21 CK	70	/* SD/MMC configuration */
7d2d58b4 JC	71	#define CONFIG_GENERIC_MMC
	72	#define CONFIG_MMC
	73	#define CONFIG_SDHCI
	74	#define CONFIG_S5P_SDHCI
b9a1ef21 CK	75
	76	/* PWM */
	77	#define CONFIG_PWM 1
	78
	79	/* allow to overwrite serial and ethaddr */
	80	#define CONFIG_ENV_OVERWRITE
	81
	82	/* Command definition*/
	83	#include <config_cmd_default.h>
	84
80615006	85	#undef CONFIG_CMD_PING
b9a1ef21 CK	86	#define CONFIG_CMD_ELF
	87	#define CONFIG_CMD_DHCP
	88	#define CONFIG_CMD_MMC
	89	#define CONFIG_CMD_FAT
	90	#undef CONFIG_CMD_NET
	91	#undef CONFIG_CMD_NFS
	92
	93	#define CONFIG_BOOTDELAY 3
	94	#define CONFIG_ZERO_BOOTDELAY_CHECK
98a48c5d CK	95	/* MMC SPL */
	96	#define CONFIG_SPL
	97	#define COPY_BL2_FNPTR_ADDR 0x02020030
b9a1ef21	98
8a00061e IS	99	#define CONFIG_SPL_TEXT_BASE 0x02021410
8a00061e IS	100
b9a1ef21 CK	101	#define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000"
	102
	103	/* Miscellaneous configurable options */
	104	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	105	#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
b9a1ef21 CK	106	#define CONFIG_SYS_PROMPT "ORIGEN # "
	107	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size*/
	108	#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
	109	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	110	#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
	111	/* Boot Argument Buffer Size */
	112	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	113	/* memtest works on */
	114	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
	115	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x6000000)
	116	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
	117
	118	#define CONFIG_SYS_HZ 1000
	119
b9a1ef21 CK	120	/* ORIGEN has 4 bank of DRAM */
	121	#define CONFIG_NR_DRAM_BANKS 4
	122	#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
	123	#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
	124	#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
	125	#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
	126	#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
	127	#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
	128	#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
	129	#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
	130	#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
	131
	132	/* FLASH and environment organization */
	133	#define CONFIG_SYS_NO_FLASH 1
	134	#undef CONFIG_CMD_IMLS
	135	#define CONFIG_IDENT_STRING " for ORIGEN"
	136
b9a1ef21 CK	137	#define CONFIG_CLK_1000_400_200
	138
	139	/* MIU (Memory Interleaving Unit) */
	140	#define CONFIG_MIU_2BIT_21_7_INTERLEAVED
	141
	142	#define CONFIG_ENV_IS_IN_MMC 1
	143	#define CONFIG_SYS_MMC_ENV_DEV 0
	144	#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
	145	#define RESERVE_BLOCK_SIZE (512)
	146	#define BL1_SIZE (16 << 10) /16 K reserved for BL1/
	147	#define CONFIG_ENV_OFFSET (RESERVE_BLOCK_SIZE + BL1_SIZE)
	148	#define CONFIG_DOS_PARTITION 1
	149
	150	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE)
98a48c5d CK	151
	152	/* U-boot copy size from boot Media to DRAM.*/
	153	#define COPY_BL2_SIZE 0x80000
	154	#define BL2_START_OFFSET ((CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)/512)
	155	#define BL2_SIZE_BLOC_COUNT (COPY_BL2_SIZE/512)
099e884a AA	156
	157	/* Enable devicetree support */
	158	#define CONFIG_OF_LIBFDT
b9a1ef21	159	#endif /* __CONFIG_H */