[people/ms/u-boot.git] / include / configs / pcm052.h

/*
 * Copyright 2013 Freescale Semiconductor, Inc.
 *
 * Configuration settings for the phytec PCM-052 SoM.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include <asm/arch/imx-regs.h>

#define CONFIG_VF610

#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_THUMB_BUILD

#define CONFIG_SKIP_LOWLEVEL_INIT

/* Enable passing of ATAGs */
#define CONFIG_CMDLINE_TAG

/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)

#define CONFIG_BOARD_EARLY_INIT_F

/* Allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE			115200

/* NAND support */
#define CONFIG_CMD_NAND
#define CONFIG_CMD_NAND_TRIMFFS
#define CONFIG_SYS_NAND_ONFI_DETECTION

#ifdef CONFIG_CMD_NAND
#define CONFIG_USE_ARCH_MEMCPY
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_SYS_NAND_BASE		NFC_BASE_ADDR

#define CONFIG_JFFS2_NAND

/* UBI */
#define CONFIG_CMD_UBIFS
#define CONFIG_RBTREE
#define CONFIG_LZO

/* Dynamic MTD partition support */
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_PARTITIONS
#define CONFIG_MTD_DEVICE
#define MTDIDS_DEFAULT			"nand0=NAND"
#define MTDPARTS_DEFAULT		"mtdparts=NAND:640k(bootloader)"\
					",128k(env1)"\
					",128k(env2)"\
					",128k(dtb)"\
					",6144k(kernel)"\
					",-(root)"
#endif

#define CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR	0
#define CONFIG_SYS_FSL_ESDHC_NUM	1

/*#define CONFIG_ESDHC_DETECT_USE_EXTERN_IRQ1*/
#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001

#define CONFIG_GENERIC_MMC
#define CONFIG_DOS_PARTITION

#define CONFIG_FEC_MXC
#define CONFIG_MII
#define IMX_FEC_BASE			ENET_BASE_ADDR
#define CONFIG_FEC_XCV_TYPE		RMII
#define CONFIG_FEC_MXC_PHYADDR          0
#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL

/* QSPI Configs*/

#ifdef CONFIG_FSL_QSPI
#define CONFIG_SPI_FLASH
#define FSL_QSPI_FLASH_SIZE		(1 << 24)
#define FSL_QSPI_FLASH_NUM		2
#define CONFIG_SYS_FSL_QSPI_LE
#endif

/* I2C Configs */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC_I2C3
#define CONFIG_SYS_I2C_MXC

/* RTC (actually an RV-4162 but M41T62-compatible) */
#define CONFIG_CMD_DATE
#define CONFIG_RTC_M41T62
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
#define CONFIG_SYS_RTC_BUS_NUM 2

/* EEPROM (24FC256) */
#define CONFIG_CMD_EEPROM
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_I2C_EEPROM_BUS 2


#define CONFIG_LOADADDR			0x82000000

/* We boot from the gfxRAM area of the OCRAM. */
#define CONFIG_SYS_TEXT_BASE		0x3f408000
#define CONFIG_BOARD_SIZE_LIMIT		524288

#define CONFIG_BOOTCOMMAND              "run bootcmd_sd"
#define CONFIG_EXTRA_ENV_SETTINGS \
	"fdt_high=0xffffffff\0" \
	"initrd_high=0xffffffff\0" \
	"blimg_file=u-boot.vyb\0" \
	"blimg_addr=0x81000000\0" \
	"kernel_file=zImage\0" \
	"kernel_addr=0x82000000\0" \
	"fdt_file=zImage.dtb\0" \
	"fdt_addr=0x81000000\0" \
	"ram_file=uRamdisk\0" \
	"ram_addr=0x83000000\0" \
	"filesys=rootfs.ubifs\0" \
	"sys_addr=0x81000000\0" \
	"tftploc=/path/to/tftp/directory/\0" \
	"nfs_root=/path/to/nfs/root\0" \
	"tftptimeout=1000\0" \
	"tftptimeoutcountmax=1000000\0" \
	"mtdparts=" MTDPARTS_DEFAULT "\0" \
	"bootargs_base=setenv bootargs rw mem=256M " \
		"console=ttyLP1,115200n8\0" \
	"bootargs_sd=setenv bootargs ${bootargs} " \
		"root=/dev/mmcblk0p2 rootwait\0" \
	"bootargs_net=setenv bootargs ${bootargs} root=/dev/nfs ip=dhcp " \
		"nfsroot=${serverip}:${nfs_root},v3,tcp\0" \
	"bootargs_nand=setenv bootargs ${bootargs} " \
		"ubi.mtd=5 rootfstype=ubifs root=ubi0:rootfs\0" \
	"bootargs_ram=setenv bootargs ${bootargs} " \
		"root=/dev/ram rw initrd=${ram_addr}\0" \
	"bootargs_mtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
	"bootcmd_sd=run bootargs_base bootargs_sd bootargs_mtd; " \
		"fatload mmc 0:1 ${kernel_addr} ${kernel_file}; " \
		"fatload mmc 0:1 ${fdt_addr} ${fdt_file}; " \
		"bootz ${kernel_addr} - ${fdt_addr}\0" \
	"bootcmd_net=run bootargs_base bootargs_net bootargs_mtd; " \
		"tftpboot ${kernel_addr} ${tftpdir}${kernel_file}; " \
		"tftpboot ${fdt_addr} ${tftpdir}${fdt_file}; " \
		"bootz ${kernel_addr} - ${fdt_addr}\0" \
	"bootcmd_nand=run bootargs_base bootargs_nand bootargs_mtd; " \
		"nand read ${fdt_addr} dtb; " \
		"nand read ${kernel_addr} kernel; " \
		"bootz ${kernel_addr} - ${fdt_addr}\0" \
	"bootcmd_ram=run bootargs_base bootargs_ram bootargs_mtd; " \
		"nand read ${fdt_addr} dtb; " \
		"nand read ${kernel_addr} kernel; " \
		"nand read ${ram_addr} root; " \
		"bootz ${kernel_addr} ${ram_addr} ${fdt_addr}\0" \
	"update_bootloader_from_tftp=if tftp ${blimg_addr} "\
		"${tftpdir}${blimg_file}; then " \
		"mtdparts default; " \
		"nand erase.part bootloader; " \
		"nand write ${blimg_addr} bootloader ${filesize}; fi\0" \
	"update_kernel_from_sd=if fatload mmc 0:2 ${kernel_addr} " \
		"${kernel_file}; " \
		"then mtdparts default; " \
		"nand erase.part kernel; " \
		"nand write ${kernel_addr} kernel ${filesize}; " \
		"if fatload mmc 0:2 ${fdt_addr} ${fdt_file}; then " \
		"nand erase.part dtb; " \
		"nand write ${fdt_addr} dtb ${filesize}; fi\0" \
	"update_kernel_from_tftp=if tftp ${fdt_addr} ${tftpdir}${fdt_file}; " \
		"then setenv fdtsize ${filesize}; " \
		"if tftp ${kernel_addr} ${tftpdir}${kernel_file}; then " \
		"mtdparts default; " \
		"nand erase.part dtb; " \
		"nand write ${fdt_addr} dtb ${fdtsize}; " \
		"nand erase.part kernel; " \
		"nand write ${kernel_addr} kernel ${filesize}; fi; fi\0" \
	"update_rootfs_from_tftp=if tftp ${sys_addr} ${tftpdir}${filesys}; " \
		"then mtdparts default; " \
		"nand erase.part root; " \
		"ubi part root; " \
		"ubi create rootfs; " \
		"ubi write ${sys_addr} rootfs ${filesize}; fi\0" \
	"update_ramdisk_from_tftp=if tftp ${ram_addr} ${tftpdir}${ram_file}; " \
		"then mtdparts default; " \
		"nand erase.part root; " \
		"nand write ${ram_addr} root ${filesize}; fi\0"

/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE		\
			(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE

#define CONFIG_SYS_MEMTEST_START	0x80010000
#define CONFIG_SYS_MEMTEST_END		0x87C00000

#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR

/*
 * Stack sizes
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE		(128 * 1024)	/* regular stack */

/* Physical memory map */
#define CONFIG_NR_DRAM_BANKS		1
#define PHYS_SDRAM			(0x80000000)
#define PHYS_SDRAM_SIZE			(256 * 1024 * 1024)

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE

#define CONFIG_SYS_INIT_SP_OFFSET \
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

/* FLASH and environment organization */
#define CONFIG_SYS_NO_FLASH

#ifdef CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_SIZE			(8 * 1024)

#define CONFIG_ENV_OFFSET		(12 * 64 * 1024)
#define CONFIG_SYS_MMC_ENV_DEV		0
#endif

#ifdef CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SECT_SIZE		(128 * 1024)
#define CONFIG_ENV_SIZE			(8 * 1024)
#define CONFIG_ENV_OFFSET		0xA0000
#define CONFIG_ENV_SIZE_REDUND		(8 * 1024)
#define CONFIG_ENV_OFFSET_REDUND	0xC0000
#endif

#endif
Commit	Line	Data
931a1d2a AA	1	/*
	2	* Copyright 2013 Freescale Semiconductor, Inc.
	3	*
	4	* Configuration settings for the phytec PCM-052 SoM.
	5	*
	6	* SPDX-License-Identifier: GPL-2.0+
	7	*/
	8
	9	#ifndef __CONFIG_H
	10	#define __CONFIG_H
	11
	12	#include <asm/arch/imx-regs.h>
	13
	14	#define CONFIG_VF610
	15
931a1d2a AA	16	#define CONFIG_DISPLAY_CPUINFO
	17	#define CONFIG_DISPLAY_BOARDINFO
	18	#define CONFIG_SYS_THUMB_BUILD
	19
	20	#define CONFIG_SKIP_LOWLEVEL_INIT
	21
	22	/* Enable passing of ATAGs */
	23	#define CONFIG_CMDLINE_TAG
	24
	25	/* Size of malloc() pool */
	26	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
	27
	28	#define CONFIG_BOARD_EARLY_INIT_F
	29
931a1d2a AA	30	/* Allow to overwrite serial and ethaddr */
931a1d2a AA	31	#define CONFIG_ENV_OVERWRITE
931a1d2a AA	32	#define CONFIG_BAUDRATE 115200
931a1d2a AA	33
931a1d2a AA	34	/* NAND support */
	35	#define CONFIG_CMD_NAND
	36	#define CONFIG_CMD_NAND_TRIMFFS
	37	#define CONFIG_SYS_NAND_ONFI_DETECTION
	38
	39	#ifdef CONFIG_CMD_NAND
	40	#define CONFIG_USE_ARCH_MEMCPY
	41	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	42	#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
	43
	44	#define CONFIG_JFFS2_NAND
	45
	46	/* UBI */
931a1d2a AA	47	#define CONFIG_CMD_UBIFS
	48	#define CONFIG_RBTREE
	49	#define CONFIG_LZO
	50
	51	/* Dynamic MTD partition support */
	52	#define CONFIG_CMD_MTDPARTS
	53	#define CONFIG_MTD_PARTITIONS
	54	#define CONFIG_MTD_DEVICE
040ef8f5	55	#define MTDIDS_DEFAULT "nand0=NAND"
27f7d4f5	56	#define MTDPARTS_DEFAULT "mtdparts=NAND:640k(bootloader)"\
931a1d2a AA	57	",128k(env1)"\
931a1d2a AA	58	",128k(env2)"\
040ef8f5 AA	59	",128k(dtb)"\
040ef8f5 AA	60	",6144k(kernel)"\
27f7d4f5	61	",-(root)"
931a1d2a AA	62	#endif
	63
	64	#define CONFIG_MMC
	65	#define CONFIG_FSL_ESDHC
	66	#define CONFIG_SYS_FSL_ESDHC_ADDR 0
	67	#define CONFIG_SYS_FSL_ESDHC_NUM 1
	68
	69	/#define CONFIG_ESDHC_DETECT_USE_EXTERN_IRQ1/
	70	#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
	71	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
	72	#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
	73
931a1d2a	74	#define CONFIG_GENERIC_MMC
931a1d2a AA	75	#define CONFIG_DOS_PARTITION
931a1d2a AA	76
931a1d2a AA	77	#define CONFIG_FEC_MXC
	78	#define CONFIG_MII
	79	#define IMX_FEC_BASE ENET_BASE_ADDR
	80	#define CONFIG_FEC_XCV_TYPE RMII
	81	#define CONFIG_FEC_MXC_PHYADDR 0
	82	#define CONFIG_PHYLIB
	83	#define CONFIG_PHY_MICREL
	84
	85	/* QSPI Configs*/
931a1d2a AA	86
931a1d2a AA	87	#ifdef CONFIG_FSL_QSPI
931a1d2a	88	#define CONFIG_SPI_FLASH
931a1d2a AA	89	#define FSL_QSPI_FLASH_SIZE (1 << 24)
	90	#define FSL_QSPI_FLASH_NUM 2
	91	#define CONFIG_SYS_FSL_QSPI_LE
	92	#endif
	93
	94	/* I2C Configs */
931a1d2a AA	95	#define CONFIG_SYS_I2C
	96	#define CONFIG_SYS_I2C_MXC_I2C3
	97	#define CONFIG_SYS_I2C_MXC
	98
	99	/* RTC (actually an RV-4162 but M41T62-compatible) */
	100	#define CONFIG_CMD_DATE
	101	#define CONFIG_RTC_M41T62
	102	#define CONFIG_SYS_I2C_RTC_ADDR 0x68
	103	#define CONFIG_SYS_RTC_BUS_NUM 2
	104
	105	/* EEPROM (24FC256) */
	106	#define CONFIG_CMD_EEPROM
	107	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
	108	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
	109	#define CONFIG_SYS_I2C_EEPROM_BUS 2
	110
931a1d2a AA	111
	112	#define CONFIG_LOADADDR 0x82000000
	113
	114	/* We boot from the gfxRAM area of the OCRAM. */
	115	#define CONFIG_SYS_TEXT_BASE 0x3f408000
	116	#define CONFIG_BOARD_SIZE_LIMIT 524288
	117
	118	#define CONFIG_BOOTCOMMAND "run bootcmd_sd"
040ef8f5 AA	119	#define CONFIG_EXTRA_ENV_SETTINGS \
	120	"fdt_high=0xffffffff\0" \
	121	"initrd_high=0xffffffff\0" \
ed0c2c0a AA	122	"blimg_file=u-boot.vyb\0" \
ed0c2c0a AA	123	"blimg_addr=0x81000000\0" \
040ef8f5 AA	124	"kernel_file=zImage\0" \
040ef8f5 AA	125	"kernel_addr=0x82000000\0" \
083e4fd4	126	"fdt_file=zImage.dtb\0" \
040ef8f5 AA	127	"fdt_addr=0x81000000\0" \
	128	"ram_file=uRamdisk\0" \
	129	"ram_addr=0x83000000\0" \
	130	"filesys=rootfs.ubifs\0" \
	131	"sys_addr=0x81000000\0" \
	132	"tftploc=/path/to/tftp/directory/\0" \
	133	"nfs_root=/path/to/nfs/root\0" \
	134	"tftptimeout=1000\0" \
	135	"tftptimeoutcountmax=1000000\0" \
	136	"mtdparts=" MTDPARTS_DEFAULT "\0" \
	137	"bootargs_base=setenv bootargs rw mem=256M " \
	138	"console=ttyLP1,115200n8\0" \
	139	"bootargs_sd=setenv bootargs ${bootargs} " \
	140	"root=/dev/mmcblk0p2 rootwait\0" \
931a1d2a	141	"bootargs_net=setenv bootargs ${bootargs} root=/dev/nfs ip=dhcp " \
040ef8f5 AA	142	"nfsroot=${serverip}:${nfs_root},v3,tcp\0" \
040ef8f5 AA	143	"bootargs_nand=setenv bootargs ${bootargs} " \
27f7d4f5	144	"ubi.mtd=5 rootfstype=ubifs root=ubi0:rootfs\0" \
040ef8f5 AA	145	"bootargs_ram=setenv bootargs ${bootargs} " \
	146	"root=/dev/ram rw initrd=${ram_addr}\0" \
	147	"bootargs_mtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
	148	"bootcmd_sd=run bootargs_base bootargs_sd bootargs_mtd; " \
	149	"fatload mmc 0:1 ${kernel_addr} ${kernel_file}; " \
	150	"fatload mmc 0:1 ${fdt_addr} ${fdt_file}; " \
	151	"bootz ${kernel_addr} - ${fdt_addr}\0" \
	152	"bootcmd_net=run bootargs_base bootargs_net bootargs_mtd; " \
	153	"tftpboot ${kernel_addr} ${tftpdir}${kernel_file}; " \
	154	"tftpboot ${fdt_addr} ${tftpdir}${fdt_file}; " \
	155	"bootz ${kernel_addr} - ${fdt_addr}\0" \
	156	"bootcmd_nand=run bootargs_base bootargs_nand bootargs_mtd; " \
	157	"nand read ${fdt_addr} dtb; " \
	158	"nand read ${kernel_addr} kernel; " \
	159	"bootz ${kernel_addr} - ${fdt_addr}\0" \
	160	"bootcmd_ram=run bootargs_base bootargs_ram bootargs_mtd; " \
	161	"nand read ${fdt_addr} dtb; " \
	162	"nand read ${kernel_addr} kernel; " \
27f7d4f5	163	"nand read ${ram_addr} root; " \
040ef8f5	164	"bootz ${kernel_addr} ${ram_addr} ${fdt_addr}\0" \
ed0c2c0a AA	165	"update_bootloader_from_tftp=if tftp ${blimg_addr} "\
	166	"${tftpdir}${blimg_file}; then " \
	167	"mtdparts default; " \
040ef8f5	168	"nand erase.part bootloader; " \
ed0c2c0a	169	"nand write ${blimg_addr} bootloader ${filesize}; fi\0" \
040ef8f5 AA	170	"update_kernel_from_sd=if fatload mmc 0:2 ${kernel_addr} " \
	171	"${kernel_file}; " \
	172	"then mtdparts default; " \
	173	"nand erase.part kernel; " \
	174	"nand write ${kernel_addr} kernel ${filesize}; " \
	175	"if fatload mmc 0:2 ${fdt_addr} ${fdt_file}; then " \
	176	"nand erase.part dtb; " \
	177	"nand write ${fdt_addr} dtb ${filesize}; fi\0" \
	178	"update_kernel_from_tftp=if tftp ${fdt_addr} ${tftpdir}${fdt_file}; " \
	179	"then setenv fdtsize ${filesize}; " \
	180	"if tftp ${kernel_addr} ${tftpdir}${kernel_file}; then " \
	181	"mtdparts default; " \
	182	"nand erase.part dtb; " \
	183	"nand write ${fdt_addr} dtb ${fdtsize}; " \
	184	"nand erase.part kernel; " \
	185	"nand write ${kernel_addr} kernel ${filesize}; fi; fi\0" \
	186	"update_rootfs_from_tftp=if tftp ${sys_addr} ${tftpdir}${filesys}; " \
	187	"then mtdparts default; " \
	188	"nand erase.part root; " \
	189	"ubi part root; " \
	190	"ubi create rootfs; " \
	191	"ubi write ${sys_addr} rootfs ${filesize}; fi\0" \
	192	"update_ramdisk_from_tftp=if tftp ${ram_addr} ${tftpdir}${ram_file}; " \
	193	"then mtdparts default; " \
27f7d4f5 AA	194	"nand erase.part root; " \
27f7d4f5 AA	195	"nand write ${ram_addr} root ${filesize}; fi\0"
931a1d2a	196
931a1d2a AA	197	/* Miscellaneous configurable options */
931a1d2a AA	198	#define CONFIG_SYS_LONGHELP /* undef to save memory */
931a1d2a AA	199	#define CONFIG_AUTO_COMPLETE
	200	#define CONFIG_CMDLINE_EDITING
	201	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	202	#define CONFIG_SYS_PBSIZE \
	203	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	204	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	205	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	206
931a1d2a AA	207	#define CONFIG_SYS_MEMTEST_START 0x80010000
	208	#define CONFIG_SYS_MEMTEST_END 0x87C00000
	209
	210	#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
	211
	212	/*
	213	* Stack sizes
	214	* The stack sizes are set up in start.S using the settings below
	215	*/
	216	#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
	217
	218	/* Physical memory map */
	219	#define CONFIG_NR_DRAM_BANKS 1
	220	#define PHYS_SDRAM (0x80000000)
	221	#define PHYS_SDRAM_SIZE (256 * 1024 * 1024)
	222
	223	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
	224	#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
	225	#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
	226
	227	#define CONFIG_SYS_INIT_SP_OFFSET \
	228	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	229	#define CONFIG_SYS_INIT_SP_ADDR \
	230	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
	231
	232	/* FLASH and environment organization */
	233	#define CONFIG_SYS_NO_FLASH
	234
	235	#ifdef CONFIG_ENV_IS_IN_MMC
	236	#define CONFIG_ENV_SIZE (8 * 1024)
	237
	238	#define CONFIG_ENV_OFFSET (12 * 64 * 1024)
	239	#define CONFIG_SYS_MMC_ENV_DEV 0
	240	#endif
	241
	242	#ifdef CONFIG_ENV_IS_IN_NAND
	243	#define CONFIG_ENV_SECT_SIZE (128 * 1024)
	244	#define CONFIG_ENV_SIZE (8 * 1024)
040ef8f5	245	#define CONFIG_ENV_OFFSET 0xA0000
931a1d2a	246	#define CONFIG_ENV_SIZE_REDUND (8 * 1024)
040ef8f5	247	#define CONFIG_ENV_OFFSET_REDUND 0xC0000
931a1d2a AA	248	#endif
931a1d2a AA	249
931a1d2a	250	#endif