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Commit | Line | Data |
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5e4b3361 SR |
1 | /* |
2 | * (C) Copyright 2003-2004 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
5e4b3361 SR |
6 | */ |
7 | ||
8 | /************************************************************************* | |
9 | * (c) 2005 esd gmbh Hannover | |
10 | * | |
11 | * | |
12 | * from IceCube.h file | |
13 | * by Reinhard Arlt reinhard.arlt@esd-electronics.com | |
14 | * | |
15 | *************************************************************************/ | |
16 | ||
17 | #ifndef __CONFIG_H | |
18 | #define __CONFIG_H | |
19 | ||
20 | /* | |
21 | * High Level Configuration Options | |
22 | * (easy to change) | |
23 | */ | |
24 | ||
25 | #define CONFIG_MPC5200 1 /* This is an MPC5xxx CPU */ | |
26 | #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ | |
27 | #define CONFIG_ICECUBE 1 /* ... on IceCube board */ | |
28 | #define CONFIG_PF5200 1 /* ... on PF5200 board */ | |
29 | #define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */ | |
30 | ||
2ae18241 WD |
31 | #ifndef CONFIG_SYS_TEXT_BASE |
32 | #define CONFIG_SYS_TEXT_BASE 0xFFF00000 | |
33 | #endif | |
34 | ||
6d0f6bcf | 35 | #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ |
5e4b3361 | 36 | |
31d82672 | 37 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
5e4b3361 SR |
38 | /* |
39 | * Serial console configuration | |
40 | */ | |
41 | #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ | |
42 | #if 0 /* test-only */ | |
43 | #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ | |
44 | #else | |
45 | #define CONFIG_BAUDRATE 9600 /* ... at 115200 bps */ | |
46 | #endif | |
6d0f6bcf | 47 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
5e4b3361 | 48 | |
5e4b3361 SR |
49 | /* |
50 | * PCI Mapping: | |
51 | * 0x40000000 - 0x4fffffff - PCI Memory | |
52 | * 0x50000000 - 0x50ffffff - PCI IO Space | |
53 | */ | |
54 | #define CONFIG_PCI 1 | |
55 | #define CONFIG_PCI_PNP 1 | |
56 | #define CONFIG_PCI_SCAN_SHOW 1 | |
f33fca22 | 57 | #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 |
5e4b3361 SR |
58 | |
59 | #define CONFIG_PCI_MEM_BUS 0x40000000 | |
60 | #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS | |
61 | #define CONFIG_PCI_MEM_SIZE 0x10000000 | |
62 | ||
63 | #define CONFIG_PCI_IO_BUS 0x50000000 | |
64 | #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS | |
65 | #define CONFIG_PCI_IO_SIZE 0x01000000 | |
66 | ||
63ff004c | 67 | #define CONFIG_MII 1 |
5e4b3361 | 68 | #if 0 /* test-only !!! */ |
5e4b3361 | 69 | #define CONFIG_EEPRO100 1 |
6d0f6bcf | 70 | #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ |
5e4b3361 SR |
71 | #define CONFIG_NS8382X 1 |
72 | #endif | |
5e4b3361 SR |
73 | |
74 | /* Partitions */ | |
75 | #define CONFIG_MAC_PARTITION | |
76 | #define CONFIG_DOS_PARTITION | |
77 | ||
78 | /* USB */ | |
79 | #if 0 | |
80 | #define CONFIG_USB_OHCI | |
5e4b3361 | 81 | #define CONFIG_USB_STORAGE |
5e4b3361 SR |
82 | #endif |
83 | ||
d794cfef | 84 | |
079a136c JL |
85 | /* |
86 | * BOOTP options | |
87 | */ | |
88 | #define CONFIG_BOOTP_BOOTFILESIZE | |
89 | #define CONFIG_BOOTP_BOOTPATH | |
90 | #define CONFIG_BOOTP_GATEWAY | |
91 | #define CONFIG_BOOTP_HOSTNAME | |
92 | ||
93 | ||
5e4b3361 | 94 | /* |
d794cfef | 95 | * Command line configuration. |
5e4b3361 | 96 | */ |
d794cfef JL |
97 | #include <config_cmd_default.h> |
98 | ||
99 | #define CONFIG_CMD_BSP | |
d794cfef JL |
100 | #define CONFIG_CMD_EEPROM |
101 | #define CONFIG_CMD_ELF | |
102 | #define CONFIG_CMD_FAT | |
103 | #define CONFIG_CMD_I2C | |
104 | #define CONFIG_CMD_IDE | |
105 | ||
079a136c | 106 | #define CONFIG_CMD_PCI |
079a136c | 107 | |
5e4b3361 | 108 | |
14d0a02a | 109 | #if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ |
6d0f6bcf JCPV |
110 | # define CONFIG_SYS_LOWBOOT 1 |
111 | # define CONFIG_SYS_LOWBOOT16 1 | |
5e4b3361 | 112 | #endif |
14d0a02a | 113 | #if (CONFIG_SYS_TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */ |
6d0f6bcf JCPV |
114 | # define CONFIG_SYS_LOWBOOT 1 |
115 | # define CONFIG_SYS_LOWBOOT08 1 | |
5e4b3361 SR |
116 | #endif |
117 | ||
118 | /* | |
119 | * Autobooting | |
120 | */ | |
121 | #define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ | |
122 | ||
123 | #define CONFIG_PREBOOT "echo;" \ | |
124 | "echo Welcome to ParaFinder pf5200;" \ | |
125 | "echo" | |
126 | ||
127 | #undef CONFIG_BOOTARGS | |
128 | ||
129 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
130 | "netdev=eth0\0" \ | |
131 | "flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \ | |
132 | "flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \ | |
fe126d8b WD |
133 | "net_vxworks=phypower 1;sleep 2;tftp ${loadaddr} ${image};run vxworks_args;bootvx\0" \ |
134 | "vxworks_args=setenv bootargs fec(0,0)${host}:${image} h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script}\0" \ | |
135 | "ata_vxworks_args=setenv bootargs /ata0/vxWorks h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script} o=fec0 \0" \ | |
5e4b3361 SR |
136 | "loadaddr=01000000\0" \ |
137 | "serverip=192.168.2.99\0" \ | |
138 | "gatewayip=10.0.0.79\0" \ | |
139 | "user=mu\0" \ | |
140 | "target=pf5200.esd\0" \ | |
141 | "script=pf5200.bat\0" \ | |
142 | "image=/tftpboot/vxWorks_pf5200\0" \ | |
143 | "ipaddr=10.0.13.196\0" \ | |
144 | "netmask=255.255.0.0\0" \ | |
145 | "" | |
146 | ||
147 | #define CONFIG_BOOTCOMMAND "run flash_vxworks0" | |
148 | ||
5e4b3361 SR |
149 | /* |
150 | * IPB Bus clocking configuration. | |
151 | */ | |
6d0f6bcf | 152 | #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ |
5e4b3361 SR |
153 | /* |
154 | * I2C configuration | |
155 | */ | |
156 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
6d0f6bcf | 157 | #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ |
5e4b3361 | 158 | |
6d0f6bcf JCPV |
159 | #define CONFIG_SYS_I2C_SPEED 86000 /* 100 kHz */ |
160 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
5e4b3361 SR |
161 | |
162 | /* | |
163 | * EEPROM configuration | |
164 | */ | |
6d0f6bcf JCPV |
165 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ |
166 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
167 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 | |
168 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 | |
169 | #define CONFIG_SYS_I2C_MULTI_EEPROMS 1 | |
5e4b3361 SR |
170 | /* |
171 | * Flash configuration | |
172 | */ | |
6d0f6bcf JCPV |
173 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 |
174 | #define CONFIG_SYS_FLASH_SIZE 0x02000000 | |
175 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00000000) | |
176 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ | |
177 | #define CONFIG_SYS_MAX_FLASH_SECT 512 | |
5e4b3361 | 178 | |
6d0f6bcf JCPV |
179 | #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ |
180 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ | |
5e4b3361 SR |
181 | |
182 | /* | |
183 | * Environment settings | |
184 | */ | |
185 | #if 1 /* test-only */ | |
5a1aceb0 | 186 | #define CONFIG_ENV_IS_IN_FLASH |
0e8d1586 JCPV |
187 | #define CONFIG_ENV_SIZE 0x10000 |
188 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
5e4b3361 SR |
189 | #define CONFIG_ENV_OVERWRITE 1 |
190 | #else | |
bb1f8b4f | 191 | #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
0e8d1586 JCPV |
192 | #define CONFIG_ENV_OFFSET 0x0000 /* environment starts at the beginning of the EEPROM */ |
193 | #define CONFIG_ENV_SIZE 0x0400 /* 8192 bytes may be used for env vars */ | |
5e4b3361 SR |
194 | /* total size of a CAT24WC32 is 8192 bytes */ |
195 | #define CONFIG_ENV_OVERWRITE 1 | |
196 | #endif | |
197 | ||
198 | /* | |
199 | * Memory map | |
200 | */ | |
6d0f6bcf JCPV |
201 | #define CONFIG_SYS_MBAR 0xF0000000 |
202 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 | |
203 | #define CONFIG_SYS_DEFAULT_MBAR 0x80000000 | |
5e4b3361 SR |
204 | |
205 | /* Use SRAM until RAM will be available */ | |
6d0f6bcf | 206 | #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM |
553f0982 | 207 | #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ |
5e4b3361 | 208 | |
25ddd1fb | 209 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 210 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
5e4b3361 | 211 | |
14d0a02a | 212 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf JCPV |
213 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
214 | # define CONFIG_SYS_RAMBOOT 1 | |
5e4b3361 SR |
215 | #endif |
216 | ||
6d0f6bcf JCPV |
217 | #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
218 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
219 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
5e4b3361 SR |
220 | |
221 | /* | |
222 | * Ethernet configuration | |
223 | */ | |
224 | #define CONFIG_MPC5xxx_FEC 1 | |
86321fc1 | 225 | #define CONFIG_MPC5xxx_FEC_MII100 |
5e4b3361 | 226 | /* |
86321fc1 | 227 | * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb |
5e4b3361 | 228 | */ |
86321fc1 | 229 | /* #define CONFIG_MPC5xxx_FEC_MII10 */ |
5e4b3361 SR |
230 | #define CONFIG_PHY_ADDR 0x00 |
231 | #define CONFIG_UDP_CHECKSUM 1 | |
232 | ||
233 | /* | |
234 | * GPIO configuration | |
235 | */ | |
6d0f6bcf | 236 | #define CONFIG_SYS_GPS_PORT_CONFIG 0x01052444 |
5e4b3361 SR |
237 | |
238 | /* | |
239 | * Miscellaneous configurable options | |
240 | */ | |
6d0f6bcf | 241 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
d794cfef | 242 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 243 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
5e4b3361 | 244 | #else |
6d0f6bcf | 245 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
5e4b3361 | 246 | #endif |
6d0f6bcf JCPV |
247 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
248 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
249 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
5e4b3361 | 250 | |
6d0f6bcf JCPV |
251 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
252 | #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ | |
5e4b3361 | 253 | |
6d0f6bcf | 254 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
5e4b3361 | 255 | |
6d0f6bcf | 256 | #define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */ |
5e4b3361 | 257 | |
6d0f6bcf | 258 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
d794cfef | 259 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 260 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
d794cfef JL |
261 | #endif |
262 | ||
5e4b3361 SR |
263 | /* |
264 | * Various low-level settings | |
265 | */ | |
6d0f6bcf JCPV |
266 | #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI |
267 | #define CONFIG_SYS_HID0_FINAL HID0_ICE | |
5e4b3361 | 268 | |
6d0f6bcf JCPV |
269 | #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE |
270 | #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE | |
271 | #define CONFIG_SYS_BOOTCS_CFG 0x0004DD00 | |
5e4b3361 | 272 | |
6d0f6bcf JCPV |
273 | #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE |
274 | #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE | |
5e4b3361 | 275 | |
6d0f6bcf JCPV |
276 | #define CONFIG_SYS_CS1_START 0xfd000000 |
277 | #define CONFIG_SYS_CS1_SIZE 0x00010000 | |
278 | #define CONFIG_SYS_CS1_CFG 0x10101410 | |
5e4b3361 | 279 | |
6d0f6bcf JCPV |
280 | #define CONFIG_SYS_CS_BURST 0x00000000 |
281 | #define CONFIG_SYS_CS_DEADCYCLE 0x33333333 | |
5e4b3361 | 282 | |
6d0f6bcf | 283 | #define CONFIG_SYS_RESET_ADDRESS 0xff000000 |
5e4b3361 SR |
284 | |
285 | /*----------------------------------------------------------------------- | |
286 | * USB stuff | |
287 | *----------------------------------------------------------------------- | |
288 | */ | |
289 | #define CONFIG_USB_CLOCK 0x0001BBBB | |
290 | #define CONFIG_USB_CONFIG 0x00001000 | |
291 | ||
292 | /*----------------------------------------------------------------------- | |
293 | * IDE/ATA stuff Supports IDE harddisk | |
294 | *----------------------------------------------------------------------- | |
295 | */ | |
296 | ||
297 | #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ | |
298 | ||
299 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
300 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
301 | ||
302 | #define CONFIG_IDE_RESET /* reset for ide supported */ | |
303 | #define CONFIG_IDE_PREINIT | |
304 | ||
6d0f6bcf JCPV |
305 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
306 | #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ | |
5e4b3361 | 307 | |
6d0f6bcf | 308 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
5e4b3361 | 309 | |
6d0f6bcf | 310 | #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA |
5e4b3361 SR |
311 | |
312 | /* Offset for data I/O */ | |
6d0f6bcf | 313 | #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) |
5e4b3361 SR |
314 | |
315 | /* Offset for normal register accesses */ | |
6d0f6bcf | 316 | #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) |
5e4b3361 SR |
317 | |
318 | /* Offset for alternate registers */ | |
6d0f6bcf | 319 | #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) |
5e4b3361 SR |
320 | |
321 | /* Interval between registers */ | |
6d0f6bcf | 322 | #define CONFIG_SYS_ATA_STRIDE 4 |
5e4b3361 SR |
323 | |
324 | /*----------------------------------------------------------------------- | |
325 | * CPLD stuff | |
326 | */ | |
6d0f6bcf JCPV |
327 | #define CONFIG_SYS_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */ |
328 | #define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */ | |
5e4b3361 SR |
329 | |
330 | /* CPLD program pin configuration */ | |
6d0f6bcf JCPV |
331 | #define CONFIG_SYS_FPGA_PRG 0x20000000 /* JTAG TMS pin (ppc output) */ |
332 | #define CONFIG_SYS_FPGA_CLK 0x10000000 /* JTAG TCK pin (ppc output) */ | |
333 | #define CONFIG_SYS_FPGA_DATA 0x20000000 /* JTAG TDO->TDI data pin (ppc output) */ | |
334 | #define CONFIG_SYS_FPGA_DONE 0x10000000 /* JTAG TDI->TDO pin (ppc input) */ | |
5e4b3361 | 335 | |
6d0f6bcf JCPV |
336 | #define JTAG_GPIO_ADDR_TMS (CONFIG_SYS_MBAR + 0xB10) /* JTAG TMS pin (GPS data out value reg.) */ |
337 | #define JTAG_GPIO_ADDR_TCK (CONFIG_SYS_MBAR + 0xC0C) /* JTAG TCK pin (GPW data out value reg.) */ | |
338 | #define JTAG_GPIO_ADDR_TDI (CONFIG_SYS_MBAR + 0xC0C) /* JTAG TDO->TDI pin (GPW data out value reg.) */ | |
339 | #define JTAG_GPIO_ADDR_TDO (CONFIG_SYS_MBAR + 0xB14) /* JTAG TDI->TDO pin (GPS data in value reg.) */ | |
5e4b3361 | 340 | |
6d0f6bcf | 341 | #define JTAG_GPIO_ADDR_CFG (CONFIG_SYS_MBAR + 0xB00) |
5e4b3361 SR |
342 | #define JTAG_GPIO_CFG_SET 0x00000000 |
343 | #define JTAG_GPIO_CFG_RESET 0x00F00000 | |
344 | ||
6d0f6bcf | 345 | #define JTAG_GPIO_ADDR_EN_TMS (CONFIG_SYS_MBAR + 0xB04) |
5e4b3361 SR |
346 | #define JTAG_GPIO_TMS_EN_SET 0x20000000 /* Enable for GPIO */ |
347 | #define JTAG_GPIO_TMS_EN_RESET 0x00000000 | |
6d0f6bcf | 348 | #define JTAG_GPIO_ADDR_DDR_TMS (CONFIG_SYS_MBAR + 0xB0C) |
5e4b3361 SR |
349 | #define JTAG_GPIO_TMS_DDR_SET 0x20000000 /* Set as output */ |
350 | #define JTAG_GPIO_TMS_DDR_RESET 0x00000000 | |
351 | ||
6d0f6bcf | 352 | #define JTAG_GPIO_ADDR_EN_TCK (CONFIG_SYS_MBAR + 0xC00) |
5e4b3361 SR |
353 | #define JTAG_GPIO_TCK_EN_SET 0x20000000 /* Enable for GPIO */ |
354 | #define JTAG_GPIO_TCK_EN_RESET 0x00000000 | |
6d0f6bcf | 355 | #define JTAG_GPIO_ADDR_DDR_TCK (CONFIG_SYS_MBAR + 0xC08) |
5e4b3361 SR |
356 | #define JTAG_GPIO_TCK_DDR_SET 0x20000000 /* Set as output */ |
357 | #define JTAG_GPIO_TCK_DDR_RESET 0x00000000 | |
358 | ||
6d0f6bcf | 359 | #define JTAG_GPIO_ADDR_EN_TDI (CONFIG_SYS_MBAR + 0xC00) |
5e4b3361 SR |
360 | #define JTAG_GPIO_TDI_EN_SET 0x10000000 /* Enable as GPIO */ |
361 | #define JTAG_GPIO_TDI_EN_RESET 0x00000000 | |
6d0f6bcf | 362 | #define JTAG_GPIO_ADDR_DDR_TDI (CONFIG_SYS_MBAR + 0xC08) |
5e4b3361 SR |
363 | #define JTAG_GPIO_TDI_DDR_SET 0x10000000 /* Set as output */ |
364 | #define JTAG_GPIO_TDI_DDR_RESET 0x00000000 | |
365 | ||
6d0f6bcf | 366 | #define JTAG_GPIO_ADDR_EN_TDO (CONFIG_SYS_MBAR + 0xB04) |
5e4b3361 SR |
367 | #define JTAG_GPIO_TDO_EN_SET 0x10000000 /* Enable as GPIO */ |
368 | #define JTAG_GPIO_TDO_EN_RESET 0x00000000 | |
6d0f6bcf | 369 | #define JTAG_GPIO_ADDR_DDR_TDO (CONFIG_SYS_MBAR + 0xB0C) |
5e4b3361 SR |
370 | #define JTAG_GPIO_TDO_DDR_SET 0x00000000 |
371 | #define JTAG_GPIO_TDO_DDR_RESET 0x10000000 /* Set as input */ | |
372 | ||
373 | #endif /* __CONFIG_H */ |