[people/ms/u-boot.git] / include / configs / ppmc7xx.h

/*
 * ppmc7xx.h
 * ---------
 *
 * Wind River PPMC 7xx/74xx board configuration file.
 *
 * By Richard Danter (richard.danter@windriver.com)
 * Copyright (C) 2005 Wind River Systems
 */


#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_PPMC7XX


/*===================================================================
 *
 * User configurable settings - Modify to your preference
 *
 *===================================================================
 */

/*
 * Debug
 *
 * DEBUG		- Define this is you want extra debug info
 * GTREGREAD		- Required to build with debug
 * do_bdinfo		- Required to build with debug
 */

#ifdef	DEBUG
#define	GTREGREAD(x)	0xFFFFFFFF
#define	do_bdinfo(a,b,c,d)
#endif

/*
 * CPU type
 *
 * CONFIG_7xx		- We have a 750 or 755 CPU
 * CONFIG_74xx		- We have a 7400 CPU
 * CONFIG_ALTIVEC	- We have altivec enabled CPU (only 7400)
 * CONFIG_BUS_CLK	- System bus clock in Hz
 */

#define	CONFIG_7xx
#undef	CONFIG_74xx
#undef	CONFIG_ALTIVEC
#define CONFIG_BUS_CLK	66000000

#define	CONFIG_SYS_TEXT_BASE	0xFFF00000

#ifndef __ASSEMBLY__
#include <galileo/core.h>
#endif

/*
 * Monitor configuration
 *
 * List of command sets to include in shell
 *
 * The following command sets have been tested and known to work:
 *
 * CMD_CACHE		- Cache control commands
 * CMD_MEMORY		- Memory display, change and test commands
 * CMD_FLASH		- Erase and program flash
 * CMD_ENV		- Environment commands
 * CMD_RUN		- Run commands stored in env vars
 * CMD_ELF		- Load ELF files
 * CMD_NET		- Networking/file download commands
 * CMD_PIN		- ICMP Echo Request command
 * CMD_PCI		- PCI Bus scanning command
 */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_FLASH
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_RUN
#define CONFIG_CMD_ELF
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_PCI

#undef CONFIG_CMD_KGDB


/*
 * Serial configuration
 *
 * CONFIG_CONS_INDEX		- Serial console port number (COM1)
 * CONFIG_BAUDRATE		- Serial speed
 */

#define CONFIG_CONS_INDEX	1
#define CONFIG_BAUDRATE		9600


/*
 * PCI config
 *
 * CONFIG_PCI			- Enable PCI bus
 * CONFIG_PCI_PNP		- Enable Plug & Play support
 * CONFIG_PCI_SCAN_SHOW		- Enable display of devices at startup
 */

#define	CONFIG_PCI
#define	CONFIG_PCI_INDIRECT_BRIDGE
#define	CONFIG_PCI_PNP
#undef	CONFIG_PCI_SCAN_SHOW


/*
 * Network config
 *
 * CONFIG_EEPRO100		- Intel 8255x Ethernet Controller
 * CONFIG_EEPRO100_SROM_WRITE	- Enable writing to network card ROM
 */

#define	CONFIG_EEPRO100
#define	CONFIG_EEPRO100_SROM_WRITE


/*
 * Enable extra init functions
 *
 * CONFIG_MISC_INIT_F		- Call pre-relocation init functions
 * CONFIG_MISC_INIT_R		- Call post relocation init functions
 */

#undef	CONFIG_MISC_INIT_F
#define CONFIG_MISC_INIT_R


/*
 * Boot config
 *
 * CONFIG_BOOTCOMMAND		- Command(s) to execute to auto-boot
 * CONFIG_BOOTDELAY		- How long to wait before auto-boot (in sec)
 */

#define CONFIG_BOOTCOMMAND		\
	"bootp;" \
	"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
	"bootm"
#define CONFIG_BOOTDELAY		5


/*===================================================================
 *
 * Board configuration settings - You should not need to modify these
 *
 *===================================================================
 */


/*
 * Memory map
 *
 * This board runs in a standard CHRP (Map-B) configuration.
 *
 *	Type	    Start	End	    Size    Width   Chip Sel
 *	----------- ----------- ----------- ------- ------- --------
 *	SDRAM	    0x00000000	0x04000000  64MB    64b	    SDRAMCS0
 *	User LED's  0x78000000				    RCS3
 *	UART	    0x7C000000				    RCS2
 *	Mailbox	    0xFF000000				    RCS1
 *	Flash	    0xFFC00000	0xFFFFFFFF   4MB    64b	    RCS0
 *
 * Flash sectors are laid out as follows.
 *
 *	Sector	Start		End	Size	Comments
 *	------- ----------- ----------- ------- -----------
 *	 0	0xFFC00000  0xFFC3FFFF	256KB
 *	 1	0xFFC40000  0xFFC7FFFF	256KB
 *	 2	0xFFC80000  0xFFCBFFFF	256KB
 *	 3	0xFFCC0000  0xFFCFFFFF	256KB
 *	 4	0xFFD00000  0xFFD3FFFF	256KB
 *	 5	0xFFD40000  0xFFD7FFFF	256KB
 *	 6	0xFFD80000  0xFFDBFFFF	256KB
 *	 7	0xFFDC0000  0xFFDFFFFF	256KB
 *	 8	0xFFE00000  0xFFE3FFFF	256KB
 *	 9	0xFFE40000  0xFFE7FFFF	256KB
 *	10	0xFFE80000  0xFFEBFFFF	256KB
 *	11	0xFFEC0000  0xFFEFFFFF	256KB
 *	12	0xFFF00000  0xFFF3FFFF	256KB	U-Boot code here
 *	13	0xFFF40000  0xFFF7FFFF	256KB
 *	14	0xFFF80000  0xFFFBFFFF	256KB
 *	15	0xFFFC0000  0xFFFDFFFF	128KB
 *	16	0xFFFE0000  0xFFFE7FFF	 32KB	U-Boot env vars here
 *	17	0xFFFE8000  0xFFFEFFFF	 32KB	U-Boot backup copy of env vars here
 *	18	0xFFFF0000  0xFFFFFFFF	 64KB
 */


/*
 * SDRAM config - see memory map details above.
 *
 * CONFIG_SYS_SDRAM_BASE		- Start address of SDRAM, this _must_ be zero!
 * CONFIG_SYS_SDRAM_SIZE		- Total size of contiguous SDRAM bank(s)
 */

#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_SDRAM_SIZE		0x04000000


/*
 * Flash config - see memory map details above.
 *
 * CONFIG_SYS_FLASH_BASE		- Start address of flash memory
 * CONFIG_SYS_FLASH_SIZE		- Total size of contiguous flash mem
 * CONFIG_SYS_FLASH_ERASE_TOUT		- Erase timeout in ms
 * CONFIG_SYS_FLASH_WRITE_TOUT		- Write timeout in ms
 * CONFIG_SYS_MAX_FLASH_BANKS		- Number of banks of flash on board
 * CONFIG_SYS_MAX_FLASH_SECT		- Number of sectors in a bank
 */

#define CONFIG_SYS_FLASH_BASE		0xFFC00000
#define CONFIG_SYS_FLASH_SIZE		0x00400000
#define CONFIG_SYS_FLASH_ERASE_TOUT	250000
#define CONFIG_SYS_FLASH_WRITE_TOUT	5000
#define CONFIG_SYS_MAX_FLASH_BANKS	1
#define CONFIG_SYS_MAX_FLASH_SECT	128


/*
 * Monitor config - see memory map details above
 *
 * CONFIG_SYS_MONITOR_BASE		- Base address of monitor code
 * CONFIG_SYS_MALLOC_LEN		- Size of malloc pool (128KB)
 */

#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MALLOC_LEN		0x20000


/*
 * Command shell settings
 *
 * CONFIG_SYS_BARGSIZE			- Boot Argument buffer size
 * CONFIG_SYS_BOOTMAPSZ		- Size of app's mapped RAM at boot (Linux=8MB)
 * CONFIG_SYS_CBSIZE			- Console Buffer (input) size
 * CONFIG_SYS_LOAD_ADDR		- Default load address
 * CONFIG_SYS_LONGHELP			- Provide more detailed help
 * CONFIG_SYS_MAXARGS			- Number of args accepted by monitor commands
 * CONFIG_SYS_MEMTEST_START		- Start address of test to run on RAM
 * CONFIG_SYS_MEMTEST_END		- End address of RAM test
 * CONFIG_SYS_PBSIZE			- Print Buffer (output) size
 * CONFIG_SYS_PROMPT			- Prompt string
 */

#define CONFIG_SYS_BARGSIZE		1024
#define CONFIG_SYS_BOOTMAPSZ		0x800000
#define CONFIG_SYS_CBSIZE		1024
#define CONFIG_SYS_LOAD_ADDR		0x100000
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_MAXARGS		16
#define CONFIG_SYS_MEMTEST_START	0x00040000
#define CONFIG_SYS_MEMTEST_END		0x00040100
#define CONFIG_SYS_PBSIZE		1024


/*
 * Environment config - see memory map details above
 *
 * CONFIG_ENV_IS_IN_FLASH		- The env variables are stored in flash
 * CONFIG_ENV_ADDR			- Address of the sector containing env vars
 * CONFIG_ENV_SIZE			- Ammount of RAM for env vars (used to save RAM, 4KB)
 * CONFIG_ENV_SECT_SIZE		- Size of sector containing env vars (32KB)
 */

#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_ADDR		0xFFFE0000
#define CONFIG_ENV_SIZE		0x1000
#define CONFIG_ENV_ADDR_REDUND	0xFFFE8000
#define CONFIG_ENV_SIZE_REDUND	0x1000
#define CONFIG_ENV_SECT_SIZE	0x8000


/*
 * Initial RAM config
 *
 * Since the main system RAM is initialised very early, we place the INIT_RAM
 * in the main system RAM just above the exception vectors. The contents are
 * copied to top of RAM by the init code.
 *
 * CONFIG_SYS_INIT_RAM_ADDR		- Address of Init RAM, above exception vect
 * CONFIG_SYS_INIT_RAM_SIZE		- Size of Init RAM
 * GENERATED_GBL_DATA_SIZE		- Ammount of RAM to reserve for global data
 * CONFIG_SYS_GBL_DATA_OFFSET		- Start of global data, top of stack
 */

#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_SDRAM_BASE + 0x4000)
#define CONFIG_SYS_INIT_RAM_SIZE	0x4000
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)


/*
 * Initial BAT config
 *
 * BAT0	- System SDRAM
 * BAT1 - LED's and Serial Port
 * BAT2 - PCI Memory
 * BAT3 - PCI I/O including Flash Memory
 */

#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U

#define CONFIG_SYS_IBAT1L (0x70000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT1L (0x70000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)

#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT2L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)

#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT3L (0xF0000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)


/*
 * Cache config
 *
 * CONFIG_SYS_CACHELINE_SIZE		- Size of a cache line (CPU specific)
 * CONFIG_SYS_L2			- L2 cache enabled if defined
 * L2_INIT			- L2 cache init flags
 * L2_ENABLE			- L2 cache enable flags
 */

#define CONFIG_SYS_CACHELINE_SIZE	32
#undef	CONFIG_SYS_L2
#define L2_INIT			0
#define L2_ENABLE		0


/*
 * Clocks config
 *
 * CONFIG_SYS_BUS_CLK			- Bus clock frequency in Hz
 * CONFIG_SYS_HZ			- Decrementer freq in Hz
 */

#define CONFIG_SYS_BUS_CLK		CONFIG_BUS_CLK


/*
 * Serial port config
 *
 * CONFIG_SYS_NS16550			- Include the NS16550 driver
 * CONFIG_SYS_NS16550_SERIAL		- Include the serial (wrapper) driver
 * CONFIG_SYS_NS16550_CLK		- Frequency of reference clock
 * CONFIG_SYS_NS16550_REG_SIZE		- 64-bit accesses to 8-bit port
 * CONFIG_SYS_NS16550_COM1		- Base address of 1st serial port
 */

#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_CLK		3686400
#define CONFIG_SYS_NS16550_REG_SIZE	-8
#define CONFIG_SYS_NS16550_COM1	0x7C000000


/*
 * PCI Config - Address Map B (CHRP)
 */

#define CONFIG_SYS_PCI_MEMORY_BUS	0x00000000
#define CONFIG_SYS_PCI_MEMORY_PHYS	0x00000000
#define CONFIG_SYS_PCI_MEMORY_SIZE	0x40000000
#define CONFIG_SYS_PCI_MEM_BUS		0x80000000
#define CONFIG_SYS_PCI_MEM_PHYS	0x80000000
#define CONFIG_SYS_PCI_MEM_SIZE	0x7D000000
#define CONFIG_SYS_ISA_MEM_BUS		0x00000000
#define CONFIG_SYS_ISA_MEM_PHYS	0xFD000000
#define CONFIG_SYS_ISA_MEM_SIZE	0x01000000
#define CONFIG_SYS_PCI_IO_BUS		0x00800000
#define CONFIG_SYS_PCI_IO_PHYS		0xFE800000
#define CONFIG_SYS_PCI_IO_SIZE		0x00400000
#define CONFIG_SYS_ISA_IO_BUS		0x00000000
#define CONFIG_SYS_ISA_IO_PHYS		0xFE000000
#define CONFIG_SYS_ISA_IO_SIZE		0x00800000
#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_ISA_IO_PHYS
#define CONFIG_SYS_ISA_IO		CONFIG_SYS_ISA_IO_PHYS
#define CONFIG_SYS_60X_PCI_IO_OFFSET	CONFIG_SYS_ISA_IO_PHYS


/*
 * Extra init functions
 *
 * CONFIG_SYS_BOARD_ASM_INIT		- Call assembly init code
 */

#define CONFIG_SYS_BOARD_ASM_INIT

#endif /* __CONFIG_H */
Commit	Line	Data
f5e0d039 HS	1	/*
	2	* ppmc7xx.h
	3	* ---------
b87dfd28	4	*
f5e0d039	5	* Wind River PPMC 7xx/74xx board configuration file.
b87dfd28	6	*
f5e0d039 HS	7	* By Richard Danter (richard.danter@windriver.com)
	8	* Copyright (C) 2005 Wind River Systems
	9	*/
	10
	11
	12	#ifndef __CONFIG_H
	13	#define __CONFIG_H
	14
	15	#define CONFIG_PPMC7XX
	16
	17
	18	/*===================================================================
b87dfd28	19	*
f5e0d039	20	* User configurable settings - Modify to your preference
b87dfd28	21	*
f5e0d039 HS	22	*===================================================================
	23	*/
	24
	25	/*
	26	* Debug
b87dfd28	27	*
cdd917a4 WD	28	* DEBUG - Define this is you want extra debug info
	29	* GTREGREAD - Required to build with debug
	30	* do_bdinfo - Required to build with debug
f5e0d039 HS	31	*/
f5e0d039 HS	32
cdd917a4 WD	33	#ifdef DEBUG
cdd917a4 WD	34	#define GTREGREAD(x) 0xFFFFFFFF
f5e0d039	35	#define do_bdinfo(a,b,c,d)
cdd917a4	36	#endif
f5e0d039 HS	37
	38	/*
	39	* CPU type
b87dfd28	40	*
cdd917a4 WD	41	* CONFIG_7xx - We have a 750 or 755 CPU
	42	* CONFIG_74xx - We have a 7400 CPU
	43	* CONFIG_ALTIVEC - We have altivec enabled CPU (only 7400)
	44	* CONFIG_BUS_CLK - System bus clock in Hz
f5e0d039 HS	45	*/
	46
	47	#define CONFIG_7xx
	48	#undef CONFIG_74xx
	49	#undef CONFIG_ALTIVEC
cdd917a4	50	#define CONFIG_BUS_CLK 66000000
f5e0d039	51
2ae18241	52	#define CONFIG_SYS_TEXT_BASE 0xFFF00000
f5e0d039	53
0aa27657 MV	54	#ifndef __ASSEMBLY__
	55	#include <galileo/core.h>
	56	#endif
	57
f5e0d039 HS	58	/*
f5e0d039 HS	59	* Monitor configuration
b87dfd28	60	*
26a34560	61	* List of command sets to include in shell
b87dfd28	62	*
f5e0d039	63	* The following command sets have been tested and known to work:
b87dfd28	64	*
26a34560 JL	65	* CMD_CACHE - Cache control commands
	66	* CMD_MEMORY - Memory display, change and test commands
	67	* CMD_FLASH - Erase and program flash
	68	* CMD_ENV - Environment commands
	69	* CMD_RUN - Run commands stored in env vars
	70	* CMD_ELF - Load ELF files
	71	* CMD_NET - Networking/file download commands
	72	* CMD_PIN - ICMP Echo Request command
	73	* CMD_PCI - PCI Bus scanning command
f5e0d039 HS	74	*/
f5e0d039 HS	75
079a136c JL	76	/*
	77	* BOOTP options
	78	*/
	79	#define CONFIG_BOOTP_BOOTFILESIZE
	80	#define CONFIG_BOOTP_BOOTPATH
	81	#define CONFIG_BOOTP_GATEWAY
	82	#define CONFIG_BOOTP_HOSTNAME
	83
	84
26a34560 JL	85	/*
	86	* Command line configuration.
	87	*/
	88	#include <config_cmd_default.h>
	89
	90	#define CONFIG_CMD_FLASH
bdab39d3	91	#define CONFIG_CMD_SAVEENV
26a34560 JL	92	#define CONFIG_CMD_RUN
	93	#define CONFIG_CMD_ELF
	94	#define CONFIG_CMD_NET
	95	#define CONFIG_CMD_PING
	96	#define CONFIG_CMD_PCI
	97
	98	#undef CONFIG_CMD_KGDB
f5e0d039 HS	99
	100
	101	/*
	102	* Serial configuration
	103	*
	104	* CONFIG_CONS_INDEX - Serial console port number (COM1)
cdd917a4	105	* CONFIG_BAUDRATE - Serial speed
f5e0d039 HS	106	*/
f5e0d039 HS	107
cdd917a4 WD	108	#define CONFIG_CONS_INDEX 1
cdd917a4 WD	109	#define CONFIG_BAUDRATE 9600
f5e0d039 HS	110
	111
	112	/*
	113	* PCI config
b87dfd28	114	*
cdd917a4 WD	115	* CONFIG_PCI - Enable PCI bus
cdd917a4 WD	116	* CONFIG_PCI_PNP - Enable Plug & Play support
f5e0d039 HS	117	* CONFIG_PCI_SCAN_SHOW - Enable display of devices at startup
	118	*/
	119
	120	#define CONFIG_PCI
842033e6	121	#define CONFIG_PCI_INDIRECT_BRIDGE
f5e0d039 HS	122	#define CONFIG_PCI_PNP
	123	#undef CONFIG_PCI_SCAN_SHOW
	124
	125
	126	/*
	127	* Network config
b87dfd28	128	*
cdd917a4 WD	129	* CONFIG_EEPRO100 - Intel 8255x Ethernet Controller
cdd917a4 WD	130	* CONFIG_EEPRO100_SROM_WRITE - Enable writing to network card ROM
f5e0d039 HS	131	*/
f5e0d039 HS	132
f5e0d039 HS	133	#define CONFIG_EEPRO100
	134	#define CONFIG_EEPRO100_SROM_WRITE
	135
	136
	137	/*
	138	* Enable extra init functions
b87dfd28	139	*
f5e0d039 HS	140	* CONFIG_MISC_INIT_F - Call pre-relocation init functions
	141	* CONFIG_MISC_INIT_R - Call post relocation init functions
	142	*/
	143
	144	#undef CONFIG_MISC_INIT_F
b87dfd28	145	#define CONFIG_MISC_INIT_R
f5e0d039 HS	146
	147
	148	/*
	149	* Boot config
b87dfd28	150	*
f5e0d039	151	* CONFIG_BOOTCOMMAND - Command(s) to execute to auto-boot
cdd917a4	152	* CONFIG_BOOTDELAY - How long to wait before auto-boot (in sec)
f5e0d039 HS	153	*/
	154
	155	#define CONFIG_BOOTCOMMAND \
	156	"bootp;" \
	157	"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
	158	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
	159	"bootm"
	160	#define CONFIG_BOOTDELAY 5
	161
	162
	163	/*===================================================================
b87dfd28	164	*
f5e0d039	165	* Board configuration settings - You should not need to modify these
b87dfd28	166	*
f5e0d039 HS	167	*===================================================================
	168	*/
	169
	170
f5e0d039 HS	171	/*
f5e0d039 HS	172	* Memory map
b87dfd28	173	*
f5e0d039	174	* This board runs in a standard CHRP (Map-B) configuration.
b87dfd28	175	*
cdd917a4	176	* Type Start End Size Width Chip Sel
f5e0d039	177	* ----------- ----------- ----------- ------- ------- --------
cdd917a4 WD	178	* SDRAM 0x00000000 0x04000000 64MB 64b SDRAMCS0
	179	* User LED's 0x78000000 RCS3
	180	* UART 0x7C000000 RCS2
	181	* Mailbox 0xFF000000 RCS1
	182	* Flash 0xFFC00000 0xFFFFFFFF 4MB 64b RCS0
b87dfd28	183	*
f5e0d039	184	* Flash sectors are laid out as follows.
b87dfd28	185	*
cdd917a4	186	* Sector Start End Size Comments
f5e0d039	187	* ------- ----------- ----------- ------- -----------
cdd917a4 WD	188	* 0 0xFFC00000 0xFFC3FFFF 256KB
	189	* 1 0xFFC40000 0xFFC7FFFF 256KB
	190	* 2 0xFFC80000 0xFFCBFFFF 256KB
	191	* 3 0xFFCC0000 0xFFCFFFFF 256KB
	192	* 4 0xFFD00000 0xFFD3FFFF 256KB
	193	* 5 0xFFD40000 0xFFD7FFFF 256KB
	194	* 6 0xFFD80000 0xFFDBFFFF 256KB
	195	* 7 0xFFDC0000 0xFFDFFFFF 256KB
	196	* 8 0xFFE00000 0xFFE3FFFF 256KB
	197	* 9 0xFFE40000 0xFFE7FFFF 256KB
	198	* 10 0xFFE80000 0xFFEBFFFF 256KB
	199	* 11 0xFFEC0000 0xFFEFFFFF 256KB
	200	* 12 0xFFF00000 0xFFF3FFFF 256KB U-Boot code here
	201	* 13 0xFFF40000 0xFFF7FFFF 256KB
	202	* 14 0xFFF80000 0xFFFBFFFF 256KB
	203	* 15 0xFFFC0000 0xFFFDFFFF 128KB
	204	* 16 0xFFFE0000 0xFFFE7FFF 32KB U-Boot env vars here
	205	* 17 0xFFFE8000 0xFFFEFFFF 32KB U-Boot backup copy of env vars here
	206	* 18 0xFFFF0000 0xFFFFFFFF 64KB
f5e0d039 HS	207	*/
	208
	209
	210	/*
	211	* SDRAM config - see memory map details above.
b87dfd28	212	*
6d0f6bcf JCPV	213	* CONFIG_SYS_SDRAM_BASE - Start address of SDRAM, this _must_ be zero!
6d0f6bcf JCPV	214	* CONFIG_SYS_SDRAM_SIZE - Total size of contiguous SDRAM bank(s)
f5e0d039 HS	215	*/
f5e0d039 HS	216
6d0f6bcf JCPV	217	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	218	#define CONFIG_SYS_SDRAM_SIZE 0x04000000
f5e0d039 HS	219
f5e0d039 HS	220
b87dfd28	221	/*
f5e0d039	222	* Flash config - see memory map details above.
b87dfd28	223	*
6d0f6bcf JCPV	224	* CONFIG_SYS_FLASH_BASE - Start address of flash memory
	225	* CONFIG_SYS_FLASH_SIZE - Total size of contiguous flash mem
	226	* CONFIG_SYS_FLASH_ERASE_TOUT - Erase timeout in ms
	227	* CONFIG_SYS_FLASH_WRITE_TOUT - Write timeout in ms
	228	* CONFIG_SYS_MAX_FLASH_BANKS - Number of banks of flash on board
	229	* CONFIG_SYS_MAX_FLASH_SECT - Number of sectors in a bank
f5e0d039 HS	230	*/
f5e0d039 HS	231
6d0f6bcf JCPV	232	#define CONFIG_SYS_FLASH_BASE 0xFFC00000
	233	#define CONFIG_SYS_FLASH_SIZE 0x00400000
	234	#define CONFIG_SYS_FLASH_ERASE_TOUT 250000
	235	#define CONFIG_SYS_FLASH_WRITE_TOUT 5000
	236	#define CONFIG_SYS_MAX_FLASH_BANKS 1
8cf69553	237	#define CONFIG_SYS_MAX_FLASH_SECT 128
f5e0d039 HS	238
	239
	240	/*
	241	* Monitor config - see memory map details above
b87dfd28	242	*
6d0f6bcf JCPV	243	* CONFIG_SYS_MONITOR_BASE - Base address of monitor code
6d0f6bcf JCPV	244	* CONFIG_SYS_MALLOC_LEN - Size of malloc pool (128KB)
f5e0d039 HS	245	*/
f5e0d039 HS	246
14d0a02a	247	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf	248	#define CONFIG_SYS_MALLOC_LEN 0x20000
f5e0d039 HS	249
	250
	251	/*
	252	* Command shell settings
b87dfd28	253	*
6d0f6bcf JCPV	254	* CONFIG_SYS_BARGSIZE - Boot Argument buffer size
	255	* CONFIG_SYS_BOOTMAPSZ - Size of app's mapped RAM at boot (Linux=8MB)
	256	* CONFIG_SYS_CBSIZE - Console Buffer (input) size
	257	* CONFIG_SYS_LOAD_ADDR - Default load address
	258	* CONFIG_SYS_LONGHELP - Provide more detailed help
	259	* CONFIG_SYS_MAXARGS - Number of args accepted by monitor commands
	260	* CONFIG_SYS_MEMTEST_START - Start address of test to run on RAM
	261	* CONFIG_SYS_MEMTEST_END - End address of RAM test
	262	* CONFIG_SYS_PBSIZE - Print Buffer (output) size
	263	* CONFIG_SYS_PROMPT - Prompt string
f5e0d039 HS	264	*/
f5e0d039 HS	265
6d0f6bcf JCPV	266	#define CONFIG_SYS_BARGSIZE 1024
	267	#define CONFIG_SYS_BOOTMAPSZ 0x800000
	268	#define CONFIG_SYS_CBSIZE 1024
	269	#define CONFIG_SYS_LOAD_ADDR 0x100000
	270	#define CONFIG_SYS_LONGHELP
	271	#define CONFIG_SYS_MAXARGS 16
	272	#define CONFIG_SYS_MEMTEST_START 0x00040000
	273	#define CONFIG_SYS_MEMTEST_END 0x00040100
	274	#define CONFIG_SYS_PBSIZE 1024
f5e0d039 HS	275
	276
	277	/*
	278	* Environment config - see memory map details above
b87dfd28	279	*
5a1aceb0	280	* CONFIG_ENV_IS_IN_FLASH - The env variables are stored in flash
0e8d1586 JCPV	281	* CONFIG_ENV_ADDR - Address of the sector containing env vars
	282	* CONFIG_ENV_SIZE - Ammount of RAM for env vars (used to save RAM, 4KB)
	283	* CONFIG_ENV_SECT_SIZE - Size of sector containing env vars (32KB)
f5e0d039 HS	284	*/
f5e0d039 HS	285
5a1aceb0	286	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	287	#define CONFIG_ENV_ADDR 0xFFFE0000
	288	#define CONFIG_ENV_SIZE 0x1000
	289	#define CONFIG_ENV_ADDR_REDUND 0xFFFE8000
	290	#define CONFIG_ENV_SIZE_REDUND 0x1000
	291	#define CONFIG_ENV_SECT_SIZE 0x8000
f5e0d039 HS	292
	293
	294	/*
	295	* Initial RAM config
	296	*
	297	* Since the main system RAM is initialised very early, we place the INIT_RAM
	298	* in the main system RAM just above the exception vectors. The contents are
	299	* copied to top of RAM by the init code.
b87dfd28	300	*
6d0f6bcf	301	* CONFIG_SYS_INIT_RAM_ADDR - Address of Init RAM, above exception vect
553f0982	302	* CONFIG_SYS_INIT_RAM_SIZE - Size of Init RAM
25ddd1fb	303	* GENERATED_GBL_DATA_SIZE - Ammount of RAM to reserve for global data
6d0f6bcf	304	* CONFIG_SYS_GBL_DATA_OFFSET - Start of global data, top of stack
f5e0d039 HS	305	*/
f5e0d039 HS	306
6d0f6bcf	307	#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4000)
553f0982	308	#define CONFIG_SYS_INIT_RAM_SIZE 0x4000
25ddd1fb	309	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
f5e0d039 HS	310
	311
	312	/*
	313	* Initial BAT config
b87dfd28	314	*
f5e0d039 HS	315	* BAT0 - System SDRAM
	316	* BAT1 - LED's and Serial Port
	317	* BAT2 - PCI Memory
	318	* BAT3 - PCI I/O including Flash Memory
	319	*/
	320
6d0f6bcf JCPV	321	#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \| BATL_PP_10 \| BATL_MEMCOHERENCE)
	322	#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \| BATU_BL_64M \| BATU_VS \| BATU_VP)
	323	#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
	324	#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
f5e0d039	325
6d0f6bcf JCPV	326	#define CONFIG_SYS_IBAT1L (0x70000000 \| BATL_PP_RW \| BATL_CACHEINHIBIT)
	327	#define CONFIG_SYS_IBAT1U (0x70000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	328	#define CONFIG_SYS_DBAT1L (0x70000000 \| BATL_PP_RW \| BATL_CACHEINHIBIT \| BATL_GUARDEDSTORAGE)
	329	#define CONFIG_SYS_DBAT1U (0x70000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
f5e0d039	330
6d0f6bcf JCPV	331	#define CONFIG_SYS_IBAT2L (0x80000000 \| BATL_PP_RW \| BATL_CACHEINHIBIT)
	332	#define CONFIG_SYS_IBAT2U (0x80000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	333	#define CONFIG_SYS_DBAT2L (0x80000000 \| BATL_PP_RW \| BATL_CACHEINHIBIT \| BATL_GUARDEDSTORAGE)
	334	#define CONFIG_SYS_DBAT2U (0x80000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
f5e0d039	335
6d0f6bcf JCPV	336	#define CONFIG_SYS_IBAT3L (0xF0000000 \| BATL_PP_RW \| BATL_CACHEINHIBIT)
	337	#define CONFIG_SYS_IBAT3U (0xF0000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	338	#define CONFIG_SYS_DBAT3L (0xF0000000 \| BATL_PP_RW \| BATL_CACHEINHIBIT \| BATL_GUARDEDSTORAGE)
	339	#define CONFIG_SYS_DBAT3U (0xF0000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
f5e0d039 HS	340
	341
	342	/*
	343	* Cache config
b87dfd28	344	*
6d0f6bcf JCPV	345	* CONFIG_SYS_CACHELINE_SIZE - Size of a cache line (CPU specific)
6d0f6bcf JCPV	346	* CONFIG_SYS_L2 - L2 cache enabled if defined
cdd917a4 WD	347	* L2_INIT - L2 cache init flags
cdd917a4 WD	348	* L2_ENABLE - L2 cache enable flags
f5e0d039 HS	349	*/
f5e0d039 HS	350
6d0f6bcf JCPV	351	#define CONFIG_SYS_CACHELINE_SIZE 32
6d0f6bcf JCPV	352	#undef CONFIG_SYS_L2
cdd917a4 WD	353	#define L2_INIT 0
cdd917a4 WD	354	#define L2_ENABLE 0
f5e0d039 HS	355
	356
	357	/*
	358	* Clocks config
b87dfd28	359	*
ee80fa7b	360	* CONFIG_SYS_BUS_CLK - Bus clock frequency in Hz
6d0f6bcf	361	* CONFIG_SYS_HZ - Decrementer freq in Hz
f5e0d039 HS	362	*/
f5e0d039 HS	363
6d0f6bcf	364	#define CONFIG_SYS_BUS_CLK CONFIG_BUS_CLK
f5e0d039 HS	365
	366
	367	/*
	368	* Serial port config
b87dfd28	369	*
6d0f6bcf JCPV	370	* CONFIG_SYS_NS16550 - Include the NS16550 driver
	371	* CONFIG_SYS_NS16550_SERIAL - Include the serial (wrapper) driver
	372	* CONFIG_SYS_NS16550_CLK - Frequency of reference clock
	373	* CONFIG_SYS_NS16550_REG_SIZE - 64-bit accesses to 8-bit port
	374	* CONFIG_SYS_NS16550_COM1 - Base address of 1st serial port
f5e0d039 HS	375	*/
f5e0d039 HS	376
6d0f6bcf JCPV	377	#define CONFIG_SYS_NS16550
	378	#define CONFIG_SYS_NS16550_SERIAL
	379	#define CONFIG_SYS_NS16550_CLK 3686400
	380	#define CONFIG_SYS_NS16550_REG_SIZE -8
	381	#define CONFIG_SYS_NS16550_COM1 0x7C000000
f5e0d039 HS	382
	383
	384	/*
	385	* PCI Config - Address Map B (CHRP)
	386	*/
	387
6d0f6bcf JCPV	388	#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
	389	#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
	390	#define CONFIG_SYS_PCI_MEMORY_SIZE 0x40000000
	391	#define CONFIG_SYS_PCI_MEM_BUS 0x80000000
	392	#define CONFIG_SYS_PCI_MEM_PHYS 0x80000000
	393	#define CONFIG_SYS_PCI_MEM_SIZE 0x7D000000
	394	#define CONFIG_SYS_ISA_MEM_BUS 0x00000000
	395	#define CONFIG_SYS_ISA_MEM_PHYS 0xFD000000
	396	#define CONFIG_SYS_ISA_MEM_SIZE 0x01000000
	397	#define CONFIG_SYS_PCI_IO_BUS 0x00800000
	398	#define CONFIG_SYS_PCI_IO_PHYS 0xFE800000
	399	#define CONFIG_SYS_PCI_IO_SIZE 0x00400000
	400	#define CONFIG_SYS_ISA_IO_BUS 0x00000000
	401	#define CONFIG_SYS_ISA_IO_PHYS 0xFE000000
	402	#define CONFIG_SYS_ISA_IO_SIZE 0x00800000
	403	#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_ISA_IO_PHYS
	404	#define CONFIG_SYS_ISA_IO CONFIG_SYS_ISA_IO_PHYS
	405	#define CONFIG_SYS_60X_PCI_IO_OFFSET CONFIG_SYS_ISA_IO_PHYS
f5e0d039 HS	406
	407
	408	/*
	409	* Extra init functions
b87dfd28	410	*
6d0f6bcf	411	* CONFIG_SYS_BOARD_ASM_INIT - Call assembly init code
f5e0d039 HS	412	*/
f5e0d039 HS	413
6d0f6bcf	414	#define CONFIG_SYS_BOARD_ASM_INIT
f5e0d039	415
f5e0d039	416	#endif /* __CONFIG_H */