projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| fe8c2806 WD |
1 | /* |
| 2 | * (C) Copyright 2000 | |
| 3 | * Murray Jensen <Murray.Jensen@cmst.csiro.au> | |
| 4 | * | |
| 5 | * (C) Copyright 2000 | |
| 6 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
| 7 | * Marius Groeger <mgroeger@sysgo.de> | |
| 8 | * | |
| 9 | * (C) Copyright 2001 | |
| 10 | * Advent Networks, Inc. <http://www.adventnetworks.com> | |
| 11 | * Jay Monkman <jtm@smoothsmoothie.com> | |
| 12 | * | |
| 13 | * Configuation settings for the WindRiver PPMC8260 board. | |
| 14 | * | |
| 3765b3e7 | 15 | * SPDX-License-Identifier: GPL-2.0+ |
| fe8c2806 WD |
16 | */ |
| 17 | ||
| 18 | #ifndef __CONFIG_H | |
| 19 | #define __CONFIG_H | |
| 20 | ||
| 2ae18241 WD |
21 | #define CONFIG_SYS_TEXT_BASE 0xfe000000 |
| 22 | ||
| fe8c2806 WD |
23 | /***************************************************************************** |
| 24 | * | |
| 25 | * These settings must match the way _your_ board is set up | |
| 26 | * | |
| 27 | *****************************************************************************/ | |
| 28 | ||
| 29 | /* What is the oscillator's (UX2) frequency in Hz? */ | |
| 30 | #define CONFIG_8260_CLKIN (66 * 1000 * 1000) | |
| 31 | ||
| 32 | /*----------------------------------------------------------------------- | |
| 33 | * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual | |
| 34 | *----------------------------------------------------------------------- | |
| 35 | * What should MODCK_H be? It is dependent on the oscillator | |
| 36 | * frequency, MODCK[1-3], and desired CPM and core frequencies. | |
| 37 | * Here are some example values (all frequencies are in MHz): | |
| 38 | * | |
| 39 | * MODCK_H MODCK[1-3] Osc CPM Core S2-6 S2-7 S2-8 | |
| 40 | * ------- ---------- --- --- ---- ----- ----- ----- | |
| 41 | * 0x2 0x2 33 133 133 Close Open Close | |
| 42 | * 0x2 0x3 33 133 166 Close Open Open | |
| 43 | * 0x2 0x4 33 133 200 Open Close Close | |
| 44 | * 0x2 0x5 33 133 233 Open Close Open | |
| 45 | * 0x2 0x6 33 133 266 Open Open Close | |
| 46 | * | |
| 47 | * 0x5 0x5 66 133 133 Open Close Open | |
| 48 | * 0x5 0x6 66 133 166 Open Open Close | |
| 49 | * 0x5 0x7 66 133 200 Open Open Open | |
| 50 | * 0x6 0x0 66 133 233 Close Close Close | |
| 51 | * 0x6 0x1 66 133 266 Close Close Open | |
| 52 | * 0x6 0x2 66 133 300 Close Open Close | |
| 53 | */ | |
| 6d0f6bcf | 54 | #define CONFIG_SYS_PPMC_MODCK_H 0x05 |
| fe8c2806 WD |
55 | |
| 56 | /* Define this if you want to boot from 0x00000100. If you don't define | |
| 57 | * this, you will need to program the bootloader to 0xfff00000, and | |
| 58 | * get the hardware reset config words at 0xfe000000. The simplest | |
| 59 | * way to do that is to program the bootloader at both addresses. | |
| 60 | * It is suggested that you just let U-Boot live at 0x00000000. | |
| 61 | */ | |
| 6d0f6bcf | 62 | #define CONFIG_SYS_PPMC_BOOT_LOW 1 |
| fe8c2806 WD |
63 | |
| 64 | /* What should the base address of the main FLASH be and how big is | |
| 14d0a02a | 65 | * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/ppmc8260/config.mk |
| fe8c2806 WD |
66 | * The main FLASH is whichever is connected to *CS0. U-Boot expects |
| 67 | * this to be the SIMM. | |
| 68 | */ | |
| 6d0f6bcf JCPV |
69 | #define CONFIG_SYS_FLASH0_BASE 0xFE000000 |
| 70 | #define CONFIG_SYS_FLASH0_SIZE 16 | |
| fe8c2806 WD |
71 | |
| 72 | /* What should be the base address of the first SDRAM DIMM and how big is | |
| 73 | * it (in Mbytes)? | |
| 74 | */ | |
| 6d0f6bcf JCPV |
75 | #define CONFIG_SYS_SDRAM0_BASE 0x00000000 |
| 76 | #define CONFIG_SYS_SDRAM0_SIZE 128 | |
| fe8c2806 WD |
77 | |
| 78 | /* What should be the base address of the second SDRAM DIMM and how big is | |
| 79 | * it (in Mbytes)? | |
| 80 | */ | |
| 6d0f6bcf JCPV |
81 | #define CONFIG_SYS_SDRAM1_BASE 0x08000000 |
| 82 | #define CONFIG_SYS_SDRAM1_SIZE 128 | |
| fe8c2806 WD |
83 | |
| 84 | /* What should be the base address of the on board SDRAM and how big is | |
| 85 | * it (in Mbytes)? | |
| 86 | */ | |
| 6d0f6bcf JCPV |
87 | #define CONFIG_SYS_SDRAM2_BASE 0x38000000 |
| 88 | #define CONFIG_SYS_SDRAM2_SIZE 16 | |
| fe8c2806 WD |
89 | |
| 90 | /* What should be the base address of the MAILBOX and how big is it | |
| 91 | * (in Bytes) | |
| 6d0f6bcf | 92 | * The eeprom lives at CONFIG_SYS_MAILBOX_BASE + 0x80000000 |
| fe8c2806 | 93 | */ |
| 6d0f6bcf JCPV |
94 | #define CONFIG_SYS_MAILBOX_BASE 0x32000000 |
| 95 | #define CONFIG_SYS_MAILBOX_SIZE 8192 | |
| fe8c2806 WD |
96 | |
| 97 | /* What is the base address of the I/O select lines and how big is it | |
| 98 | * (In Mbytes)? | |
| 99 | */ | |
| 100 | ||
| 6d0f6bcf JCPV |
101 | #define CONFIG_SYS_IOSELECT_BASE 0xE0000000 |
| 102 | #define CONFIG_SYS_IOSELECT_SIZE 32 | |
| fe8c2806 WD |
103 | |
| 104 | ||
| 105 | /* What should be the base address of the LEDs and switch S0? | |
| 106 | * If you don't want them enabled, don't define this. | |
| 107 | */ | |
| 6d0f6bcf | 108 | #define CONFIG_SYS_LED_BASE 0xF1000000 |
| fe8c2806 WD |
109 | |
| 110 | /* | |
| 111 | * PPMC8260 with 256 16 MB DIMM: | |
| 112 | * | |
| 113 | * 0x0000 0000 Exception Vector code, 8k | |
| 114 | * : | |
| 115 | * 0x0000 1FFF | |
| 116 | * 0x0000 2000 Free for Application Use | |
| 117 | * : | |
| 118 | * : | |
| 119 | * | |
| 120 | * : | |
| 121 | * : | |
| 122 | * 0x0FF5 FF30 Monitor Stack (Growing downward) | |
| 123 | * Monitor Stack Buffer (0x80) | |
| 124 | * 0x0FF5 FFB0 Board Info Data | |
| 125 | * 0x0FF6 0000 Malloc Arena | |
| 0e8d1586 | 126 | * : CONFIG_ENV_SECT_SIZE, 256k |
| 6d0f6bcf | 127 | * : CONFIG_SYS_MALLOC_LEN, 128k |
| fe8c2806 | 128 | * 0x0FFC 0000 RAM Copy of Monitor Code |
| 6d0f6bcf JCPV |
129 | * : CONFIG_SYS_MONITOR_LEN, 256k |
| 130 | * 0x0FFF FFFF [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1 | |
| fe8c2806 WD |
131 | */ |
| 132 | ||
| 133 | ||
| 134 | /* | |
| 135 | * select serial console configuration | |
| 136 | * | |
| 137 | * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then | |
| 138 | * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 | |
| 139 | * for SCC). | |
| 140 | * | |
| 141 | * if CONFIG_CONS_NONE is defined, then the serial console routines must | |
| 142 | * defined elsewhere. | |
| 143 | * The console can be on SMC1 or SMC2 | |
| 144 | */ | |
| 145 | #define CONFIG_CONS_ON_SMC 1 /* define if console on SMC */ | |
| 146 | #undef CONFIG_CONS_ON_SCC /* define if console on SCC */ | |
| 147 | #undef CONFIG_CONS_NONE /* define if console on neither */ | |
| 148 | #define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */ | |
| 149 | ||
| 150 | /* | |
| 151 | * select ethernet configuration | |
| 152 | * | |
| 153 | * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then | |
| 154 | * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 | |
| 155 | * for FCC) | |
| 156 | * | |
| 157 | * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be | |
| 639221c7 | 158 | * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. |
| fe8c2806 WD |
159 | */ |
| 160 | ||
| 161 | #undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */ | |
| 162 | #define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */ | |
| 163 | #undef CONFIG_ETHER_NONE /* define if ethernet on neither */ | |
| 164 | #define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ | |
| 165 | #define CONFIG_MII /* MII PHY management */ | |
| 166 | #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ | |
| 167 | /* | |
| 168 | * Port pins used for bit-banged MII communictions (if applicable). | |
| 169 | */ | |
| 170 | #define MDIO_PORT 2 /* Port C */ | |
| be225442 LCM |
171 | #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ |
| 172 | (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) | |
| 173 | #define MDC_DECLARE MDIO_DECLARE | |
| 174 | ||
| fe8c2806 WD |
175 | #define MDIO_ACTIVE (iop->pdir |= 0x00400000) |
| 176 | #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) | |
| 177 | #define MDIO_READ ((iop->pdat & 0x00400000) != 0) | |
| 178 | ||
| 179 | #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ | |
| 180 | else iop->pdat &= ~0x00400000 | |
| 181 | ||
| 182 | #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ | |
| 183 | else iop->pdat &= ~0x00200000 | |
| 184 | ||
| 185 | #define MIIDELAY udelay(1) | |
| 186 | ||
| 187 | ||
| 188 | /* Define this to reserve an entire FLASH sector (256 KB) for | |
| 189 | * environment variables. Otherwise, the environment will be | |
| 190 | * put in the same sector as U-Boot, and changing variables | |
| 191 | * will erase U-Boot temporarily | |
| 192 | */ | |
| 0e8d1586 | 193 | #define CONFIG_ENV_IN_OWN_SECT 1 |
| fe8c2806 WD |
194 | |
| 195 | /* Define to allow the user to overwrite serial and ethaddr */ | |
| 196 | #define CONFIG_ENV_OVERWRITE | |
| 197 | ||
| 198 | /* What should the console's baud rate be? */ | |
| 199 | #define CONFIG_BAUDRATE 9600 | |
| 200 | ||
| 201 | /* Ethernet MAC address */ | |
| 202 | ||
| 203 | #define CONFIG_ETHADDR 00:a0:1e:90:2b:00 | |
| 204 | ||
| 205 | /* Define this to set the last octet of the ethernet address | |
| 206 | * from the DS0-DS7 switch and light the leds with the result | |
| 207 | * The DS0-DS7 switch and the leds are backwards with respect | |
| 208 | * to each other. DS7 is on the board edge side of both the | |
| 209 | * led strip and the DS0-DS7 switch. | |
| 210 | */ | |
| 211 | #define CONFIG_MISC_INIT_R | |
| 212 | ||
| 213 | /* Set to a positive value to delay for running BOOTCOMMAND */ | |
| 214 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
| 215 | ||
| 216 | #if 0 | |
| 217 | /* Be selective on what keys can delay or stop the autoboot process | |
| 218 | * To stop use: " " | |
| 219 | */ | |
| 220 | # define CONFIG_AUTOBOOT_KEYED | |
| c37207d7 WD |
221 | # define CONFIG_AUTOBOOT_PROMPT \ |
| 222 | "Autobooting in %d seconds, press \" \" to stop\n", bootdelay | |
| fe8c2806 WD |
223 | # define CONFIG_AUTOBOOT_STOP_STR " " |
| 224 | # undef CONFIG_AUTOBOOT_DELAY_STR | |
| 225 | # define DEBUG_BOOTKEYS 0 | |
| 226 | #endif | |
| 227 | ||
| 228 | /* Define a command string that is automatically executed when no character | |
| 229 | * is read on the console interface withing "Boot Delay" after reset. | |
| 230 | */ | |
| 53677ef1 | 231 | #undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */ |
| b79a11cc | 232 | #define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */ |
| fe8c2806 | 233 | |
| 42dfe7a1 | 234 | #ifdef CONFIG_BOOT_ROOT_INITRD |
| fe8c2806 WD |
235 | #define CONFIG_BOOTCOMMAND \ |
| 236 | "version;" \ | |
| 237 | "echo;" \ | |
| 238 | "bootp;" \ | |
| 239 | "setenv bootargs root=/dev/ram0 rw " \ | |
| fe126d8b | 240 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ |
| fe8c2806 WD |
241 | "bootm" |
| 242 | #endif /* CONFIG_BOOT_ROOT_INITRD */ | |
| 243 | ||
| 42dfe7a1 | 244 | #ifdef CONFIG_BOOT_ROOT_NFS |
| fe8c2806 WD |
245 | #define CONFIG_BOOTCOMMAND \ |
| 246 | "version;" \ | |
| 247 | "echo;" \ | |
| 248 | "bootp;" \ | |
| fe126d8b WD |
249 | "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ |
| 250 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ | |
| fe8c2806 WD |
251 | "bootm" |
| 252 | #endif /* CONFIG_BOOT_ROOT_NFS */ | |
| 253 | ||
| d3b8c1a7 JL |
254 | |
| 255 | /* | |
| 256 | * BOOTP options | |
| fe8c2806 | 257 | */ |
| d3b8c1a7 JL |
258 | #define CONFIG_BOOTP_SUBNETMASK |
| 259 | #define CONFIG_BOOTP_GATEWAY | |
| 260 | #define CONFIG_BOOTP_HOSTNAME | |
| 261 | #define CONFIG_BOOTP_BOOTPATH | |
| 262 | #define CONFIG_BOOTP_BOOTFILESIZE | |
| 263 | #define CONFIG_BOOTP_DNS | |
| 264 | ||
| fe8c2806 WD |
265 | |
| 266 | /* undef this to save memory */ | |
| 6d0f6bcf | 267 | #define CONFIG_SYS_LONGHELP |
| fe8c2806 WD |
268 | |
| 269 | /* Monitor Command Prompt */ | |
| fe8c2806 | 270 | |
| 26a34560 JL |
271 | |
| 272 | /* | |
| 273 | * Command line configuration. | |
| 274 | */ | |
| 275 | #include <config_cmd_default.h> | |
| 276 | ||
| 277 | #define CONFIG_CMD_ELF | |
| 278 | #define CONFIG_CMD_ASKENV | |
| 279 | #define CONFIG_CMD_REGINFO | |
| 280 | #define CONFIG_CMD_MEMTEST | |
| 281 | #define CONFIG_CMD_MII | |
| 282 | #define CONFIG_CMD_IMMAP | |
| 283 | ||
| 284 | #undef CONFIG_CMD_KGDB | |
| fe8c2806 WD |
285 | |
| 286 | ||
| 287 | /* Where do the internal registers live? */ | |
| 6d0f6bcf | 288 | #define CONFIG_SYS_IMMR 0xf0000000 |
| fe8c2806 WD |
289 | |
| 290 | /***************************************************************************** | |
| 291 | * | |
| 292 | * You should not have to modify any of the following settings | |
| 293 | * | |
| 294 | *****************************************************************************/ | |
| 295 | ||
| 296 | #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ | |
| 297 | #define CONFIG_PPMC8260 1 /* on an Wind River PPMC8260 Board */ | |
| 9c4c5ae3 | 298 | #define CONFIG_CPM2 1 /* Has a CPM2 */ |
| fe8c2806 | 299 | |
| fe8c2806 WD |
300 | /* |
| 301 | * Miscellaneous configurable options | |
| 302 | */ | |
| 26a34560 | 303 | #if defined(CONFIG_CMD_KGDB) |
| 6d0f6bcf | 304 | # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
| fe8c2806 | 305 | #else |
| 6d0f6bcf | 306 | # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| fe8c2806 WD |
307 | #endif |
| 308 | ||
| 309 | /* Print Buffer Size */ | |
| 6d0f6bcf | 310 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16) |
| fe8c2806 | 311 | |
| 6d0f6bcf | 312 | #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ |
| fe8c2806 | 313 | |
| 6d0f6bcf | 314 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
| fe8c2806 | 315 | |
| 6d0f6bcf | 316 | #define CONFIG_SYS_LOAD_ADDR 0x140000 /* default load address */ |
| fe8c2806 | 317 | |
| 6d0f6bcf | 318 | #define CONFIG_SYS_MEMTEST_START 0x2000 /* memtest works from the end of */ |
| fe8c2806 WD |
319 | /* the exception vector table */ |
| 320 | /* to the end of the DRAM */ | |
| 321 | /* less monitor and malloc area */ | |
| 6d0f6bcf JCPV |
322 | #define CONFIG_SYS_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */ |
| 323 | #define CONFIG_SYS_MEM_END_USAGE ( CONFIG_SYS_MONITOR_LEN \ | |
| 324 | + CONFIG_SYS_MALLOC_LEN \ | |
| 0e8d1586 | 325 | + CONFIG_ENV_SECT_SIZE \ |
| 6d0f6bcf | 326 | + CONFIG_SYS_STACK_USAGE ) |
| fe8c2806 | 327 | |
| 6d0f6bcf JCPV |
328 | #define CONFIG_SYS_MEMTEST_END ( CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 \ |
| 329 | - CONFIG_SYS_MEM_END_USAGE ) | |
| fe8c2806 | 330 | |
| fe8c2806 WD |
331 | /* |
| 332 | * Low Level Configuration Settings | |
| 333 | * (address mappings, register initial values, etc.) | |
| 334 | * You should know what you are doing if you make changes here. | |
| 335 | */ | |
| 336 | ||
| 337 | #if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1) | |
| 338 | /* | |
| 339 | * Attention: This is board specific | |
| 340 | * - RX clk is CLK11 | |
| 341 | * - TX clk is CLK12 | |
| 342 | */ | |
| 6d0f6bcf | 343 | #define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 |\ |
| fe8c2806 WD |
344 | CMXSCR_TS1CS_CLK12) |
| 345 | ||
| 346 | #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) | |
| 347 | /* | |
| 348 | * Attention: this is board-specific | |
| 349 | * - Rx-CLK is CLK13 | |
| 350 | * - Tx-CLK is CLK14 | |
| 351 | * - Select bus for bd/buffers (see 28-13) | |
| 352 | * - Enable Full Duplex in FSMR | |
| 353 | */ | |
| d4590da4 MF |
354 | #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) |
| 355 | #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) | |
| 6d0f6bcf JCPV |
356 | #define CONFIG_SYS_CPMFCR_RAMTYPE 0 |
| 357 | #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) | |
| fe8c2806 WD |
358 | #endif /* CONFIG_ETHER_INDEX */ |
| 359 | ||
| 6d0f6bcf JCPV |
360 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE |
| 361 | #define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE | |
| 362 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM0_BASE | |
| 363 | #define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_SDRAM0_SIZE + CONFIG_SYS_SDRAM1_SIZE) | |
| fe8c2806 WD |
364 | |
| 365 | /*----------------------------------------------------------------------- | |
| 366 | * Hard Reset Configuration Words | |
| 367 | */ | |
| 6d0f6bcf JCPV |
368 | #if defined(CONFIG_SYS_PPMC_BOOT_LOW) |
| 369 | # define CONFIG_SYS_PPMC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS) | |
| fe8c2806 | 370 | #else |
| 6d0f6bcf JCPV |
371 | # define CONFIG_SYS_PPMC_HRCW_BOOT_FLAGS (0) |
| 372 | #endif /* defined(CONFIG_SYS_PPMC_BOOT_LOW) */ | |
| fe8c2806 | 373 | |
| 6d0f6bcf JCPV |
374 | /* get the HRCW ISB field from CONFIG_SYS_IMMR */ |
| 375 | #define CONFIG_SYS_PPMC_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) | \ | |
| 376 | ((CONFIG_SYS_IMMR & 0x01000000) >> 7) | \ | |
| 377 | ((CONFIG_SYS_IMMR & 0x00100000) >> 4) ) | |
| fe8c2806 | 378 | |
| 6d0f6bcf | 379 | #define CONFIG_SYS_HRCW_MASTER ( HRCW_EBM | \ |
| fe8c2806 WD |
380 | HRCW_BPS11 | \ |
| 381 | HRCW_L2CPC10 | \ | |
| 382 | HRCW_DPPC00 | \ | |
| 6d0f6bcf | 383 | CONFIG_SYS_PPMC_HRCW_IMMR | \ |
| fe8c2806 WD |
384 | HRCW_MMR00 | \ |
| 385 | HRCW_LBPC00 | \ | |
| 386 | HRCW_APPC10 | \ | |
| 387 | HRCW_CS10PC00 | \ | |
| 6d0f6bcf JCPV |
388 | (CONFIG_SYS_PPMC_MODCK_H & HRCW_MODCK_H1111) | \ |
| 389 | CONFIG_SYS_PPMC_HRCW_BOOT_FLAGS ) | |
| fe8c2806 WD |
390 | |
| 391 | /* no slaves */ | |
| 6d0f6bcf JCPV |
392 | #define CONFIG_SYS_HRCW_SLAVE1 0 |
| 393 | #define CONFIG_SYS_HRCW_SLAVE2 0 | |
| 394 | #define CONFIG_SYS_HRCW_SLAVE3 0 | |
| 395 | #define CONFIG_SYS_HRCW_SLAVE4 0 | |
| 396 | #define CONFIG_SYS_HRCW_SLAVE5 0 | |
| 397 | #define CONFIG_SYS_HRCW_SLAVE6 0 | |
| 398 | #define CONFIG_SYS_HRCW_SLAVE7 0 | |
| fe8c2806 WD |
399 | |
| 400 | /*----------------------------------------------------------------------- | |
| 401 | * Definitions for initial stack pointer and data area (in DPRAM) | |
| 402 | */ | |
| 6d0f6bcf | 403 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
| 553f0982 | 404 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ |
| 25ddd1fb | 405 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
| 6d0f6bcf | 406 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
| fe8c2806 WD |
407 | |
| 408 | /*----------------------------------------------------------------------- | |
| 409 | * Start addresses for the final memory configuration | |
| 410 | * (Set up by the startup code) | |
| 6d0f6bcf JCPV |
411 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
| 412 | * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent. | |
| fe8c2806 | 413 | */ |
| 6d0f6bcf | 414 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH0_BASE |
| fe8c2806 | 415 | |
| 6d0f6bcf JCPV |
416 | #ifndef CONFIG_SYS_MONITOR_BASE |
| 417 | #define CONFIG_SYS_MONITOR_BASE 0x0ff80000 | |
| fe8c2806 WD |
418 | #endif |
| 419 | ||
| 6d0f6bcf JCPV |
420 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
| 421 | # define CONFIG_SYS_RAMBOOT | |
| fe8c2806 WD |
422 | #endif |
| 423 | ||
| 6d0f6bcf JCPV |
424 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 374 kB for Monitor */ |
| 425 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
| fe8c2806 WD |
426 | |
| 427 | /* | |
| 428 | * For booting Linux, the board info and command line data | |
| 429 | * have to be in the first 8 MB of memory, since this is | |
| 430 | * the maximum mapped by the Linux kernel during initialization. | |
| 431 | */ | |
| 6d0f6bcf | 432 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
| fe8c2806 WD |
433 | |
| 434 | /*----------------------------------------------------------------------- | |
| 435 | * FLASH and environment organization | |
| 436 | */ | |
| 437 | ||
| 6d0f6bcf | 438 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
| 00b1883a | 439 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ |
| 6d0f6bcf JCPV |
440 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ |
| 441 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
| 442 | #define CONFIG_SYS_FLASH_INCREMENT 0 /* there is only one bank */ | |
| 443 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */ | |
| 444 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ | |
| fe8c2806 WD |
445 | |
| 446 | ||
| 6d0f6bcf | 447 | #ifndef CONFIG_SYS_RAMBOOT |
| fe8c2806 | 448 | |
| 5a1aceb0 | 449 | # define CONFIG_ENV_IS_IN_FLASH 1 |
| 0e8d1586 | 450 | # ifdef CONFIG_ENV_IN_OWN_SECT |
| 6d0f6bcf | 451 | # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) |
| 0e8d1586 | 452 | # define CONFIG_ENV_SECT_SIZE 0x40000 |
| fe8c2806 | 453 | # else |
| 6d0f6bcf | 454 | # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE) |
| 0e8d1586 JCPV |
455 | # define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ |
| 456 | # define CONFIG_ENV_SECT_SIZE 0x40000 /* see README - env sect real size */ | |
| 457 | # endif /* CONFIG_ENV_IN_OWN_SECT */ | |
| fe8c2806 WD |
458 | |
| 459 | #else | |
| 5a1aceb0 | 460 | # define CONFIG_ENV_IS_IN_FLASH 1 |
| 6d0f6bcf | 461 | # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) |
| 0e8d1586 JCPV |
462 | #define CONFIG_ENV_SIZE 0x1000 |
| 463 | # define CONFIG_ENV_SECT_SIZE 0x40000 | |
| 6d0f6bcf | 464 | #endif /* CONFIG_SYS_RAMBOOT */ |
| fe8c2806 WD |
465 | |
| 466 | /*----------------------------------------------------------------------- | |
| 467 | * Cache Configuration | |
| 468 | */ | |
| 6d0f6bcf | 469 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ |
| fe8c2806 | 470 | |
| 26a34560 | 471 | #if defined(CONFIG_CMD_KGDB) |
| 6d0f6bcf | 472 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
| fe8c2806 WD |
473 | #endif |
| 474 | ||
| 475 | /*----------------------------------------------------------------------- | |
| 476 | * HIDx - Hardware Implementation-dependent Registers 2-11 | |
| 477 | *----------------------------------------------------------------------- | |
| 478 | * HID0 also contains cache control - initially enable both caches and | |
| 479 | * invalidate contents, then the final state leaves only the instruction | |
| 480 | * cache enabled. Note that Power-On and Hard reset invalidate the caches, | |
| 481 | * but Soft reset does not. | |
| 482 | * | |
| 483 | * HID1 has only read-only information - nothing to set. | |
| 484 | */ | |
| 6d0f6bcf | 485 | #define CONFIG_SYS_HID0_INIT (HID0_ICE |\ |
| fe8c2806 WD |
486 | HID0_DCE |\ |
| 487 | HID0_ICFI |\ | |
| 488 | HID0_DCI |\ | |
| 489 | HID0_IFEM |\ | |
| 490 | HID0_ABE) | |
| 491 | ||
| 6d0f6bcf | 492 | #define CONFIG_SYS_HID0_FINAL (HID0_ICE |\ |
| fe8c2806 WD |
493 | HID0_IFEM |\ |
| 494 | HID0_ABE |\ | |
| 495 | HID0_EMCP) | |
| 6d0f6bcf | 496 | #define CONFIG_SYS_HID2 0 |
| fe8c2806 WD |
497 | |
| 498 | /*----------------------------------------------------------------------- | |
| 499 | * RMR - Reset Mode Register | |
| 500 | *----------------------------------------------------------------------- | |
| 501 | */ | |
| 6d0f6bcf | 502 | #define CONFIG_SYS_RMR 0 |
| fe8c2806 WD |
503 | |
| 504 | /*----------------------------------------------------------------------- | |
| 505 | * BCR - Bus Configuration 4-25 | |
| 506 | *----------------------------------------------------------------------- | |
| 507 | */ | |
| 6d0f6bcf | 508 | #define CONFIG_SYS_BCR (BCR_EBM |\ |
| fe8c2806 WD |
509 | 0x30000000) |
| 510 | ||
| 511 | /*----------------------------------------------------------------------- | |
| 512 | * SIUMCR - SIU Module Configuration 4-31 | |
| 513 | * Ref Section 4.3.2.6 page 4-31 | |
| 514 | *----------------------------------------------------------------------- | |
| 515 | */ | |
| 516 | ||
| 6d0f6bcf | 517 | #define CONFIG_SYS_SIUMCR (SIUMCR_ESE |\ |
| fe8c2806 WD |
518 | SIUMCR_DPPC00 |\ |
| 519 | SIUMCR_L2CPC10 |\ | |
| 520 | SIUMCR_LBPC00 |\ | |
| 521 | SIUMCR_APPC10 |\ | |
| 522 | SIUMCR_CS10PC00 |\ | |
| 523 | SIUMCR_BCTLC00 |\ | |
| 524 | SIUMCR_MMR00) | |
| 525 | ||
| 526 | ||
| 527 | /*----------------------------------------------------------------------- | |
| 528 | * SYPCR - System Protection Control 11-9 | |
| 529 | * SYPCR can only be written once after reset! | |
| 530 | *----------------------------------------------------------------------- | |
| 531 | * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable | |
| 532 | */ | |
| 6d0f6bcf | 533 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC |\ |
| fe8c2806 WD |
534 | SYPCR_BMT |\ |
| 535 | SYPCR_PBME |\ | |
| 536 | SYPCR_LBME |\ | |
| 537 | SYPCR_SWRI |\ | |
| 538 | SYPCR_SWP) | |
| 539 | ||
| 540 | /*----------------------------------------------------------------------- | |
| 541 | * TMCNTSC - Time Counter Status and Control 4-40 | |
| 542 | *----------------------------------------------------------------------- | |
| 543 | * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, | |
| 544 | * and enable Time Counter | |
| 545 | */ | |
| 6d0f6bcf | 546 | #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC |\ |
| fe8c2806 WD |
547 | TMCNTSC_ALR |\ |
| 548 | TMCNTSC_TCF |\ | |
| 549 | TMCNTSC_TCE) | |
| 550 | ||
| 551 | /*----------------------------------------------------------------------- | |
| 552 | * PISCR - Periodic Interrupt Status and Control 4-42 | |
| 553 | *----------------------------------------------------------------------- | |
| 554 | * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable | |
| 555 | * Periodic timer | |
| 556 | */ | |
| 6d0f6bcf | 557 | #define CONFIG_SYS_PISCR (PISCR_PS |\ |
| fe8c2806 WD |
558 | PISCR_PTF |\ |
| 559 | PISCR_PTE) | |
| 560 | ||
| 561 | /*----------------------------------------------------------------------- | |
| 562 | * SCCR - System Clock Control 9-8 | |
| 563 | *----------------------------------------------------------------------- | |
| 564 | */ | |
| 6d0f6bcf | 565 | #define CONFIG_SYS_SCCR 0 |
| fe8c2806 WD |
566 | |
| 567 | /*----------------------------------------------------------------------- | |
| 568 | * RCCR - RISC Controller Configuration 13-7 | |
| 569 | *----------------------------------------------------------------------- | |
| 570 | */ | |
| 6d0f6bcf | 571 | #define CONFIG_SYS_RCCR 0 |
| fe8c2806 WD |
572 | |
| 573 | /* | |
| 574 | * Initialize Memory Controller: | |
| 575 | * | |
| 576 | * Bank Bus Machine PortSz Device | |
| 577 | * ---- --- ------- ------ ------ | |
| 578 | * 0 60x GPCM 32 bit FLASH (SIMM - 32MB) * | |
| 579 | * 1 unused | |
| 580 | * 2 60x SDRAM 64 bit SDRAM (DIMM - 128MB) | |
| 581 | * 3 60x SDRAM 64 bit SDRAM (DIMM - 128MB) | |
| 582 | * 4 Local SDRAM 32 bit SDRAM (on board - 16MB) | |
| 583 | * 5 60x GPCM 8 bit Mailbox/EEPROM (8KB) | |
| 584 | * 6 60x GPCM 8 bit FLASH (on board - 2MB) * | |
| 585 | * 7 60x GPCM 8 bit LEDs, switches | |
| 586 | * | |
| 587 | * (*) This configuration requires the PPMC8260 be configured | |
| 588 | * so that *CS0 goes to the FLASH SIMM, and *CS6 goes to | |
| 589 | * the on board FLASH. In other words, JP24 should have | |
| 590 | * pins 1 and 2 jumpered and pins 3 and 4 jumpered. | |
| 591 | * | |
| 592 | */ | |
| 593 | ||
| 594 | /*----------------------------------------------------------------------- | |
| 595 | * BR0,BR1 - Base Register | |
| 596 | * Ref: Section 10.3.1 on page 10-14 | |
| 597 | * OR0,OR1 - Option Register | |
| 598 | * Ref: Section 10.3.2 on page 10-18 | |
| 599 | *----------------------------------------------------------------------- | |
| 600 | */ | |
| 601 | ||
| 602 | /* Bank 0,1 - FLASH SIMM | |
| 603 | * | |
| 604 | * This expects the FLASH SIMM to be connected to *CS0 | |
| 605 | * It consists of 4 AM29F080B parts. | |
| 606 | * | |
| 607 | * Note: For the 4 MB SIMM, *CS1 is unused. | |
| 608 | */ | |
| 609 | ||
| 610 | /* BR0 is configured as follows: | |
| 611 | * | |
| 612 | * - Base address of 0xFE000000 | |
| 613 | * - 32 bit port size | |
| 614 | * - Data errors checking is disabled | |
| 615 | * - Read and write access | |
| 616 | * - GPCM 60x bus | |
| 617 | * - Access are handled by the memory controller according to MSEL | |
| 618 | * - Not used for atomic operations | |
| 619 | * - No data pipelining is done | |
| 620 | * - Valid | |
| 621 | */ | |
| 6d0f6bcf | 622 | #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\ |
| fe8c2806 WD |
623 | BRx_PS_32 |\ |
| 624 | BRx_MS_GPCM_P |\ | |
| 625 | BRx_V) | |
| 626 | ||
| 627 | /* OR0 is configured as follows: | |
| 628 | * | |
| 629 | * - 32 MB | |
| 630 | * - *BCTL0 is asserted upon access to the current memory bank | |
| 631 | * - *CW / *WE are negated a quarter of a clock earlier | |
| 632 | * - *CS is output at the same time as the address lines | |
| 633 | * - Uses a clock cycle length of 5 | |
| 634 | * - *PSDVAL is generated internally by the memory controller | |
| 635 | * unless *GTA is asserted earlier externally. | |
| 636 | * - Relaxed timing is generated by the GPCM for accesses | |
| 637 | * initiated to this memory region. | |
| 638 | * - One idle clock is inserted between a read access from the | |
| 639 | * current bank and the next access. | |
| 640 | */ | |
| 6d0f6bcf | 641 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE) |\ |
| fe8c2806 WD |
642 | ORxG_CSNT |\ |
| 643 | ORxG_ACS_DIV1 |\ | |
| 644 | ORxG_SCY_5_CLK |\ | |
| 645 | ORxG_TRLX |\ | |
| 646 | ORxG_EHTR) | |
| 647 | ||
| 648 | /*----------------------------------------------------------------------- | |
| 649 | * BR2,BR3 - Base Register | |
| 650 | * Ref: Section 10.3.1 on page 10-14 | |
| 651 | * OR2,OR3 - Option Register | |
| 652 | * Ref: Section 10.3.2 on page 10-16 | |
| 653 | *----------------------------------------------------------------------- | |
| 654 | */ | |
| 655 | ||
| 656 | /* | |
| 657 | * Bank 2,3 - 128 MB SDRAM DIMM | |
| 658 | */ | |
| 659 | ||
| 660 | /* With a 128 MB DIMM, the BR2 is configured as follows: | |
| 661 | * | |
| 662 | * - Base address of 0x00000000/0x08000000 | |
| 663 | * - 64 bit port size (60x bus only) | |
| 664 | * - Data errors checking is disabled | |
| 665 | * - Read and write access | |
| 666 | * - SDRAM 60x bus | |
| 667 | * - Access are handled by the memory controller according to MSEL | |
| 668 | * - Not used for atomic operations | |
| 669 | * - No data pipelining is done | |
| 670 | * - Valid | |
| 671 | */ | |
| 6d0f6bcf | 672 | #define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\ |
| fe8c2806 WD |
673 | BRx_PS_64 |\ |
| 674 | BRx_MS_SDRAM_P |\ | |
| 675 | BRx_V) | |
| 676 | ||
| 6d0f6bcf | 677 | #define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_SDRAM1_BASE & BRx_BA_MSK) |\ |
| fe8c2806 WD |
678 | BRx_PS_64 |\ |
| 679 | BRx_MS_SDRAM_P |\ | |
| 680 | BRx_V) | |
| 681 | ||
| 682 | /* With a 128 MB DIMM, the OR2 is configured as follows: | |
| 683 | * | |
| 684 | * - 128 MB | |
| 685 | * - 4 internal banks per device | |
| 686 | * - Row start address bit is A8 with PSDMR[PBI] = 0 | |
| 687 | * - 13 row address lines | |
| 688 | * - Back-to-back page mode | |
| 689 | * - Internal bank interleaving within save device enabled | |
| 690 | */ | |
| 691 | ||
| 6d0f6bcf | 692 | #define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\ |
| fe8c2806 WD |
693 | ORxS_BPD_4 |\ |
| 694 | ORxS_ROWST_PBI0_A7 |\ | |
| 695 | ORxS_NUMR_13) | |
| 696 | ||
| 6d0f6bcf | 697 | #define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM1_SIZE) |\ |
| fe8c2806 WD |
698 | ORxS_BPD_4 |\ |
| 699 | ORxS_ROWST_PBI0_A7 |\ | |
| 700 | ORxS_NUMR_13) | |
| 701 | ||
| 702 | ||
| 703 | /*----------------------------------------------------------------------- | |
| 704 | * PSDMR - 60x Bus SDRAM Mode Register | |
| 705 | * Ref: Section 10.3.3 on page 10-21 | |
| 706 | *----------------------------------------------------------------------- | |
| 707 | */ | |
| 708 | ||
| 709 | /* With a 128 MB DIMM, the PSDMR is configured as follows: | |
| 710 | * | |
| 711 | * - Page Based Interleaving, | |
| 712 | * - Refresh Enable, | |
| 713 | * - Normal Operation | |
| 714 | * - Address Multiplexing where A5 is output on A14 pin | |
| 715 | * (A6 on A15, and so on), | |
| 716 | * - use address pins A13-A15 as bank select, | |
| 717 | * - A9 is output on SDA10 during an ACTIVATE command, | |
| 718 | * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks, | |
| 719 | * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command | |
| 720 | * is 3 clocks, | |
| 721 | * - earliest timing for READ/WRITE command after ACTIVATE command is | |
| 722 | * 2 clocks, | |
| 723 | * - earliest timing for PRECHARGE after last data was read is 1 clock, | |
| 724 | * - earliest timing for PRECHARGE after last data was written is 1 clock, | |
| 725 | * - External Address Multiplexing enabled | |
| 726 | * - CAS Latency is 2. | |
| 727 | */ | |
| 6d0f6bcf | 728 | #define CONFIG_SYS_PSDMR (PSDMR_RFEN |\ |
| fe8c2806 WD |
729 | PSDMR_SDAM_A14_IS_A5 |\ |
| 730 | PSDMR_BSMA_A13_A15 |\ | |
| 731 | PSDMR_SDA10_PBI0_A9 |\ | |
| 732 | PSDMR_RFRC_7_CLK |\ | |
| 733 | PSDMR_PRETOACT_3W |\ | |
| 734 | PSDMR_ACTTORW_2W |\ | |
| 735 | PSDMR_LDOTOPRE_1C |\ | |
| 736 | PSDMR_WRC_1C |\ | |
| 737 | PSDMR_EAMUX |\ | |
| 738 | PSDMR_CL_2) | |
| 739 | ||
| 740 | ||
| 6d0f6bcf JCPV |
741 | #define CONFIG_SYS_PSRT 0x0e |
| 742 | #define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32 | |
| fe8c2806 WD |
743 | |
| 744 | ||
| 745 | /*----------------------------------------------------------------------- | |
| 746 | * BR4 - Base Register | |
| 747 | * Ref: Section 10.3.1 on page 10-14 | |
| 748 | * OR4 - Option Register | |
| 749 | * Ref: Section 10.3.2 on page 10-16 | |
| 750 | *----------------------------------------------------------------------- | |
| 751 | */ | |
| 752 | ||
| 753 | /* | |
| 754 | * Bank 4 - On board SDRAM | |
| 755 | * | |
| 756 | */ | |
| 757 | /* With 16 MB of onboard SDRAM BR4 is configured as follows | |
| 758 | * | |
| 759 | * - Base address 0x38000000 | |
| 760 | * - 32 bit port size | |
| 761 | * - Data error checking disabled | |
| 762 | * - Read/Write access | |
| 763 | * - SDRAM local bus | |
| 764 | * - Not used for atomic operations | |
| 765 | * - No data pipelining is done | |
| 766 | * - Valid | |
| 767 | * | |
| 768 | */ | |
| 769 | ||
| 6d0f6bcf | 770 | #define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_SDRAM2_BASE & BRx_BA_MSK) |\ |
| fe8c2806 WD |
771 | BRx_PS_32 |\ |
| 772 | BRx_DECC_NONE |\ | |
| 773 | BRx_MS_SDRAM_L |\ | |
| 774 | BRx_V) | |
| 775 | ||
| 776 | /* | |
| 777 | * With 16MB SDRAM, OR4 is configured as follows | |
| 778 | * - 4 internal banks per device | |
| 779 | * - Row start address bit is A10 with LSDMR[PBI] = 0 | |
| 780 | * - 12 row address lines | |
| 781 | * - Back-to-back page mode | |
| 782 | * - Internal bank interleaving within save device enabled | |
| 783 | */ | |
| 784 | ||
| 6d0f6bcf | 785 | #define CONFIG_SYS_OR4_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM2_SIZE) |\ |
| fe8c2806 WD |
786 | ORxS_BPD_4 |\ |
| 787 | ORxS_ROWST_PBI0_A10 |\ | |
| 788 | ORxS_NUMR_12) | |
| 789 | ||
| 790 | ||
| 791 | /*----------------------------------------------------------------------- | |
| 792 | * LSDMR - Local Bus SDRAM Mode Register | |
| 793 | * Ref: Section 10.3.4 on page 10-24 | |
| 794 | *----------------------------------------------------------------------- | |
| 795 | */ | |
| 796 | ||
| 797 | /* With a 16 MB onboard SDRAM, the LSDMR is configured as follows: | |
| 798 | * | |
| 799 | * - Page Based Interleaving, | |
| 800 | * - Refresh Enable, | |
| 801 | * - Normal Operation | |
| 802 | * - Address Multiplexing where A5 is output on A13 pin | |
| 803 | * (A6 on A15, and so on), | |
| 804 | * - use address pins A15-A17 as bank select, | |
| 805 | * - A11 is output on SDA10 during an ACTIVATE command, | |
| 806 | * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks, | |
| 807 | * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command | |
| 808 | * is 2 clocks, | |
| 809 | * - earliest timing for READ/WRITE command after ACTIVATE command is | |
| 810 | * 2 clocks, | |
| 811 | * - SDRAM burst length is 8 | |
| 812 | * - earliest timing for PRECHARGE after last data was read is 1 clock, | |
| 813 | * - earliest timing for PRECHARGE after last data was written is 1 clock, | |
| 814 | * - External Address Multiplexing disabled | |
| 815 | * - CAS Latency is 2. | |
| 816 | */ | |
| 6d0f6bcf | 817 | #define CONFIG_SYS_LSDMR (PSDMR_RFEN |\ |
| fe8c2806 WD |
818 | PSDMR_SDAM_A13_IS_A5 |\ |
| 819 | PSDMR_BSMA_A15_A17 |\ | |
| 820 | PSDMR_SDA10_PBI0_A11 |\ | |
| 821 | PSDMR_RFRC_7_CLK |\ | |
| 822 | PSDMR_PRETOACT_2W |\ | |
| 823 | PSDMR_ACTTORW_2W |\ | |
| 824 | PSDMR_BL |\ | |
| 825 | PSDMR_LDOTOPRE_1C |\ | |
| 826 | PSDMR_WRC_1C |\ | |
| 827 | PSDMR_CL_2) | |
| 828 | ||
| 6d0f6bcf | 829 | #define CONFIG_SYS_LSRT 0x0e |
| fe8c2806 WD |
830 | |
| 831 | /*----------------------------------------------------------------------- | |
| 832 | * BR5 - Base Register | |
| 833 | * Ref: Section 10.3.1 on page 10-14 | |
| 834 | * OR5 - Option Register | |
| 835 | * Ref: Section 10.3.2 on page 10-16 | |
| 836 | *----------------------------------------------------------------------- | |
| 837 | */ | |
| 838 | ||
| 839 | /* | |
| 840 | * Bank 5 EEProm and Mailbox | |
| 841 | * | |
| 842 | * The EEPROM and mailbox live on the same chip select. | |
| 843 | * the eeprom is selected if the MSb of the address is set and the mailbox is | |
| 844 | * selected if the MSb of the address is clear. | |
| 845 | * | |
| 846 | */ | |
| 847 | ||
| 848 | /* BR5 is configured as follows: | |
| 849 | * | |
| 850 | * - Base address of 0x32000000/0xF2000000 | |
| 851 | * - 8 bit | |
| 852 | * - Data error checking disabled | |
| 853 | * - Read/Write access | |
| 854 | * - GPCM 60x Bus | |
| 855 | * - SDRAM local bus | |
| 856 | * - No data pipelining is done | |
| 857 | * - Valid | |
| 858 | */ | |
| 859 | ||
| 6d0f6bcf | 860 | #define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_MAILBOX_BASE & BRx_BA_MSK) |\ |
| fe8c2806 WD |
861 | BRx_PS_8 |\ |
| 862 | BRx_DECC_NONE |\ | |
| 863 | BRx_MS_GPCM_P |\ | |
| 864 | BRx_V) | |
| 865 | /* OR5 is configured as follows | |
| 866 | * - buffer control enabled | |
| 867 | * - chip select negated normally | |
| 868 | * - CS output 1/2 clock after address | |
| 869 | * - 15 wait states | |
| 870 | * - *PSDVAL is generated internally by the memory controller | |
| 871 | * unless *GTA is asserted earlier externally. | |
| 872 | * - Relaxed timing is generated by the GPCM for accesses | |
| 873 | * initiated to this memory region. | |
| 874 | * - One idle clock is inserted between a read access from the | |
| 875 | * current bank and the next access. | |
| 876 | */ | |
| 877 | ||
| 6d0f6bcf | 878 | #define CONFIG_SYS_OR5_PRELIM ((P2SZ_TO_AM(CONFIG_SYS_MAILBOX_SIZE) & ~0x80000000) |\ |
| fe8c2806 WD |
879 | ORxG_ACS_DIV2 |\ |
| 880 | ORxG_SCY_15_CLK |\ | |
| 881 | ORxG_TRLX |\ | |
| 882 | ORxG_EHTR) | |
| 883 | ||
| 884 | /*----------------------------------------------------------------------- | |
| 885 | * BR6 - Base Register | |
| 886 | * Ref: Section 10.3.1 on page 10-14 | |
| 887 | * OR6 - Option Register | |
| 888 | * Ref: Section 10.3.2 on page 10-18 | |
| 889 | *----------------------------------------------------------------------- | |
| 890 | */ | |
| 891 | ||
| 892 | /* Bank 6 - I/O select | |
| 893 | * | |
| 894 | */ | |
| 895 | ||
| 896 | /* BR6 is configured as follows: | |
| 897 | * | |
| 898 | * - Base address of 0xE0000000 | |
| 899 | * - 16 bit port size | |
| 900 | * - Data errors checking is disabled | |
| 901 | * - Read and write access | |
| 902 | * - GPCM 60x bus | |
| 903 | * - Access are handled by the memory controller according to MSEL | |
| 904 | * - Not used for atomic operations | |
| 905 | * - No data pipelining is done | |
| 906 | * - Valid | |
| 907 | */ | |
| 6d0f6bcf | 908 | #define CONFIG_SYS_BR6_PRELIM ((CONFIG_SYS_IOSELECT_BASE & BRx_BA_MSK) |\ |
| fe8c2806 WD |
909 | BRx_PS_16 |\ |
| 910 | BRx_MS_GPCM_P |\ | |
| 911 | BRx_V) | |
| 912 | ||
| 913 | /* OR6 is configured as follows | |
| 914 | * - buffer control enabled | |
| 915 | * - chip select negated normally | |
| 916 | * - CS output 1/2 clock after address | |
| 917 | * - 15 wait states | |
| 918 | * - *PSDVAL is generated internally by the memory controller | |
| 919 | * unless *GTA is asserted earlier externally. | |
| 920 | * - Relaxed timing is generated by the GPCM for accesses | |
| 921 | * initiated to this memory region. | |
| 922 | * - One idle clock is inserted between a read access from the | |
| 923 | * current bank and the next access. | |
| 924 | */ | |
| 925 | ||
| 6d0f6bcf | 926 | #define CONFIG_SYS_OR6_PRELIM (MEG_TO_AM(CONFIG_SYS_IOSELECT_SIZE) |\ |
| fe8c2806 WD |
927 | ORxG_ACS_DIV2 |\ |
| 928 | ORxG_SCY_15_CLK |\ | |
| 929 | ORxG_TRLX |\ | |
| 930 | ORxG_EHTR) | |
| 931 | ||
| 932 | ||
| 933 | /*----------------------------------------------------------------------- | |
| 934 | * BR7 - Base Register | |
| 935 | * Ref: Section 10.3.1 on page 10-14 | |
| 936 | * OR7 - Option Register | |
| 937 | * Ref: Section 10.3.2 on page 10-18 | |
| 938 | *----------------------------------------------------------------------- | |
| 939 | */ | |
| 940 | ||
| 941 | /* Bank 7 - LEDs and switches | |
| 942 | * | |
| 943 | * LEDs are at 0x00001 (write only) | |
| 944 | * switches are at 0x00001 (read only) | |
| 945 | */ | |
| 6d0f6bcf | 946 | #ifdef CONFIG_SYS_LED_BASE |
| fe8c2806 WD |
947 | |
| 948 | /* BR7 is configured as follows: | |
| 949 | * | |
| 950 | * - Base address of 0xA0000000 | |
| 951 | * - 8 bit port size | |
| 952 | * - Data errors checking is disabled | |
| 953 | * - Read and write access | |
| 954 | * - GPCM 60x bus | |
| 955 | * - Access are handled by the memory controller according to MSEL | |
| 956 | * - Not used for atomic operations | |
| 957 | * - No data pipelining is done | |
| 958 | * - Valid | |
| 959 | */ | |
| 6d0f6bcf | 960 | #define CONFIG_SYS_BR7_PRELIM ((CONFIG_SYS_LED_BASE & BRx_BA_MSK) |\ |
| fe8c2806 WD |
961 | BRx_PS_8 |\ |
| 962 | BRx_DECC_NONE |\ | |
| 963 | BRx_MS_GPCM_P |\ | |
| 964 | BRx_V) | |
| 965 | ||
| 966 | /* OR7 is configured as follows: | |
| 967 | * | |
| 968 | * - 1 byte | |
| 969 | * - *BCTL0 is asserted upon access to the current memory bank | |
| 970 | * - *CW / *WE are negated a quarter of a clock earlier | |
| 971 | * - *CS is output at the same time as the address lines | |
| 972 | * - Uses a clock cycle length of 15 | |
| 973 | * - *PSDVAL is generated internally by the memory controller | |
| 974 | * unless *GTA is asserted earlier externally. | |
| 975 | * - Relaxed timing is generated by the GPCM for accesses | |
| 976 | * initiated to this memory region. | |
| 977 | * - One idle clock is inserted between a read access from the | |
| 978 | * current bank and the next access. | |
| 979 | */ | |
| 6d0f6bcf | 980 | #define CONFIG_SYS_OR7_PRELIM (ORxG_AM_MSK |\ |
| fe8c2806 WD |
981 | ORxG_CSNT |\ |
| 982 | ORxG_ACS_DIV1 |\ | |
| 983 | ORxG_SCY_15_CLK |\ | |
| 984 | ORxG_TRLX |\ | |
| 985 | ORxG_EHTR) | |
| 6d0f6bcf | 986 | #endif /* CONFIG_SYS_LED_BASE */ |
| fe8c2806 | 987 | #endif /* __CONFIG_H */ |