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0d19f6c8 IY |
1 | /* |
2 | * Copyright (C) 2009, Ilya Yanok, Emcraft Systems, <yanok@emcraft.com> | |
3 | * | |
4 | * Configuration settings for the Dave/DENX QongEVB-LITE board. | |
5 | * | |
3765b3e7 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
0d19f6c8 IY |
7 | */ |
8 | ||
9 | #ifndef __CONFIG_H | |
10 | #define __CONFIG_H | |
11 | ||
86271115 | 12 | #include <asm/arch/imx-regs.h> |
0d19f6c8 | 13 | |
22a9ea97 | 14 | /* High Level Configuration Options */ |
8a508e30 FE |
15 | #define CONFIG_ARM1136 /* This is an arm1136 CPU core */ |
16 | #define CONFIG_MX31 /* in a mx31 */ | |
17 | #define CONFIG_QONG | |
0d19f6c8 IY |
18 | |
19 | #define CONFIG_DISPLAY_CPUINFO | |
20 | #define CONFIG_DISPLAY_BOARDINFO | |
21 | ||
22a9ea97 SB |
22 | #define CONFIG_SYS_TEXT_BASE 0xa0000000 |
23 | ||
8a508e30 FE |
24 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ |
25 | #define CONFIG_SETUP_MEMORY_TAGS | |
26 | #define CONFIG_INITRD_TAG | |
0d19f6c8 IY |
27 | |
28 | /* | |
29 | * Size of malloc() pool | |
30 | */ | |
544aa66a | 31 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1536 * 1024) |
0d19f6c8 IY |
32 | |
33 | /* | |
34 | * Hardware drivers | |
35 | */ | |
36 | ||
40f6fffe SB |
37 | #define CONFIG_MXC_UART |
38 | #define CONFIG_MXC_UART_BASE UART1_BASE | |
0d19f6c8 | 39 | |
c4ea1424 | 40 | #define CONFIG_MXC_GPIO |
8640c984 | 41 | #define CONFIG_HW_WATCHDOG |
abbab703 | 42 | #define CONFIG_IMX_WATCHDOG |
45997e0a | 43 | |
e98ecd71 SB |
44 | #define CONFIG_MXC_SPI |
45 | #define CONFIG_DEFAULT_SPI_BUS 1 | |
9f481e95 | 46 | #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) |
4e8b7544 | 47 | #define CONFIG_RTC_MC13XXX |
e98ecd71 | 48 | |
be3b51aa ŁM |
49 | #define CONFIG_POWER |
50 | #define CONFIG_POWER_SPI | |
51 | #define CONFIG_POWER_FSL | |
e98ecd71 SB |
52 | #define CONFIG_FSL_PMIC_BUS 1 |
53 | #define CONFIG_FSL_PMIC_CS 0 | |
54 | #define CONFIG_FSL_PMIC_CLK 100000 | |
9f481e95 | 55 | #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) |
f33bd087 | 56 | #define CONFIG_FSL_PMIC_BITLEN 32 |
e98ecd71 | 57 | |
0d19f6c8 | 58 | /* FPGA */ |
b9eb3fdf | 59 | #define CONFIG_FPGA |
8a508e30 | 60 | #define CONFIG_QONG_FPGA |
0d19f6c8 | 61 | #define CONFIG_FPGA_BASE (CS1_BASE) |
b9eb3fdf SB |
62 | #define CONFIG_FPGA_LATTICE |
63 | #define CONFIG_FPGA_COUNT 1 | |
0d19f6c8 IY |
64 | |
65 | #ifdef CONFIG_QONG_FPGA | |
66 | /* Ethernet */ | |
8a508e30 | 67 | #define CONFIG_DNET |
0d19f6c8 | 68 | #define CONFIG_DNET_BASE (CS1_BASE + QONG_FPGA_PERIPH_SIZE) |
0d19f6c8 | 69 | |
7c8cf0d0 | 70 | /* Framebuffer and LCD */ |
62a22dca HR |
71 | #define CONFIG_VIDEO |
72 | #define CONFIG_CFB_CONSOLE | |
7c8cf0d0 | 73 | #define CONFIG_VIDEO_MX3 |
62a22dca HR |
74 | #define CONFIG_VIDEO_LOGO |
75 | #define CONFIG_VIDEO_SW_CURSOR | |
76 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
7c8cf0d0 | 77 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV |
62a22dca | 78 | #define CONFIG_SPLASH_SCREEN |
7c8cf0d0 SB |
79 | #define CONFIG_CMD_BMP |
80 | #define CONFIG_BMP_16BPP | |
544aa66a WD |
81 | #define CONFIG_VIDEO_BMP_GZIP |
82 | #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (512 << 10) | |
7c8cf0d0 | 83 | |
d7dc464b SB |
84 | /* USB */ |
85 | #define CONFIG_CMD_USB | |
86 | #ifdef CONFIG_CMD_USB | |
87 | #define CONFIG_USB_EHCI /* Enable EHCI USB support */ | |
88 | #define CONFIG_USB_EHCI_MXC | |
89 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
90 | #define CONFIG_MXC_USB_PORT 2 | |
91 | #define CONFIG_MXC_USB_PORTSC (MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT) | |
92 | #define CONFIG_MXC_USB_FLAGS MXC_EHCI_POWER_PINS_ENABLED | |
93 | #define CONFIG_EHCI_IS_TDI | |
94 | #define CONFIG_USB_STORAGE | |
95 | #define CONFIG_DOS_PARTITION | |
96 | #define CONFIG_SUPPORT_VFAT | |
b952c24a | 97 | #define CONFIG_CMD_EXT2 |
d7dc464b SB |
98 | #define CONFIG_CMD_FAT |
99 | #endif /* CONFIG_CMD_USB */ | |
100 | ||
0d19f6c8 IY |
101 | /* |
102 | * Reducing the ARP timeout from default 5 seconds to 200ms we speed up the | |
103 | * initial TFTP transfer, should the user wish one, significantly. | |
104 | */ | |
105 | #define CONFIG_ARP_TIMEOUT 200UL | |
106 | ||
107 | #endif /* CONFIG_QONG_FPGA */ | |
108 | ||
109 | #define CONFIG_CONS_INDEX 1 | |
110 | #define CONFIG_BAUDRATE 115200 | |
0d19f6c8 IY |
111 | |
112 | /*********************************************************** | |
113 | * Command definition | |
114 | ***********************************************************/ | |
115 | ||
116 | #include <config_cmd_default.h> | |
117 | ||
7e4a9e6d | 118 | #define CONFIG_CMD_CACHE |
b952c24a | 119 | #define CONFIG_CMD_DATE |
0d19f6c8 | 120 | #define CONFIG_CMD_DHCP |
0d19f6c8 | 121 | #define CONFIG_CMD_MII |
45997e0a | 122 | #define CONFIG_CMD_NAND |
b952c24a WD |
123 | #define CONFIG_CMD_NET |
124 | #define CONFIG_CMD_PING | |
125 | #define CONFIG_CMD_SETEXPR | |
e98ecd71 | 126 | #define CONFIG_CMD_SPI |
544aa66a | 127 | #define CONFIG_CMD_UNZIP |
0d19f6c8 | 128 | |
9660e442 | 129 | #define CONFIG_BOARD_LATE_INIT |
0d19f6c8 IY |
130 | |
131 | #define CONFIG_BOOTDELAY 5 | |
132 | ||
133 | #define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */ | |
134 | ||
0d19f6c8 IY |
135 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
136 | "netdev=eth0\0" \ | |
137 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
138 | "nfsroot=${serverip}:${rootpath}\0" \ | |
139 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
140 | "addip=setenv bootargs ${bootargs} " \ | |
141 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
142 | ":${hostname}:${netdev}:off panic=1\0" \ | |
143 | "addtty=setenv bootargs ${bootargs}" \ | |
144 | " console=ttymxc0,${baudrate}\0" \ | |
b4e85d0f | 145 | "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ |
0d19f6c8 | 146 | "addmisc=setenv bootargs ${bootargs}\0" \ |
8a1cdaa9 | 147 | "uboot_addr=A0000000\0" \ |
b952c24a | 148 | "kernel_addr=A00C0000\0" \ |
8a1cdaa9 | 149 | "ramdisk_addr=A0300000\0" \ |
b4e85d0f | 150 | "u-boot=qong/u-boot.bin\0" \ |
0d19f6c8 IY |
151 | "kernel_addr_r=80800000\0" \ |
152 | "hostname=qong\0" \ | |
153 | "bootfile=qong/uImage\0" \ | |
154 | "rootpath=/opt/eldk-4.2-arm/armVFP\0" \ | |
b4e85d0f | 155 | "flash_self=run ramargs addip addtty addmtd addmisc;" \ |
0d19f6c8 | 156 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
b4e85d0f | 157 | "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ |
0d19f6c8 IY |
158 | "bootm ${kernel_addr}\0" \ |
159 | "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ | |
b4e85d0f | 160 | "run nfsargs addip addtty addmtd addmisc;" \ |
0d19f6c8 | 161 | "bootm\0" \ |
b4e85d0f IY |
162 | "bootcmd=run flash_self\0" \ |
163 | "load=tftp ${loadaddr} ${u-boot}\0" \ | |
93ea89f0 MV |
164 | "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ |
165 | " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ | |
0d19f6c8 | 166 | " +${filesize};cp.b ${fileaddr} " \ |
93ea89f0 | 167 | __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ |
0d19f6c8 | 168 | "upd=run load update\0" \ |
62a22dca HR |
169 | "videomode=video=ctfb:x:640,y:480,depth:16,mode:0,pclk:40000," \ |
170 | "le:120,ri:40,up:35,lo:10,hs:30,vs:3,sync:100663296," \ | |
171 | "vmode:0\0" \ | |
0d19f6c8 IY |
172 | |
173 | /* | |
174 | * Miscellaneous configurable options | |
175 | */ | |
176 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
b4e85d0f | 177 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ |
0d19f6c8 IY |
178 | /* Print Buffer Size */ |
179 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
180 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
181 | #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ | |
182 | /* Boot Argument Buffer Size */ | |
183 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
184 | ||
185 | /* memtest works on first 255MB of RAM */ | |
186 | #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 | |
187 | #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0xff000000) | |
188 | ||
189 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR | |
190 | ||
8a508e30 FE |
191 | #define CONFIG_CMDLINE_EDITING |
192 | #define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ | |
0d19f6c8 | 193 | |
8a508e30 | 194 | #define CONFIG_MISC_INIT_R |
0d19f6c8 IY |
195 | |
196 | /*----------------------------------------------------------------------- | |
197 | * Physical Memory Map | |
198 | */ | |
199 | #define CONFIG_NR_DRAM_BANKS 1 | |
200 | #define PHYS_SDRAM_1 CSD0_BASE | |
201 | #define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */ | |
202 | ||
45997e0a SB |
203 | /* |
204 | * NAND driver | |
205 | */ | |
206 | ||
207 | #ifndef __ASSEMBLY__ | |
208 | extern void qong_nand_plat_init(void *chip); | |
209 | extern int qong_nand_rdy(void *chip); | |
210 | #endif | |
211 | #define CONFIG_NAND_PLAT | |
212 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
213 | #define CONFIG_SYS_NAND_BASE CS3_BASE | |
214 | #define NAND_PLAT_INIT() qong_nand_plat_init(nand) | |
215 | ||
216 | #define QONG_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 24)) | |
217 | #define QONG_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 23)) | |
218 | #define QONG_NAND_WRITE(addr, cmd) \ | |
219 | do { \ | |
220 | __REG8(addr) = cmd; \ | |
221 | } while (0) | |
222 | ||
223 | #define NAND_PLAT_WRITE_CMD(chip, cmd) QONG_NAND_WRITE(QONG_NAND_CLE(chip), cmd) | |
224 | #define NAND_PLAT_WRITE_ADR(chip, cmd) QONG_NAND_WRITE(QONG_NAND_ALE(chip), cmd) | |
225 | #define NAND_PLAT_DEV_READY(chip) (qong_nand_rdy(chip)) | |
226 | ||
0d19f6c8 IY |
227 | /*----------------------------------------------------------------------- |
228 | * FLASH and environment organization | |
229 | */ | |
230 | #define CONFIG_SYS_FLASH_BASE CS0_BASE | |
231 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
232 | /* max number of sectors on one chip */ | |
233 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 | |
234 | /* Monitor at beginning of flash */ | |
235 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
236 | #define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256KiB */ | |
237 | ||
8a508e30 | 238 | #define CONFIG_ENV_IS_IN_FLASH |
0d19f6c8 IY |
239 | #define CONFIG_ENV_SECT_SIZE 0x20000 |
240 | #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE | |
d7dc464b | 241 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x80000) |
0d19f6c8 IY |
242 | |
243 | /* Address and size of Redundant Environment Sector */ | |
244 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) | |
245 | #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE | |
246 | ||
247 | /*----------------------------------------------------------------------- | |
248 | * CFI FLASH driver setup | |
249 | */ | |
250 | /* Flash memory is CFI compliant */ | |
8a508e30 | 251 | #define CONFIG_SYS_FLASH_CFI |
0d19f6c8 | 252 | /* Use drivers/cfi_flash.c */ |
8a508e30 | 253 | #define CONFIG_FLASH_CFI_DRIVER |
0d19f6c8 | 254 | /* Use buffered writes (~10x faster) */ |
8a508e30 | 255 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
0d19f6c8 | 256 | /* Use hardware sector protection */ |
8a508e30 | 257 | #define CONFIG_SYS_FLASH_PROTECTION |
0d19f6c8 IY |
258 | |
259 | /* | |
c9d944d3 | 260 | * Filesystem |
0d19f6c8 | 261 | */ |
c9d944d3 SB |
262 | #define CONFIG_CMD_JFFS2 |
263 | #define CONFIG_CMD_UBI | |
264 | #define CONFIG_CMD_UBIFS | |
265 | #define CONFIG_RBTREE | |
266 | #define CONFIG_MTD_PARTITIONS | |
68d7d651 | 267 | #define CONFIG_CMD_MTDPARTS |
c9d944d3 | 268 | #define CONFIG_LZO |
942556a9 SR |
269 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
270 | #define CONFIG_FLASH_CFI_MTD | |
b952c24a WD |
271 | #define MTDIDS_DEFAULT "nor0=physmap-flash.0," \ |
272 | "nand0=gen_nand" | |
b4e85d0f | 273 | #define MTDPARTS_DEFAULT \ |
b952c24a WD |
274 | "mtdparts=physmap-flash.0:" \ |
275 | "512k(U-Boot),128k(env1),128k(env2)," \ | |
276 | "2304k(kernel),13m(ramdisk),-(user);" \ | |
277 | "gen_nand:" \ | |
278 | "128m(nand)" | |
0d19f6c8 | 279 | |
a784c01a | 280 | /* additions for new relocation code, must be added to all boards */ |
e48b7c0a HS |
281 | #define CONFIG_SYS_SDRAM_BASE 0x80000000 |
282 | #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR | |
553f0982 | 283 | #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE |
25ddd1fb | 284 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
e48b7c0a HS |
285 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET) |
286 | ||
8a508e30 | 287 | #define CONFIG_BOARD_EARLY_INIT_F |
e48b7c0a | 288 | |
0d19f6c8 | 289 | #endif /* __CONFIG_H */ |