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Commit | Line | Data |
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c133c1fb YG |
1 | /* |
2 | * Configuation settings for the Renesas R7780MP board | |
3 | * | |
ec39d479 | 4 | * Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
c133c1fb YG |
5 | * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com> |
6 | * | |
1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
c133c1fb YG |
8 | */ |
9 | ||
10 | #ifndef __R7780RP_H | |
11 | #define __R7780RP_H | |
12 | ||
13 | #undef DEBUG | |
14 | #define CONFIG_SH 1 | |
15 | #define CONFIG_SH4A 1 | |
16 | #define CONFIG_CPU_SH7780 1 | |
17 | #define CONFIG_R7780MP 1 | |
6d0f6bcf | 18 | #define CONFIG_SYS_R7780MP_OLD_FLASH 1 |
ec39d479 | 19 | #define __LITTLE_ENDIAN__ 1 |
c133c1fb YG |
20 | |
21 | /* | |
22 | * Command line configuration. | |
23 | */ | |
24 | #define CONFIG_CMD_SDRAM | |
25 | #define CONFIG_CMD_FLASH | |
26 | #define CONFIG_CMD_MEMORY | |
27 | #define CONFIG_CMD_PCI | |
28 | #define CONFIG_CMD_NET | |
29 | #define CONFIG_CMD_PING | |
bdab39d3 | 30 | #define CONFIG_CMD_SAVEENV |
c133c1fb YG |
31 | #define CONFIG_CMD_NFS |
32 | #define CONFIG_CMD_IDE | |
33 | #define CONFIG_CMD_EXT2 | |
34 | #define CONFIG_DOS_PARTITION | |
35 | ||
6c58a030 | 36 | #define CONFIG_SCIF_CONSOLE 1 |
c133c1fb YG |
37 | #define CONFIG_BAUDRATE 115200 |
38 | #define CONFIG_CONS_SCIF0 1 | |
39 | ||
40 | #define CONFIG_BOOTDELAY 3 | |
41 | #define CONFIG_BOOTARGS "console=ttySC0,115200" | |
42 | #define CONFIG_ENV_OVERWRITE 1 | |
43 | ||
44 | /* check for keypress on bootdelay==0 */ | |
45 | /*#define CONFIG_ZERO_BOOTDELAY_CHECK*/ | |
46 | ||
913c8910 | 47 | #define CONFIG_SYS_TEXT_BASE 0x0FFC0000 |
6d0f6bcf JCPV |
48 | #define CONFIG_SYS_SDRAM_BASE (0x08000000) |
49 | #define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024) | |
c133c1fb | 50 | |
6d0f6bcf | 51 | #define CONFIG_SYS_LONGHELP |
6d0f6bcf JCPV |
52 | #define CONFIG_SYS_CBSIZE 256 |
53 | #define CONFIG_SYS_PBSIZE 256 | |
54 | #define CONFIG_SYS_MAXARGS 16 | |
55 | #define CONFIG_SYS_BARGSIZE 512 | |
c133c1fb | 56 | |
6d0f6bcf | 57 | #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) |
14d0a02a | 58 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000) |
c133c1fb | 59 | |
ec39d479 | 60 | /* Flash board support */ |
6d0f6bcf JCPV |
61 | #define CONFIG_SYS_FLASH_BASE (0xA0000000) |
62 | #ifdef CONFIG_SYS_R7780MP_OLD_FLASH | |
ec39d479 | 63 | /* NOR Flash (S29PL127J60TFI130) */ |
6d0f6bcf JCPV |
64 | # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT |
65 | # define CONFIG_SYS_MAX_FLASH_BANKS (2) | |
66 | # define CONFIG_SYS_MAX_FLASH_SECT 270 | |
67 | # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ | |
68 | CONFIG_SYS_FLASH_BASE + 0x100000,\ | |
69 | CONFIG_SYS_FLASH_BASE + 0x400000,\ | |
70 | CONFIG_SYS_FLASH_BASE + 0x700000, } | |
71 | #else /* CONFIG_SYS_R7780MP_OLD_FLASH */ | |
ec39d479 | 72 | /* NOR Flash (Spantion S29GL256P) */ |
6d0f6bcf JCPV |
73 | # define CONFIG_SYS_MAX_FLASH_BANKS (1) |
74 | # define CONFIG_SYS_MAX_FLASH_SECT 256 | |
75 | # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
76 | #endif /* CONFIG_SYS_R7780MP_OLD_FLASH */ | |
c133c1fb | 77 | |
6d0f6bcf | 78 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024) |
c133c1fb | 79 | /* Address of u-boot image in Flash */ |
6d0f6bcf JCPV |
80 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) |
81 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) | |
c133c1fb | 82 | /* Size of DRAM reserved for malloc() use */ |
6d0f6bcf | 83 | #define CONFIG_SYS_MALLOC_LEN (1204 * 1024) |
c133c1fb | 84 | |
6d0f6bcf JCPV |
85 | #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) |
86 | #define CONFIG_SYS_RX_ETH_BUFFER (8) | |
c133c1fb | 87 | |
6d0f6bcf | 88 | #define CONFIG_SYS_FLASH_CFI |
00b1883a | 89 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
90 | #undef CONFIG_SYS_FLASH_CFI_BROKEN_TABLE |
91 | #undef CONFIG_SYS_FLASH_QUIET_TEST | |
c133c1fb | 92 | /* print 'E' for empty sector on flinfo */ |
6d0f6bcf | 93 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
c133c1fb | 94 | |
5a1aceb0 | 95 | #define CONFIG_ENV_IS_IN_FLASH |
0e8d1586 JCPV |
96 | #define CONFIG_ENV_SECT_SIZE (256 * 1024) |
97 | #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) | |
6d0f6bcf JCPV |
98 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
99 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 | |
100 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 | |
c133c1fb YG |
101 | |
102 | /* Board Clock */ | |
103 | #define CONFIG_SYS_CLK_FREQ 33333333 | |
684a501e NI |
104 | #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ |
105 | #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ | |
be45c632 | 106 | #define CONFIG_SYS_TMU_CLK_DIV 4 |
c133c1fb YG |
107 | |
108 | /* PCI Controller */ | |
109 | #if defined(CONFIG_CMD_PCI) | |
110 | #define CONFIG_PCI | |
111 | #define CONFIG_SH4_PCI | |
ab8f4d40 | 112 | #define CONFIG_SH7780_PCI |
06b18163 YS |
113 | #define CONFIG_SH7780_PCI_LSR 0x07f00001 |
114 | #define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE | |
115 | #define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE | |
c133c1fb YG |
116 | #define CONFIG_PCI_PNP |
117 | #define CONFIG_PCI_SCAN_SHOW 1 | |
118 | #define __io | |
119 | #define __mem_pci | |
120 | ||
121 | #define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */ | |
122 | #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS | |
123 | #define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */ | |
124 | ||
125 | #define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */ | |
126 | #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS | |
127 | #define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */ | |
04366d07 NI |
128 | #define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE |
129 | #define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE | |
130 | #define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE | |
c133c1fb YG |
131 | #endif /* CONFIG_CMD_PCI */ |
132 | ||
133 | #if defined(CONFIG_CMD_NET) | |
ec39d479 | 134 | /* |
ec39d479 NI |
135 | #define CONFIG_RTL8169 |
136 | */ | |
c7c1dbbf | 137 | /* AX88796L Support(NE2000 base chip) */ |
c133c1fb YG |
138 | #define CONFIG_DRIVER_AX88796L |
139 | #define CONFIG_DRIVER_NE2000_BASE 0xA4100000 | |
140 | #endif | |
141 | ||
142 | /* Compact flash Support */ | |
143 | #if defined(CONFIG_CMD_IDE) | |
144 | #define CONFIG_IDE_RESET 1 | |
6d0f6bcf JCPV |
145 | #define CONFIG_SYS_PIO_MODE 1 |
146 | #define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */ | |
147 | #define CONFIG_SYS_IDE_MAXDEVICE 1 | |
148 | #define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000 | |
149 | #define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */ | |
150 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */ | |
151 | #define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */ | |
152 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */ | |
f2a37fcd | 153 | #define CONFIG_IDE_SWAP_IO |
c133c1fb YG |
154 | #endif /* CONFIG_CMD_IDE */ |
155 | ||
156 | #endif /* __R7780RP_H */ |