[people/ms/u-boot.git] / include / configs / sbc35_a9g20.h

/*
 * Copyright (C) 2009
 * Albin Tonnerre, Free Electrons <albin.tonnerre@free-electrons.com>
 *
 * Configuation settings for the Calao SBC35-A9G20 board
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* SoC type is defined in boards.cfg */
#include <asm/hardware.h>
#include <asm/sizes.h>

#if defined(CONFIG_SYS_USE_NANDFLASH)
#define CONFIG_ENV_IS_IN_NAND
#else
#define CONFIG_ENV_IS_IN_EEPROM
#endif

#define MACH_TYPE_SBC35_A9G20		1848
#define CONFIG_MACH_TYPE		MACH_TYPE_SBC35_A9G20

/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
#define CONFIG_SYS_AT91_MAIN_CLOCK	12000000	/* 12.000 MHz crystal */

#define CONFIG_ARCH_CPU_INIT

#define CONFIG_CMDLINE_TAG              /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_SKIP_LOWLEVEL_INIT

/* GPIO */
#define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
#define CONFIG_AT91_GPIO

/* Serial */
#define CONFIG_ATMEL_USART
#define CONFIG_USART_BASE               ATMEL_BASE_DBGU
#define CONFIG_USART_ID                 ATMEL_ID_SYS
#define CONFIG_BAUDRATE			115200

#define CONFIG_BOOTDELAY	3

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>
#undef CONFIG_CMD_BDI
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_IMI
#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_SOURCE

#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_USB

/* SDRAM */
#define CONFIG_NR_DRAM_BANKS	1
#define CONFIG_SYS_SDRAM_BASE	ATMEL_BASE_CS1
#define CONFIG_SYS_SDRAM_SIZE	0x04000000	/* 64 megs */
#define CONFIG_SYS_INIT_SP_ADDR	(ATMEL_BASE_SRAM1 + 0x1000 - \
				 GENERATED_GBL_DATA_SIZE)

/* SPI EEPROM */
#define CONFIG_SPI
#define CONFIG_CMD_SPI
#define CONFIG_ATMEL_SPI
#define CONFIG_SYS_SPI_WRITE_TOUT	(5 * CONFIG_SYS_HZ)

#define CONFIG_CMD_EEPROM
#define CONFIG_SPI_M95XXX
#define CONFIG_SYS_EEPROM_SIZE 0x10000
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5

/* SPI RTC */
#define CONFIG_CMD_DATE
#define CONFIG_RTC_M41T94
#define CONFIG_M41T94_SPI_BUS 0
#define CONFIG_M41T94_SPI_CS 0

/* NAND flash */
#define CONFIG_CMD_NAND
#define CONFIG_NAND_ATMEL
#define CONFIG_SYS_MAX_NAND_DEVICE		1
#define CONFIG_SYS_NAND_BASE			0x40000000
#define CONFIG_SYS_NAND_DBW_8
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
/* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PC14
#define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PC13

/* NOR flash - no real flash on this board */
#define CONFIG_SYS_NO_FLASH			1

/* Ethernet */
#define CONFIG_MACB
#define CONFIG_RMII
#define CONFIG_NET_RETRY_COUNT		20
#define CONFIG_RESET_PHY_R
#define CONFIG_MACB_SEARCH_PHY

/* USB */
#define CONFIG_USB_ATMEL
#define CONFIG_USB_OHCI_NEW
#define CONFIG_DOS_PARTITION
#define CONFIG_SYS_USB_OHCI_CPU_INIT
#define CONFIG_SYS_USB_OHCI_REGS_BASE	0x00500000	/* AT91SAM9260_UHP_BASE */
#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"at91sam9260"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
#define CONFIG_USB_STORAGE
#define CONFIG_CMD_FAT

#define CONFIG_SYS_LOAD_ADDR		0x22000000	/* load address */

#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END		0x23e00000

/* Env in EEPROM, bootstrap + u-boot in NAND*/
#ifdef CONFIG_ENV_IS_IN_EEPROM
#define CONFIG_ENV_OFFSET	0x20
#define CONFIG_ENV_SIZE		0x1000
#endif

/* Env, bootstrap and u-boot in NAND */
#ifdef CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET		0x60000
#define CONFIG_ENV_OFFSET_REDUND	0x80000
#define CONFIG_ENV_SIZE			0x20000
#endif

#define CONFIG_BOOTCOMMAND	"nboot 0x21000000 0 400000"
#define CONFIG_BOOTARGS		"console=ttyS0,115200 " \
				"root=/dev/mtdblock1 " \
				"mtdparts=atmel_nand:16M(kernel)ro," \
				"120M(rootfs),-(other) " \
				"rw rootfstype=jffs2"


#define CONFIG_SYS_PROMPT	"U-Boot> "
#define CONFIG_SYS_CBSIZE	256
#define CONFIG_SYS_MAXARGS	16
#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_LONGHELP	1
#define CONFIG_CMDLINE_EDITING	1

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN	ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)

#endif
Commit	Line	Data
9453967e AT	1	/*
	2	* Copyright (C) 2009
	3	* Albin Tonnerre, Free Electrons <albin.tonnerre@free-electrons.com>
	4	*
	5	* Configuation settings for the Calao SBC35-A9G20 board
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
9453967e AT	8	*/
	9
	10	#ifndef __CONFIG_H
	11	#define __CONFIG_H
	12
6785c7c8 TP	13	/* SoC type is defined in boards.cfg */
	14	#include <asm/hardware.h>
	15	#include <asm/sizes.h>
425de62d	16
6785c7c8	17	#if defined(CONFIG_SYS_USE_NANDFLASH)
9453967e AT	18	#define CONFIG_ENV_IS_IN_NAND
	19	#else
	20	#define CONFIG_ENV_IS_IN_EEPROM
	21	#endif
	22
204ab93f AG	23	#define MACH_TYPE_SBC35_A9G20 1848
	24	#define CONFIG_MACH_TYPE MACH_TYPE_SBC35_A9G20
	25
9453967e	26	/* ARM asynchronous clock */
6785c7c8	27	#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
7c966a8b	28	#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12.000 MHz crystal */
9453967e AT	29
9453967e AT	30	#define CONFIG_ARCH_CPU_INIT
9453967e	31
6785c7c8 TP	32	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
	33	#define CONFIG_SETUP_MEMORY_TAGS
	34	#define CONFIG_INITRD_TAG
9453967e	35	#define CONFIG_SKIP_LOWLEVEL_INIT
9453967e	36
6785c7c8 TP	37	/* GPIO */
	38	#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
	39	#define CONFIG_AT91_GPIO
	40
	41	/* Serial */
9453967e	42	#define CONFIG_ATMEL_USART
6785c7c8 TP	43	#define CONFIG_USART_BASE ATMEL_BASE_DBGU
	44	#define CONFIG_USART_ID ATMEL_ID_SYS
	45	#define CONFIG_BAUDRATE 115200
9453967e AT	46
	47	#define CONFIG_BOOTDELAY 3
	48
	49	/*
	50	* BOOTP options
	51	*/
6785c7c8 TP	52	#define CONFIG_BOOTP_BOOTFILESIZE
	53	#define CONFIG_BOOTP_BOOTPATH
	54	#define CONFIG_BOOTP_GATEWAY
	55	#define CONFIG_BOOTP_HOSTNAME
9453967e AT	56
	57	/*
	58	* Command line configuration.
	59	*/
	60	#include <config_cmd_default.h>
	61	#undef CONFIG_CMD_BDI
	62	#undef CONFIG_CMD_FPGA
	63	#undef CONFIG_CMD_IMI
	64	#undef CONFIG_CMD_IMLS
	65	#undef CONFIG_CMD_LOADS
	66	#undef CONFIG_CMD_SOURCE
	67
6785c7c8 TP	68	#define CONFIG_CMD_PING
	69	#define CONFIG_CMD_DHCP
	70	#define CONFIG_CMD_USB
9453967e AT	71
	72	/* SDRAM */
	73	#define CONFIG_NR_DRAM_BANKS 1
6785c7c8 TP	74	#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
	75	#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 megs */
	76	#define CONFIG_SYS_INIT_SP_ADDR (ATMEL_BASE_SRAM1 + 0x1000 - \
	77	GENERATED_GBL_DATA_SIZE)
9453967e AT	78
	79	/* SPI EEPROM */
	80	#define CONFIG_SPI
	81	#define CONFIG_CMD_SPI
	82	#define CONFIG_ATMEL_SPI
	83	#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ)
	84
	85	#define CONFIG_CMD_EEPROM
	86	#define CONFIG_SPI_M95XXX
	87	#define CONFIG_SYS_EEPROM_SIZE 0x10000
	88	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
	89
	90	/* SPI RTC */
	91	#define CONFIG_CMD_DATE
	92	#define CONFIG_RTC_M41T94
	93	#define CONFIG_M41T94_SPI_BUS 0
	94	#define CONFIG_M41T94_SPI_CS 0
	95
	96	/* NAND flash */
	97	#define CONFIG_CMD_NAND
	98	#define CONFIG_NAND_ATMEL
	99	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	100	#define CONFIG_SYS_NAND_BASE 0x40000000
6785c7c8	101	#define CONFIG_SYS_NAND_DBW_8
9453967e AT	102	/* our ALE is AD21 */
	103	#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
	104	/* our CLE is AD22 */
	105	#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
	106	#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
	107	#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
	108
	109	/* NOR flash - no real flash on this board */
	110	#define CONFIG_SYS_NO_FLASH 1
	111
	112	/* Ethernet */
6785c7c8 TP	113	#define CONFIG_MACB
6785c7c8 TP	114	#define CONFIG_RMII
9453967e	115	#define CONFIG_NET_RETRY_COUNT 20
6785c7c8 TP	116	#define CONFIG_RESET_PHY_R
6785c7c8 TP	117	#define CONFIG_MACB_SEARCH_PHY
9453967e AT	118
	119	/* USB */
	120	#define CONFIG_USB_ATMEL
6785c7c8 TP	121	#define CONFIG_USB_OHCI_NEW
	122	#define CONFIG_DOS_PARTITION
	123	#define CONFIG_SYS_USB_OHCI_CPU_INIT
9453967e AT	124	#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9260_UHP_BASE */
	125	#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
	126	#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
6785c7c8 TP	127	#define CONFIG_USB_STORAGE
6785c7c8 TP	128	#define CONFIG_CMD_FAT
9453967e AT	129
	130	#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
	131
6785c7c8	132	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
9453967e AT	133	#define CONFIG_SYS_MEMTEST_END 0x23e00000
	134
	135	/* Env in EEPROM, bootstrap + u-boot in NAND*/
	136	#ifdef CONFIG_ENV_IS_IN_EEPROM
	137	#define CONFIG_ENV_OFFSET 0x20
	138	#define CONFIG_ENV_SIZE 0x1000
	139	#endif
	140
	141	/* Env, bootstrap and u-boot in NAND */
	142	#ifdef CONFIG_ENV_IS_IN_NAND
	143	#define CONFIG_ENV_OFFSET 0x60000
	144	#define CONFIG_ENV_OFFSET_REDUND 0x80000
	145	#define CONFIG_ENV_SIZE 0x20000
	146	#endif
	147
	148	#define CONFIG_BOOTCOMMAND "nboot 0x21000000 0 400000"
	149	#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
	150	"root=/dev/mtdblock1 " \
	151	"mtdparts=atmel_nand:16M(kernel)ro," \
	152	"120M(rootfs),-(other) " \
	153	"rw rootfstype=jffs2"
	154
9453967e AT	155
	156	#define CONFIG_SYS_PROMPT "U-Boot> "
	157	#define CONFIG_SYS_CBSIZE 256
	158	#define CONFIG_SYS_MAXARGS 16
	159	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	160	#define CONFIG_SYS_LONGHELP 1
	161	#define CONFIG_CMDLINE_EDITING 1
	162
	163	/*
	164	* Size of malloc() pool
	165	*/
	166	#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
9453967e AT	167
9453967e AT	168	#endif