[people/ms/u-boot.git] / include / configs / sh7763rdp.h

/*
 * Configuation settings for the Renesas SH7763RDP board
 *
 * Copyright (C) 2008 Renesas Solutions Corp.
 * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __SH7763RDP_H
#define __SH7763RDP_H

#define CONFIG_CPU_SH7763	1
#define CONFIG_SH7763RDP	1
#define __LITTLE_ENDIAN		1

/*
 * Command line configuration.
 */
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_JFFS2

#define CONFIG_BOOTARGS         "console=ttySC2,115200 root=1f01"
#define CONFIG_ENV_OVERWRITE    1

#define CONFIG_VERSION_VARIABLE
#undef  CONFIG_SHOW_BOOT_PROGRESS

/* SCIF */
#define CONFIG_SCIF_CONSOLE        1
#define CONFIG_BAUDRATE         115200
#define CONFIG_CONS_SCIF2		1

#define CONFIG_SYS_TEXT_BASE	0x8FFC0000
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_CBSIZE		256	/* Buffer size for input from the Console */
#define CONFIG_SYS_PBSIZE		256	/* Buffer size for Console output */
#define CONFIG_SYS_MAXARGS		16	/* max args accepted for monitor commands */
#define CONFIG_SYS_BARGSIZE	512	/* Buffer size for Boot Arguments
								passed to kernel */
#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }	/* List of legal baudrate
												settings for this board */

/* SDRAM */
#define CONFIG_SYS_SDRAM_BASE		(0x8C000000)
#define CONFIG_SYS_SDRAM_SIZE		(64 * 1024 * 1024)
#define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))

/* Flash(NOR) */
#define CONFIG_SYS_FLASH_BASE		(0xA0000000)
#define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT)
#define CONFIG_SYS_MAX_FLASH_BANKS (1)
#define CONFIG_SYS_MAX_FLASH_SECT  (520)

/* U-Boot setting */
#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_MONITOR_LEN		(128 * 1024)
/* Size of DRAM reserved for malloc() use */
#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)
#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)

#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#undef  CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_SYS_FLASH_EMPTY_INFO	/* print 'E' for empty sector on flinfo */
/* Timeout for Flash erase operations (in ms) */
#define CONFIG_SYS_FLASH_ERASE_TOUT	(3 * 1000)
/* Timeout for Flash write operations (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	(3 * 1000)
/* Timeout for Flash set sector lock bit operations (in ms) */
#define CONFIG_SYS_FLASH_LOCK_TOUT		(3 * 1000)
/* Timeout for Flash clear lock bit operations (in ms) */
#define CONFIG_SYS_FLASH_UNLOCK_TOUT	(3 * 1000)
/* Use hardware flash sectors protection instead of U-Boot software protection */
#undef  CONFIG_SYS_FLASH_PROTECTION
#undef  CONFIG_SYS_DIRECT_FLASH_TFTP
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE	(128 * 1024)
#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE))
/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
#define CONFIG_ENV_OFFSET		(CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))

/* Clock */
#define CONFIG_SYS_CLK_FREQ	66666666
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV		(4)	/* 4 (default), 16, 64, 256 or 1024 */

/* Ether */
#define CONFIG_SH_ETHER 1
#define CONFIG_SH_ETHER_USE_PORT (1)
#define CONFIG_SH_ETHER_PHY_ADDR (0x01)
#define CONFIG_PHYLIB
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII

#endif /* __SH7763RDP_H */
Commit	Line	Data
7faddaec NI	1	/*
	2	* Configuation settings for the Renesas SH7763RDP board
	3	*
	4	* Copyright (C) 2008 Renesas Solutions Corp.
	5	* Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
7faddaec NI	8	*/
	9
	10	#ifndef __SH7763RDP_H
	11	#define __SH7763RDP_H
	12
7faddaec NI	13	#define CONFIG_CPU_SH7763 1
	14	#define CONFIG_SH7763RDP 1
	15	#define __LITTLE_ENDIAN 1
	16
	17	/*
	18	* Command line configuration.
	19	*/
	20	#define CONFIG_CMD_SDRAM
ba932445	21	#define CONFIG_CMD_JFFS2
7faddaec	22
7faddaec NI	23	#define CONFIG_BOOTARGS "console=ttySC2,115200 root=1f01"
	24	#define CONFIG_ENV_OVERWRITE 1
	25
	26	#define CONFIG_VERSION_VARIABLE
	27	#undef CONFIG_SHOW_BOOT_PROGRESS
	28
	29	/* SCIF */
6c58a030	30	#define CONFIG_SCIF_CONSOLE 1
7faddaec NI	31	#define CONFIG_BAUDRATE 115200
	32	#define CONFIG_CONS_SCIF2 1
	33
00cb2e32	34	#define CONFIG_SYS_TEXT_BASE 0x8FFC0000
6d0f6bcf	35	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	36	#define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */
	37	#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
	38	#define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */
	39	#define CONFIG_SYS_BARGSIZE 512 /* Buffer size for Boot Arguments
7faddaec	40	passed to kernel */
6d0f6bcf	41	#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate
7faddaec NI	42	settings for this board */
7faddaec NI	43
7faddaec	44	/* SDRAM */
6d0f6bcf JCPV	45	#define CONFIG_SYS_SDRAM_BASE (0x8C000000)
	46	#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
	47	#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
	48	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
7faddaec NI	49
7faddaec NI	50	/* Flash(NOR) */
6d0f6bcf JCPV	51	#define CONFIG_SYS_FLASH_BASE (0xA0000000)
	52	#define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT)
	53	#define CONFIG_SYS_MAX_FLASH_BANKS (1)
	54	#define CONFIG_SYS_MAX_FLASH_SECT (520)
7faddaec	55
a187559e	56	/* U-Boot setting */
6d0f6bcf JCPV	57	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
	58	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
	59	#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
7faddaec	60	/* Size of DRAM reserved for malloc() use */
6d0f6bcf	61	#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
6d0f6bcf	62	#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
7faddaec	63
6d0f6bcf	64	#define CONFIG_SYS_FLASH_CFI
00b1883a	65	#define CONFIG_FLASH_CFI_DRIVER
6d0f6bcf JCPV	66	#undef CONFIG_SYS_FLASH_QUIET_TEST
6d0f6bcf JCPV	67	#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
7faddaec	68	/* Timeout for Flash erase operations (in ms) */
6d0f6bcf	69	#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
7faddaec	70	/* Timeout for Flash write operations (in ms) */
6d0f6bcf	71	#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
7faddaec	72	/* Timeout for Flash set sector lock bit operations (in ms) */
6d0f6bcf	73	#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
7faddaec	74	/* Timeout for Flash clear lock bit operations (in ms) */
6d0f6bcf	75	#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
7faddaec	76	/* Use hardware flash sectors protection instead of U-Boot software protection */
6d0f6bcf JCPV	77	#undef CONFIG_SYS_FLASH_PROTECTION
6d0f6bcf JCPV	78	#undef CONFIG_SYS_DIRECT_FLASH_TFTP
5a1aceb0	79	#define CONFIG_ENV_IS_IN_FLASH
0e8d1586 JCPV	80	#define CONFIG_ENV_SECT_SIZE (128 * 1024)
0e8d1586 JCPV	81	#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
6d0f6bcf JCPV	82	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE))
	83	/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
	84	#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
0e8d1586	85	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
6d0f6bcf	86	#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
7faddaec NI	87
	88	/* Clock */
	89	#define CONFIG_SYS_CLK_FREQ 66666666
684a501e NI	90	#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
684a501e NI	91	#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
be45c632	92	#define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
7faddaec	93
ba932445 NI	94	/* Ether */
	95	#define CONFIG_SH_ETHER 1
	96	#define CONFIG_SH_ETHER_USE_PORT (1)
	97	#define CONFIG_SH_ETHER_PHY_ADDR (0x01)
c8ceca95 YS	98	#define CONFIG_PHYLIB
	99	#define CONFIG_BITBANGMII
	100	#define CONFIG_BITBANGMII_MULTI
a80a6619	101	#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
ba932445	102
7faddaec	103	#endif /* __SH7763RDP_H */