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ae9996c8 SR |
1 | /* |
2 | * Copyright (C) 2015 Stefan Roese <sr@denx.de> | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | #ifndef __CONFIG_SOCFPGA_SR1500_H__ | |
7 | #define __CONFIG_SOCFPGA_SR1500_H__ | |
8 | ||
9 | #include <asm/arch/base_addr_ac5.h> | |
10 | ||
ae9996c8 SR |
11 | #define CONFIG_FAT_WRITE |
12 | ||
13 | #define CONFIG_HW_WATCHDOG | |
14 | ||
ae9996c8 SR |
15 | /* Memory configurations */ |
16 | #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SR1500 */ | |
17 | ||
18 | /* Booting Linux */ | |
ae9996c8 | 19 | #define CONFIG_BOOTFILE "uImage" |
77cd5368 | 20 | #define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) |
ae9996c8 SR |
21 | #define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" |
22 | #define CONFIG_LOADADDR 0x01000000 | |
23 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR | |
ae9996c8 SR |
24 | |
25 | /* Ethernet on SoC (EMAC) */ | |
26 | #define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII | |
27 | /* The PHY is autodetected, so no MII PHY address is needed here */ | |
28 | #define CONFIG_PHY_MARVELL | |
29 | #define PHY_ANEG_TIMEOUT 8000 | |
30 | ||
ae9996c8 SR |
31 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
32 | "verify=n\0" \ | |
f6060ce4 | 33 | "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ |
ae9996c8 SR |
34 | "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ |
35 | "bootm ${loadaddr} - ${fdt_addr}\0" \ | |
36 | "bootimage=zImage\0" \ | |
37 | "fdt_addr=100\0" \ | |
38 | "fdtimage=socfpga.dtb\0" \ | |
39 | "fsloadcmd=ext2load\0" \ | |
40 | "bootm ${loadaddr} - ${fdt_addr}\0" \ | |
41 | "mmcroot=/dev/mmcblk0p2\0" \ | |
42 | "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ | |
43 | " root=${mmcroot} rw rootwait;" \ | |
44 | "bootz ${loadaddr} - ${fdt_addr}\0" \ | |
45 | "mmcload=mmc rescan;" \ | |
46 | "load mmc 0:1 ${loadaddr} ${bootimage};" \ | |
47 | "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ | |
b3bb1110 | 48 | "qspiload=sf probe && mtdparts default && run ubiload\0" \ |
ae9996c8 | 49 | "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ |
94f53a7d CLS |
50 | " ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\ |
51 | "bootz ${loadaddr} - ${fdt_addr}\0" \ | |
eb45022c CLS |
52 | "ubiload=ubi part UBI && ubifsmount ubi0 && " \ |
53 | "ubifsload ${loadaddr} /boot/${bootimage} && " \ | |
54 | "ubifsload ${fdt_addr} /boot/${fdtimage}\0" | |
ae9996c8 SR |
55 | |
56 | /* Environment */ | |
57 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
58 | ||
59 | /* Enable SPI NOR flash reset, needed for SPI booting */ | |
60 | #define CONFIG_SPI_N25Q256A_RESET | |
61 | ||
62 | /* | |
63 | * Bootcounter | |
64 | */ | |
65 | #define CONFIG_BOOTCOUNT_LIMIT | |
66 | /* last 2 lwords in OCRAM */ | |
67 | #define CONFIG_SYS_BOOTCOUNT_ADDR 0xfffffff8 | |
68 | #define CONFIG_SYS_BOOTCOUNT_BE | |
69 | ||
ae9996c8 | 70 | /* Environment setting for SPI flash */ |
ae9996c8 SR |
71 | #define CONFIG_SYS_REDUNDAND_ENVIRONMENT |
72 | #define CONFIG_ENV_SECT_SIZE (64 * 1024) | |
73 | #define CONFIG_ENV_SIZE (16 * 1024) | |
93d9fc26 | 74 | #define CONFIG_ENV_OFFSET 0x000e0000 |
ae9996c8 SR |
75 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE) |
76 | #define CONFIG_ENV_SPI_BUS 0 | |
77 | #define CONFIG_ENV_SPI_CS 0 | |
78 | #define CONFIG_ENV_SPI_MODE SPI_MODE_3 | |
93d9fc26 SR |
79 | #define CONFIG_ENV_SPI_MAX_HZ 100000000 /* Use max of 100MHz */ |
80 | #define CONFIG_SF_DEFAULT_SPEED 100000000 | |
81 | ||
82 | /* | |
83 | * The QSPI NOR flash layout on SR1500: | |
84 | * | |
85 | * 0000.0000 - 0003.ffff: SPL (4 times) | |
86 | * 0004.0000 - 000d.ffff: U-Boot | |
87 | * 000e.0000 - 000e.ffff: env1 | |
88 | * 000f.0000 - 000f.ffff: env2 | |
89 | */ | |
ae9996c8 | 90 | |
b72041cc MV |
91 | /* The rest of the configuration is shared */ |
92 | #include <configs/socfpga_common.h> | |
93 | ||
ae9996c8 | 94 | #endif /* __CONFIG_SOCFPGA_SR1500_H__ */ |