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7abf0c58 WD |
1 | /* |
2 | * (C) Copyright 2003 Embedded Edge, LLC | |
3 | * Dan Malek <dan@embeddededge.com> | |
4 | * Copied from ADS85xx. | |
5 | * Updates for Silicon Tx GP3 8560 board. | |
6 | * | |
7 | * (C) Copyright 2002,2003 Motorola,Inc. | |
8 | * Xianghua Xiao <X.Xiao@motorola.com> | |
9 | * | |
3765b3e7 | 10 | * SPDX-License-Identifier: GPL-2.0+ |
7abf0c58 WD |
11 | */ |
12 | ||
13 | /* mpc8560ads board configuration file */ | |
14 | /* please refer to doc/README.mpc85xx for more info */ | |
15 | /* make sure you change the MAC address and other network params first, | |
16 | * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file | |
17 | */ | |
18 | ||
19 | #ifndef __CONFIG_H | |
20 | #define __CONFIG_H | |
21 | ||
22 | /* High Level Configuration Options */ | |
23 | #define CONFIG_BOOKE 1 /* BOOKE */ | |
24 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
25 | #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ | |
9c4c5ae3 | 26 | #define CONFIG_CPM2 1 /* has CPM2 */ |
7abf0c58 | 27 | #define CONFIG_STXGP3 1 /* Silicon Tx GPPP board specific*/ |
f060054d | 28 | #define CONFIG_MPC8560 1 |
7abf0c58 | 29 | |
2ae18241 WD |
30 | #define CONFIG_SYS_TEXT_BASE 0xfff80000 |
31 | ||
53677ef1 WD |
32 | #undef CONFIG_PCI /* pci ethernet support */ |
33 | #define CONFIG_TSEC_ENET /* tsec ethernet support*/ | |
7abf0c58 WD |
34 | #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ |
35 | #define CONFIG_ENV_OVERWRITE | |
9aea9530 | 36 | |
572b13af | 37 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ |
7abf0c58 | 38 | |
9aea9530 | 39 | /* sysclk for MPC85xx |
7abf0c58 | 40 | */ |
7abf0c58 WD |
41 | |
42 | #define CONFIG_SYS_CLK_FREQ 33333333 /* most pci cards are 33Mhz */ | |
43 | ||
44 | /* Blinkin' LEDs for Robert :-) | |
45 | */ | |
46 | #define CONFIG_SHOW_ACTIVITY 1 | |
47 | ||
9aea9530 WD |
48 | /* |
49 | * These can be toggled for performance analysis, otherwise use default. | |
50 | */ | |
7abf0c58 | 51 | #define CONFIG_L2_CACHE /* toggle L2 cache */ |
9aea9530 | 52 | #define CONFIG_BTB /* toggle branch predition */ |
7abf0c58 | 53 | |
9aea9530 | 54 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ |
004eca0c | 55 | #define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ |
7abf0c58 | 56 | |
6d0f6bcf JCPV |
57 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
58 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ | |
59 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
7abf0c58 | 60 | |
7abf0c58 WD |
61 | |
62 | /* Localbus SDRAM is an option, not all boards have it. | |
9aea9530 WD |
63 | * This address, however, is used to configure a 256M local bus |
64 | * window that includes the Config latch below. | |
65 | */ | |
6d0f6bcf JCPV |
66 | #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ |
67 | #define CONFIG_SYS_LBC_SDRAM_SIZE 256 /* LBC SDRAM is 64MB */ | |
7abf0c58 | 68 | |
6d0f6bcf JCPV |
69 | #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ |
70 | #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */ | |
7abf0c58 | 71 | |
6d0f6bcf JCPV |
72 | #define CONFIG_SYS_OR0_PRELIM 0xff000ff7 /* 16 MB Flash */ |
73 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
74 | #define CONFIG_SYS_MAX_FLASH_SECT 136 /* sectors per device */ | |
75 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
76 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Timeout for Flash Erase (in ms) */ | |
77 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
7abf0c58 WD |
78 | |
79 | /* The configuration latch is Chip Select 1. | |
9aea9530 | 80 | * It's an 8-bit latch in the lower 8 bits of the word. |
7abf0c58 | 81 | */ |
6d0f6bcf JCPV |
82 | #define CONFIG_SYS_BR1_PRELIM 0xfc001801 /* 32-bit port */ |
83 | #define CONFIG_SYS_OR1_PRELIM 0xffff0ff7 /* 64K is enough */ | |
84 | #define CONFIG_SYS_LBC_LCLDEVS_BASE 0xfc000000 /* Base of localbus devices */ | |
7abf0c58 | 85 | |
14d0a02a | 86 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
7abf0c58 | 87 | |
6d0f6bcf JCPV |
88 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
89 | #define CONFIG_SYS_RAMBOOT | |
7abf0c58 | 90 | #else |
6d0f6bcf | 91 | #undef CONFIG_SYS_RAMBOOT |
7abf0c58 WD |
92 | #endif |
93 | ||
6d0f6bcf JCPV |
94 | #ifdef CONFIG_SYS_RAMBOOT |
95 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */ | |
7abf0c58 | 96 | #endif |
e46fedfe TT |
97 | #define CONFIG_SYS_CCSRBAR 0xfdf00000 |
98 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
7abf0c58 | 99 | |
c360d9b9 KG |
100 | /* DDR Setup */ |
101 | #define CONFIG_FSL_DDR1 | |
102 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ | |
103 | #define CONFIG_DDR_SPD | |
104 | #undef CONFIG_FSL_DDR_INTERACTIVE | |
7abf0c58 | 105 | |
c360d9b9 | 106 | #undef CONFIG_DDR_ECC /* only for ECC DDR module */ |
810c4427 | 107 | #define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */ |
c360d9b9 | 108 | #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ |
7abf0c58 | 109 | |
c360d9b9 KG |
110 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
111 | ||
6d0f6bcf JCPV |
112 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ |
113 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
9aea9530 | 114 | |
c360d9b9 KG |
115 | #define CONFIG_NUM_DDR_CONTROLLERS 1 |
116 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
117 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
118 | ||
119 | /* I2C addresses of SPD EEPROMs */ | |
120 | #define SPD_EEPROM_ADDRESS 0x54 /* CTLR 0 DIMM 0 */ | |
7abf0c58 WD |
121 | |
122 | #undef CONFIG_CLOCKS_IN_MHZ | |
123 | ||
124 | /* local bus definitions */ | |
6d0f6bcf JCPV |
125 | #define CONFIG_SYS_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */ |
126 | #define CONFIG_SYS_OR2_PRELIM 0xfc006901 | |
127 | #define CONFIG_SYS_LBC_LCRR 0x00030004 /* local bus freq */ | |
128 | #define CONFIG_SYS_LBC_LBCR 0x00000000 | |
129 | #define CONFIG_SYS_LBC_LSRT 0x20000000 | |
130 | #define CONFIG_SYS_LBC_MRTPR 0x20000000 | |
131 | #define CONFIG_SYS_LBC_LSDMR_1 0x2861b723 | |
132 | #define CONFIG_SYS_LBC_LSDMR_2 0x0861b723 | |
133 | #define CONFIG_SYS_LBC_LSDMR_3 0x0861b723 | |
134 | #define CONFIG_SYS_LBC_LSDMR_4 0x1861b723 | |
135 | #define CONFIG_SYS_LBC_LSDMR_5 0x4061b723 | |
7abf0c58 | 136 | |
6d0f6bcf JCPV |
137 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
138 | #define CONFIG_SYS_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */ | |
553f0982 | 139 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ |
7abf0c58 | 140 | |
25ddd1fb | 141 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 142 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
7abf0c58 | 143 | |
6d0f6bcf JCPV |
144 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
145 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ | |
7abf0c58 WD |
146 | |
147 | /* Serial Port */ | |
53677ef1 WD |
148 | #define CONFIG_CONS_ON_SCC /* define if console on SCC */ |
149 | #undef CONFIG_CONS_NONE /* define if console on something else */ | |
150 | #define CONFIG_CONS_INDEX 2 /* which serial channel for console */ | |
7abf0c58 | 151 | |
53677ef1 | 152 | #define CONFIG_BAUDRATE 38400 |
7abf0c58 | 153 | |
6d0f6bcf | 154 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
7abf0c58 WD |
155 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
156 | ||
157 | /* Use the HUSH parser */ | |
6d0f6bcf JCPV |
158 | #define CONFIG_SYS_HUSH_PARSER |
159 | #ifdef CONFIG_SYS_HUSH_PARSER | |
7abf0c58 WD |
160 | #endif |
161 | ||
20476726 JL |
162 | /* |
163 | * I2C | |
164 | */ | |
00f792e0 HS |
165 | #define CONFIG_SYS_I2C |
166 | #define CONFIG_SYS_I2C_FSL | |
167 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
168 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
169 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
170 | ||
7abf0c58 | 171 | #if 0 |
6d0f6bcf | 172 | #define CONFIG_SYS_I2C_NOPROBES {0x00} /* Don't probe these addrs */ |
7abf0c58 WD |
173 | #else |
174 | /* I did the 'if 0' so we could keep the syntax above if ever needed. */ | |
6d0f6bcf | 175 | #undef CONFIG_SYS_I2C_NOPROBES |
7abf0c58 WD |
176 | #endif |
177 | ||
9aea9530 WD |
178 | /* RapdIO Map configuration, mapped 1:1. |
179 | */ | |
6d0f6bcf JCPV |
180 | #define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 |
181 | #define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE | |
182 | #define CONFIG_SYS_RIO_MEM_SIZE 0x200000000 /* 512 M */ | |
9aea9530 WD |
183 | |
184 | /* Standard 8560 PCI addressing, mapped 1:1. | |
185 | */ | |
6d0f6bcf JCPV |
186 | #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 |
187 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE | |
188 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ | |
189 | #define CONFIG_SYS_PCI1_IO_BASE 0xe2000000 | |
190 | #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE | |
191 | #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16 M */ | |
7abf0c58 | 192 | |
53677ef1 | 193 | #if defined(CONFIG_PCI) /* PCI Ethernet card */ |
9aea9530 | 194 | |
53677ef1 | 195 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
9aea9530 WD |
196 | |
197 | #undef CONFIG_EEPRO100 | |
198 | #undef CONFIG_TULIP | |
199 | ||
200 | #if !defined(CONFIG_PCI_PNP) | |
53677ef1 | 201 | #define PCI_ENET0_IOADDR 0xe0000000 |
7abf0c58 | 202 | #define PCI_ENET0_MEMADDR 0xe0000000 |
53677ef1 | 203 | #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ |
7abf0c58 | 204 | #endif |
9aea9530 WD |
205 | |
206 | #undef CONFIG_PCI_SCAN_SHOW | |
6d0f6bcf | 207 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ |
9aea9530 WD |
208 | |
209 | #endif /* CONFIG_PCI */ | |
210 | ||
211 | #if defined(CONFIG_TSEC_ENET) | |
212 | ||
7abf0c58 | 213 | #define CONFIG_MII 1 /* MII PHY management */ |
9aea9530 | 214 | |
255a3577 KP |
215 | #define CONFIG_TSEC1 1 |
216 | #define CONFIG_TSEC1_NAME "TSEC0" | |
217 | #define CONFIG_TSEC2 1 | |
218 | #define CONFIG_TSEC2_NAME "TSEC1" | |
9aea9530 WD |
219 | |
220 | #define TSEC1_PHY_ADDR 2 | |
221 | #define TSEC2_PHY_ADDR 4 | |
222 | #define TSEC1_PHYIDX 0 | |
223 | #define TSEC2_PHYIDX 0 | |
3a79013e AF |
224 | #define TSEC1_FLAGS TSEC_GIGABIT |
225 | #define TSEC2_FLAGS TSEC_GIGABIT | |
d9b94f28 | 226 | #define CONFIG_ETHPRIME "TSEC0" |
9aea9530 | 227 | |
7abf0c58 | 228 | #elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ |
9aea9530 | 229 | |
7abf0c58 WD |
230 | #define CONFIG_ETHER_ON_FCC2 /* define if ether on FCC */ |
231 | #undef CONFIG_ETHER_NONE /* define if ether on something else */ | |
232 | #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ | |
9aea9530 WD |
233 | |
234 | #if (CONFIG_ETHER_INDEX == 2) | |
7abf0c58 WD |
235 | /* |
236 | * - Rx-CLK is CLK13 | |
237 | * - Tx-CLK is CLK14 | |
238 | * - Select bus for bd/buffers | |
239 | * - Full duplex | |
240 | */ | |
d4590da4 MF |
241 | #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) |
242 | #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) | |
6d0f6bcf | 243 | #define CONFIG_SYS_CPMFCR_RAMTYPE 0 |
7abf0c58 | 244 | #if 0 |
6d0f6bcf | 245 | #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE) |
7abf0c58 | 246 | #else |
6d0f6bcf | 247 | #define CONFIG_SYS_FCC_PSMR 0 |
7abf0c58 WD |
248 | #endif |
249 | #define FETH2_RST 0x01 | |
9aea9530 | 250 | #elif (CONFIG_ETHER_INDEX == 3) |
7abf0c58 WD |
251 | /* need more definitions here for FE3 */ |
252 | #define FETH3_RST 0x80 | |
53677ef1 | 253 | #endif /* CONFIG_ETHER_INDEX */ |
9aea9530 WD |
254 | |
255 | /* MDIO is done through the TSEC0 control. | |
256 | */ | |
7abf0c58 WD |
257 | #define CONFIG_MII /* MII PHY management */ |
258 | #undef CONFIG_BITBANGMII /* bit-bang MII PHY management */ | |
7abf0c58 | 259 | |
7abf0c58 WD |
260 | #endif |
261 | ||
262 | /* Environment */ | |
263 | /* We use the top boot sector flash, so we have some 16K sectors for env | |
7abf0c58 | 264 | */ |
6d0f6bcf | 265 | #ifndef CONFIG_SYS_RAMBOOT |
5a1aceb0 | 266 | #define CONFIG_ENV_IS_IN_FLASH 1 |
6d0f6bcf | 267 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x60000) |
0e8d1586 JCPV |
268 | #define CONFIG_ENV_SECT_SIZE 0x4000 /* 16K (one top sector) for env */ |
269 | #define CONFIG_ENV_SIZE 0x2000 | |
7abf0c58 | 270 | #else |
6d0f6bcf | 271 | #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ |
93f6d725 | 272 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
6d0f6bcf | 273 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
0e8d1586 | 274 | #define CONFIG_ENV_SIZE 0x2000 |
7abf0c58 WD |
275 | #endif |
276 | ||
277 | #define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,38400" | |
9aea9530 | 278 | #define CONFIG_BOOTCOMMAND "bootm 0xff000000 0xff100000" |
7abf0c58 WD |
279 | #define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */ |
280 | ||
281 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 282 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
7abf0c58 | 283 | |
079a136c JL |
284 | /* |
285 | * BOOTP options | |
286 | */ | |
287 | #define CONFIG_BOOTP_BOOTFILESIZE | |
288 | #define CONFIG_BOOTP_BOOTPATH | |
289 | #define CONFIG_BOOTP_GATEWAY | |
290 | #define CONFIG_BOOTP_HOSTNAME | |
291 | ||
292 | ||
2835e518 JL |
293 | /* |
294 | * Command line configuration. | |
295 | */ | |
296 | #include <config_cmd_default.h> | |
297 | ||
298 | #define CONFIG_CMD_PING | |
299 | #define CONFIG_CMD_I2C | |
199e262e | 300 | #define CONFIG_CMD_REGINFO |
2835e518 | 301 | |
6d0f6bcf | 302 | #if defined(CONFIG_SYS_RAMBOOT) |
bdab39d3 | 303 | #undef CONFIG_CMD_SAVEENV |
2835e518 | 304 | #undef CONFIG_CMD_LOADS |
7abf0c58 | 305 | #else |
2835e518 JL |
306 | #define CONFIG_CMD_ELF |
307 | #endif | |
308 | ||
309 | #if defined(CONFIG_PCI) | |
310 | #define CONFIG_CMD_PCI | |
7abf0c58 | 311 | #endif |
2835e518 JL |
312 | |
313 | #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) | |
314 | #define CONFIG_CMD_MII | |
315 | #endif | |
316 | ||
7abf0c58 WD |
317 | |
318 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
319 | ||
320 | /* | |
321 | * Miscellaneous configurable options | |
322 | */ | |
6d0f6bcf JCPV |
323 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
324 | #define CONFIG_SYS_PROMPT "GPPP=> " /* Monitor Command Prompt */ | |
2835e518 | 325 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 326 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
7abf0c58 | 327 | #else |
6d0f6bcf | 328 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
7abf0c58 | 329 | #endif |
6d0f6bcf JCPV |
330 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
331 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
332 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
333 | #define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */ | |
7abf0c58 WD |
334 | |
335 | /* | |
336 | * For booting Linux, the board info and command line data | |
337 | * have to be in the first 8 MB of memory, since this is | |
338 | * the maximum mapped by the Linux kernel during initialization. | |
339 | */ | |
6d0f6bcf | 340 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
7abf0c58 | 341 | |
2835e518 | 342 | #if defined(CONFIG_CMD_KGDB) |
7abf0c58 WD |
343 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
344 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
345 | #endif | |
346 | ||
347 | /*Note: change below for your network setting!!! */ | |
348 | #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) | |
10327dc5 | 349 | #define CONFIG_HAS_ETH0 |
53677ef1 | 350 | #define CONFIG_ETHADDR 00:e0:0c:07:9b:8a |
e2ffd59b | 351 | #define CONFIG_HAS_ETH1 |
53677ef1 | 352 | #define CONFIG_ETH1ADDR 00:e0:0c:07:9b:8b |
e2ffd59b | 353 | #define CONFIG_HAS_ETH2 |
53677ef1 | 354 | #define CONFIG_ETH2ADDR 00:e0:0c:07:9b:8c |
7abf0c58 WD |
355 | #endif |
356 | ||
53677ef1 WD |
357 | #define CONFIG_SERVERIP 192.168.85.1 |
358 | #define CONFIG_IPADDR 192.168.85.60 | |
7abf0c58 WD |
359 | #define CONFIG_GATEWAYIP 192.168.85.1 |
360 | #define CONFIG_NETMASK 255.255.255.0 | |
53677ef1 | 361 | #define CONFIG_HOSTNAME STX_GP3 |
8b3637c6 | 362 | #define CONFIG_ROOTPATH "/gppproot" |
b3f44c21 | 363 | #define CONFIG_BOOTFILE "uImage" |
9aea9530 | 364 | #define CONFIG_LOADADDR 0x1000000 |
7abf0c58 WD |
365 | |
366 | #endif /* __CONFIG_H */ |