[people/ms/u-boot.git] / include / configs / sunxi-common.h

/*
 * (C) Copyright 2012-2012 Henrik Nordstrom <henrik@henriknordstrom.net>
 *
 * (C) Copyright 2007-2011
 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
 * Tom Cubie <tangliang@allwinnertech.com>
 *
 * Configuration settings for the Allwinner sunxi series of boards.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _SUNXI_COMMON_CONFIG_H
#define _SUNXI_COMMON_CONFIG_H

#include <asm/arch/cpu.h>
#include <linux/stringify.h>

#ifdef CONFIG_OLD_SUNXI_KERNEL_COMPAT
/*
 * The U-Boot workarounds bugs in the outdated buggy sunxi-3.4 kernels at the
 * expense of restricting some features, so the regular machine id values can
 * be used.
 */
# define CONFIG_MACH_TYPE_COMPAT_REV	0
#else
/*
 * A compatibility guard to prevent loading outdated buggy sunxi-3.4 kernels.
 * Only sunxi-3.4 kernels with appropriate fixes applied are able to pass
 * beyond the machine id check.
 */
# define CONFIG_MACH_TYPE_COMPAT_REV	1
#endif

/*
 * High Level Configuration Options
 */
#define CONFIG_SUNXI		/* sunxi family */
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_THUMB_BUILD	/* Thumbs mode to save space in SPL */
#endif

/* Serial & console */
#define CONFIG_SYS_NS16550_SERIAL
/* ns16550 reg in the low bits of cpu reg */
#define CONFIG_SYS_NS16550_CLK		24000000
#ifndef CONFIG_DM_SERIAL
# define CONFIG_SYS_NS16550_REG_SIZE	-4
# define CONFIG_SYS_NS16550_COM1		SUNXI_UART0_BASE
# define CONFIG_SYS_NS16550_COM2		SUNXI_UART1_BASE
# define CONFIG_SYS_NS16550_COM3		SUNXI_UART2_BASE
# define CONFIG_SYS_NS16550_COM4		SUNXI_UART3_BASE
# define CONFIG_SYS_NS16550_COM5		SUNXI_R_UART_BASE
#endif

/* CPU */
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_TIMER_CLK_FREQ		24000000

/*
 * The DRAM Base differs between some models. We cannot use macros for the
 * CONFIG_FOO defines which contain the DRAM base address since they end
 * up unexpanded in include/autoconf.mk .
 *
 * So we have to have this #ifdef #else #endif block for these.
 */
#ifdef CONFIG_MACH_SUN9I
#define SDRAM_OFFSET(x) 0x2##x
#define CONFIG_SYS_SDRAM_BASE		0x20000000
#define CONFIG_SYS_LOAD_ADDR		0x22000000 /* default load address */
#define CONFIG_SYS_TEXT_BASE		0x2a000000
#define CONFIG_PRE_CON_BUF_ADDR		0x2f000000
/* Note SPL_STACK_R_ADDR is set through Kconfig, we include it here 
 * since it needs to fit in with the other values. By also #defining it
 * we get warnings if the Kconfig value mismatches. */
#define CONFIG_SPL_STACK_R_ADDR		0x2fe00000
#define CONFIG_SPL_BSS_START_ADDR	0x2ff80000
#else
#define SDRAM_OFFSET(x) 0x4##x
#define CONFIG_SYS_SDRAM_BASE		0x40000000
#define CONFIG_SYS_LOAD_ADDR		0x42000000 /* default load address */
#define CONFIG_SYS_TEXT_BASE		0x4a000000
#define CONFIG_PRE_CON_BUF_ADDR		0x4f000000
/* Note SPL_STACK_R_ADDR is set through Kconfig, we include it here 
 * since it needs to fit in with the other values. By also #defining it
 * we get warnings if the Kconfig value mismatches. */
#define CONFIG_SPL_STACK_R_ADDR		0x4fe00000
#define CONFIG_SPL_BSS_START_ADDR	0x4ff80000
#endif

#define CONFIG_SPL_BSS_MAX_SIZE		0x00080000 /* 512 KiB */

#if defined(CONFIG_MACH_SUN9I) || defined(CONFIG_MACH_SUN50I)
/*
 * The A80's A1 sram starts at 0x00010000 rather then at 0x00000000 and is
 * slightly bigger. Note that it is possible to map the first 32 KiB of the
 * A1 at 0x00000000 like with older SoCs by writing 0x16aa0001 to the
 * undocumented 0x008000e0 SYS_CTRL register. Where the 16aa is a key and
 * the 1 actually activates the mapping of the first 32 KiB to 0x00000000.
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x10000
#define CONFIG_SYS_INIT_RAM_SIZE	0x08000	/* FIXME: 40 KiB ? */
#else
#define CONFIG_SYS_INIT_RAM_ADDR	0x0
#define CONFIG_SYS_INIT_RAM_SIZE	0x8000	/* 32 KiB */
#endif

#define CONFIG_SYS_INIT_SP_OFFSET \
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

#define CONFIG_NR_DRAM_BANKS		1
#define PHYS_SDRAM_0			CONFIG_SYS_SDRAM_BASE
#define PHYS_SDRAM_0_SIZE		0x80000000 /* 2 GiB */

#ifdef CONFIG_AHCI
#define CONFIG_LIBATA
#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SUNXI_AHCI
#define CONFIG_SYS_64BIT_LBA
#define CONFIG_SYS_SCSI_MAX_SCSI_ID	1
#define CONFIG_SYS_SCSI_MAX_LUN		1
#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
					 CONFIG_SYS_SCSI_MAX_LUN)
#define CONFIG_SCSI
#endif

#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_CMDLINE_TAG
#define CONFIG_INITRD_TAG
#define CONFIG_SERIAL_TAG

#ifdef CONFIG_NAND_SUNXI
#define CONFIG_SYS_NAND_MAX_ECCPOS 1664
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_SYS_MAX_NAND_DEVICE 8
#endif

#ifdef CONFIG_SPL_SPI_SUNXI
#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x8000
#endif

/* mmc config */
#ifdef CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_MMC_SUNXI
#define CONFIG_MMC_SUNXI_SLOT		0
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV		0	/* first detected MMC controller */
#endif

/* 64MB of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (64 << 20))

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE	1024	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16	/* max number of command args */

/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE

/* standalone support */
#define CONFIG_STANDALONE_LOAD_ADDR	CONFIG_SYS_LOAD_ADDR

/* baudrate */
#define CONFIG_BAUDRATE			115200

/* The stack sizes are set up in start.S using the settings below */
#define CONFIG_STACKSIZE		(256 << 10)	/* 256 KiB */

/* FLASH and environment organization */

#define CONFIG_SYS_NO_FLASH

#define CONFIG_SYS_MONITOR_LEN		(768 << 10)	/* 768 KiB */
#define CONFIG_DISPLAY_BOARDINFO

#define CONFIG_ENV_OFFSET		(544 << 10) /* (8 + 24 + 512) KiB */
#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */

#define CONFIG_FAT_WRITE	/* enable write access */

#define CONFIG_SPL_FRAMEWORK

#define CONFIG_SPL_BOARD_LOAD_IMAGE

#if defined(CONFIG_MACH_SUN9I)
#define CONFIG_SPL_TEXT_BASE		0x10040		/* sram start+header */
#define CONFIG_SPL_MAX_SIZE		0x5fc0		/* ? KiB on sun9i */
#elif defined(CONFIG_MACH_SUN50I)
#define CONFIG_SPL_TEXT_BASE		0x10040		/* sram start+header */
#define CONFIG_SPL_MAX_SIZE		0x7fc0		/* 32 KiB on sun50i */
#else
#define CONFIG_SPL_TEXT_BASE		0x40		/* sram start+header */
#define CONFIG_SPL_MAX_SIZE		0x5fc0		/* 24KB on sun4i/sun7i */
#endif

#ifndef CONFIG_ARM64
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
#endif

#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	80	/* 40KiB */
#define CONFIG_SPL_PAD_TO		32768		/* decimal for 'dd' */

#if defined(CONFIG_MACH_SUN9I) || defined(CONFIG_MACH_SUN50I)
/* FIXME: 40 KiB instead of 32 KiB ? */
#define LOW_LEVEL_SRAM_STACK		0x00018000
#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
#else
/* end of 32 KiB in sram */
#define LOW_LEVEL_SRAM_STACK		0x00008000 /* End of sram */
#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
#endif

/* I2C */
#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
    defined CONFIG_SY8106A_POWER
#endif

#if defined CONFIG_I2C0_ENABLE || defined CONFIG_I2C1_ENABLE || \
    defined CONFIG_I2C2_ENABLE || defined CONFIG_I2C3_ENABLE || \
    defined CONFIG_I2C4_ENABLE || defined CONFIG_R_I2C_ENABLE
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MVTWSI
#define CONFIG_SYS_I2C_SPEED		400000
#define CONFIG_SYS_I2C_SLAVE		0x7f
#endif

#if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
#define CONFIG_SYS_I2C_SOFT
#define CONFIG_SYS_I2C_SOFT_SPEED	50000
#define CONFIG_SYS_I2C_SOFT_SLAVE	0x00
/* We use pin names in Kconfig and sunxi_name_to_gpio() */
#define CONFIG_SOFT_I2C_GPIO_SDA	soft_i2c_gpio_sda
#define CONFIG_SOFT_I2C_GPIO_SCL	soft_i2c_gpio_scl
#ifndef __ASSEMBLY__
extern int soft_i2c_gpio_sda;
extern int soft_i2c_gpio_scl;
#endif
#define CONFIG_VIDEO_LCD_I2C_BUS	0 /* The lcd panel soft i2c is bus 0 */
#define CONFIG_SYS_SPD_BUS_NUM		1 /* And the axp209 i2c bus is bus 1 */
#else
#define CONFIG_SYS_SPD_BUS_NUM		0 /* The axp209 i2c bus is bus 0 */
#define CONFIG_VIDEO_LCD_I2C_BUS	-1 /* NA, but necessary to compile */
#endif

/* PMU */
#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
    defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER || \
    defined CONFIG_SY8106A_POWER
#endif

#ifndef CONFIG_CONS_INDEX
#define CONFIG_CONS_INDEX              1       /* UART0 */
#endif

#ifdef CONFIG_REQUIRE_SERIAL_CONSOLE
#if CONFIG_CONS_INDEX == 1
#ifdef CONFIG_MACH_SUN9I
#define OF_STDOUT_PATH		"/soc/serial@07000000:115200"
#else
#define OF_STDOUT_PATH		"/soc@01c00000/serial@01c28000:115200"
#endif
#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
#define OF_STDOUT_PATH		"/soc@01c00000/serial@01c28400:115200"
#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
#define OF_STDOUT_PATH		"/soc@01c00000/serial@01c28800:115200"
#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
#define OF_STDOUT_PATH		"/soc@01c00000/serial@01f02800:115200"
#else
#error Unsupported console port nr. Please fix stdout-path in sunxi-common.h.
#endif
#endif /* ifdef CONFIG_REQUIRE_SERIAL_CONSOLE */

/* GPIO */
#define CONFIG_SUNXI_GPIO

#ifdef CONFIG_VIDEO
/*
 * The amount of RAM to keep free at the top of RAM when relocating u-boot,
 * to use as framebuffer. This must be a multiple of 4096.
 */
#define CONFIG_SUNXI_MAX_FB_SIZE (16 << 20)

/* Do we want to initialize a simple FB? */
#define CONFIG_VIDEO_DT_SIMPLEFB

#define CONFIG_VIDEO_SUNXI

#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_STD_TIMINGS
#define CONFIG_I2C_EDID
#define VIDEO_LINE_LEN (pGD->plnSizeX)

/* allow both serial and cfb console. */
#define CONFIG_CONSOLE_MUX
/* stop x86 thinking in cfbconsole from trying to init a pc keyboard */
#define CONFIG_VGA_AS_SINGLE_DEVICE

#endif /* CONFIG_VIDEO */

/* Ethernet support */
#ifdef CONFIG_SUNXI_EMAC
#define CONFIG_PHY_ADDR		1
#define CONFIG_MII			/* MII PHY management		*/
#define CONFIG_PHYLIB
#endif

#ifdef CONFIG_SUNXI_GMAC
#define CONFIG_PHY_GIGE			/* GMAC can use gigabit PHY	*/
#define CONFIG_PHY_ADDR		1
#define CONFIG_MII			/* MII PHY management		*/
#define CONFIG_PHY_REALTEK
#endif

#ifdef CONFIG_USB_EHCI_HCD
#define CONFIG_USB_OHCI_NEW
#define CONFIG_USB_OHCI_SUNXI
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
#endif

#ifdef CONFIG_USB_MUSB_SUNXI
#define CONFIG_USB_MUSB_PIO_ONLY
#endif

#ifdef CONFIG_USB_MUSB_GADGET
#define CONFIG_USB_FUNCTION_DFU
#define CONFIG_USB_FUNCTION_FASTBOOT
#define CONFIG_USB_FUNCTION_MASS_STORAGE
#endif

#ifdef CONFIG_USB_FUNCTION_DFU
#define CONFIG_DFU_RAM
#endif

#ifdef CONFIG_USB_FUNCTION_FASTBOOT
#define CONFIG_CMD_FASTBOOT
#define CONFIG_FASTBOOT_BUF_ADDR	CONFIG_SYS_LOAD_ADDR
#define CONFIG_FASTBOOT_BUF_SIZE	0x2000000
#define CONFIG_ANDROID_BOOT_IMAGE

#define CONFIG_FASTBOOT_FLASH

#ifdef CONFIG_MMC
#define CONFIG_FASTBOOT_FLASH_MMC_DEV	0
#define CONFIG_EFI_PARTITION
#endif
#endif

#ifdef CONFIG_USB_FUNCTION_MASS_STORAGE
#endif

#ifdef CONFIG_USB_KEYBOARD
#define CONFIG_CONSOLE_MUX
#define CONFIG_PREBOOT
#define CONFIG_SYS_STDIO_DEREGISTER
#define CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE
#endif

#if !defined CONFIG_ENV_IS_IN_MMC && \
    !defined CONFIG_ENV_IS_IN_NAND && \
    !defined CONFIG_ENV_IS_IN_FAT && \
    !defined CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_IS_NOWHERE
#endif

#define CONFIG_MISC_INIT_R
#define CONFIG_SYS_CONSOLE_IS_IN_ENV

#ifndef CONFIG_SPL_BUILD
#include <config_distro_defaults.h>

/* Enable pre-console buffer to get complete log on the VGA console */
#define CONFIG_PRE_CONSOLE_BUFFER
#define CONFIG_PRE_CON_BUF_SZ		4096 /* Aprox 2 80*25 screens */

#ifdef CONFIG_ARM64
/*
 * Boards seem to come with at least 512MB of DRAM.
 * The kernel should go at 512K, which is the default text offset (that will
 * be adjusted at runtime if needed).
 * There is no compression for arm64 kernels (yet), so leave some space
 * for really big kernels, say 256MB for now.
 * Scripts, PXE and DTBs should go afterwards, leaving the rest for the initrd.
 * Align the initrd to a 2MB page.
 */
#define KERNEL_ADDR_R	__stringify(SDRAM_OFFSET(0080000))
#define FDT_ADDR_R	__stringify(SDRAM_OFFSET(FA00000))
#define SCRIPT_ADDR_R	__stringify(SDRAM_OFFSET(FC00000))
#define PXEFILE_ADDR_R	__stringify(SDRAM_OFFSET(FD00000))
#define RAMDISK_ADDR_R	__stringify(SDRAM_OFFSET(FE00000))

#else
/*
 * 160M RAM (256M minimum minus 64MB heap + 32MB for u-boot, stack, fb, etc.
 * 32M uncompressed kernel, 16M compressed kernel, 1M fdt,
 * 1M script, 1M pxe and the ramdisk at the end.
 */

#define KERNEL_ADDR_R  __stringify(SDRAM_OFFSET(2000000))
#define FDT_ADDR_R     __stringify(SDRAM_OFFSET(3000000))
#define SCRIPT_ADDR_R  __stringify(SDRAM_OFFSET(3100000))
#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(3200000))
#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(3300000))
#endif

#define MEM_LAYOUT_ENV_SETTINGS \
	"bootm_size=0xa000000\0" \
	"kernel_addr_r=" KERNEL_ADDR_R "\0" \
	"fdt_addr_r=" FDT_ADDR_R "\0" \
	"scriptaddr=" SCRIPT_ADDR_R "\0" \
	"pxefile_addr_r=" PXEFILE_ADDR_R "\0" \
	"ramdisk_addr_r=" RAMDISK_ADDR_R "\0"

#define DFU_ALT_INFO_RAM \
	"dfu_alt_info_ram=" \
	"kernel ram " KERNEL_ADDR_R " 0x1000000;" \
	"fdt ram " FDT_ADDR_R " 0x100000;" \
	"ramdisk ram " RAMDISK_ADDR_R " 0x4000000\0"

#ifdef CONFIG_MMC
#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
#if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
#define BOOT_TARGET_DEVICES_MMC_EXTRA(func) func(MMC, mmc, 1)
#else
#define BOOT_TARGET_DEVICES_MMC_EXTRA(func)
#endif
#else
#define BOOT_TARGET_DEVICES_MMC(func)
#define BOOT_TARGET_DEVICES_MMC_EXTRA(func)
#endif

#ifdef CONFIG_AHCI
#define BOOT_TARGET_DEVICES_SCSI(func) func(SCSI, scsi, 0)
#else
#define BOOT_TARGET_DEVICES_SCSI(func)
#endif

#ifdef CONFIG_USB_STORAGE
#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0)
#else
#define BOOT_TARGET_DEVICES_USB(func)
#endif

/* FEL boot support, auto-execute boot.scr if a script address was provided */
#define BOOTENV_DEV_FEL(devtypeu, devtypel, instance) \
	"bootcmd_fel=" \
		"if test -n ${fel_booted} && test -n ${fel_scriptaddr}; then " \
			"echo '(FEL boot)'; " \
			"source ${fel_scriptaddr}; " \
		"fi\0"
#define BOOTENV_DEV_NAME_FEL(devtypeu, devtypel, instance) \
	"fel "

#define BOOT_TARGET_DEVICES(func) \
	func(FEL, fel, na) \
	BOOT_TARGET_DEVICES_MMC(func) \
	BOOT_TARGET_DEVICES_MMC_EXTRA(func) \
	BOOT_TARGET_DEVICES_SCSI(func) \
	BOOT_TARGET_DEVICES_USB(func) \
	func(PXE, pxe, na) \
	func(DHCP, dhcp, na)

#ifdef CONFIG_OLD_SUNXI_KERNEL_COMPAT
#define BOOTCMD_SUNXI_COMPAT \
	"bootcmd_sunxi_compat=" \
		"setenv root /dev/mmcblk0p3 rootwait; " \
		"if ext2load mmc 0 0x44000000 uEnv.txt; then " \
			"echo Loaded environment from uEnv.txt; " \
			"env import -t 0x44000000 ${filesize}; " \
		"fi; " \
		"setenv bootargs console=${console} root=${root} ${extraargs}; " \
		"ext2load mmc 0 0x43000000 script.bin && " \
		"ext2load mmc 0 0x48000000 uImage && " \
		"bootm 0x48000000\0"
#else
#define BOOTCMD_SUNXI_COMPAT
#endif

#include <config_distro_bootcmd.h>

#ifdef CONFIG_USB_KEYBOARD
#define CONSOLE_STDIN_SETTINGS \
	"preboot=usb start\0" \
	"stdin=serial,usbkbd\0"
#else
#define CONSOLE_STDIN_SETTINGS \
	"stdin=serial\0"
#endif

#ifdef CONFIG_VIDEO
#define CONSOLE_STDOUT_SETTINGS \
	"stdout=serial,vga\0" \
	"stderr=serial,vga\0"
#else
#define CONSOLE_STDOUT_SETTINGS \
	"stdout=serial\0" \
	"stderr=serial\0"
#endif

#define CONSOLE_ENV_SETTINGS \
	CONSOLE_STDIN_SETTINGS \
	CONSOLE_STDOUT_SETTINGS

#define CONFIG_EXTRA_ENV_SETTINGS \
	CONSOLE_ENV_SETTINGS \
	MEM_LAYOUT_ENV_SETTINGS \
	DFU_ALT_INFO_RAM \
	"fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
	"console=ttyS0,115200\0" \
	BOOTCMD_SUNXI_COMPAT \
	BOOTENV

#else /* ifndef CONFIG_SPL_BUILD */
#define CONFIG_EXTRA_ENV_SETTINGS
#endif

#endif /* _SUNXI_COMMON_CONFIG_H */
Commit	Line	Data
cba69eee IC	1	/*
	2	* (C) Copyright 2012-2012 Henrik Nordstrom <henrik@henriknordstrom.net>
	3	*
	4	* (C) Copyright 2007-2011
	5	* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
	6	* Tom Cubie <tangliang@allwinnertech.com>
	7	*
	8	* Configuration settings for the Allwinner sunxi series of boards.
	9	*
	10	* SPDX-License-Identifier: GPL-2.0+
	11	*/
	12
	13	#ifndef _SUNXI_COMMON_CONFIG_H
	14	#define _SUNXI_COMMON_CONFIG_H
	15
daf6d399	16	#include <asm/arch/cpu.h>
e049fe28 HG	17	#include <linux/stringify.h>
e049fe28 HG	18
77ef1369 SS	19	#ifdef CONFIG_OLD_SUNXI_KERNEL_COMPAT
	20	/*
	21	* The U-Boot workarounds bugs in the outdated buggy sunxi-3.4 kernels at the
	22	* expense of restricting some features, so the regular machine id values can
	23	* be used.
	24	*/
	25	# define CONFIG_MACH_TYPE_COMPAT_REV 0
	26	#else
	27	/*
	28	* A compatibility guard to prevent loading outdated buggy sunxi-3.4 kernels.
	29	* Only sunxi-3.4 kernels with appropriate fixes applied are able to pass
	30	* beyond the machine id check.
	31	*/
	32	# define CONFIG_MACH_TYPE_COMPAT_REV 1
	33	#endif
	34
cba69eee IC	35	/*
	36	* High Level Configuration Options
	37	*/
	38	#define CONFIG_SUNXI /* sunxi family */
50827a59	39	#ifdef CONFIG_SPL_BUILD
50827a59 IC	40	#define CONFIG_SYS_THUMB_BUILD /* Thumbs mode to save space in SPL */
50827a59 IC	41	#endif
cba69eee	42
cba69eee	43	/* Serial & console */
cba69eee IC	44	#define CONFIG_SYS_NS16550_SERIAL
cba69eee IC	45	/* ns16550 reg in the low bits of cpu reg */
cba69eee	46	#define CONFIG_SYS_NS16550_CLK 24000000
4fb60552	47	#ifndef CONFIG_DM_SERIAL
1a81cf83 SG	48	# define CONFIG_SYS_NS16550_REG_SIZE -4
	49	# define CONFIG_SYS_NS16550_COM1 SUNXI_UART0_BASE
	50	# define CONFIG_SYS_NS16550_COM2 SUNXI_UART1_BASE
	51	# define CONFIG_SYS_NS16550_COM3 SUNXI_UART2_BASE
	52	# define CONFIG_SYS_NS16550_COM4 SUNXI_UART3_BASE
	53	# define CONFIG_SYS_NS16550_COM5 SUNXI_R_UART_BASE
	54	#endif
cba69eee	55
8a65f69c	56	/* CPU */
daf6d399	57	#define CONFIG_DISPLAY_CPUINFO
d96ebc46	58	#define CONFIG_TIMER_CLK_FREQ 24000000
8a65f69c	59
e049fe28 HG	60	/*
	61	* The DRAM Base differs between some models. We cannot use macros for the
	62	* CONFIG_FOO defines which contain the DRAM base address since they end
	63	* up unexpanded in include/autoconf.mk .
	64	*
	65	* So we have to have this #ifdef #else #endif block for these.
	66	*/
	67	#ifdef CONFIG_MACH_SUN9I
	68	#define SDRAM_OFFSET(x) 0x2##x
	69	#define CONFIG_SYS_SDRAM_BASE 0x20000000
	70	#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* default load address */
	71	#define CONFIG_SYS_TEXT_BASE 0x2a000000
	72	#define CONFIG_PRE_CON_BUF_ADDR 0x2f000000
ff42d107 HG	73	/* Note SPL_STACK_R_ADDR is set through Kconfig, we include it here
	74	* since it needs to fit in with the other values. By also #defining it
	75	* we get warnings if the Kconfig value mismatches. */
	76	#define CONFIG_SPL_STACK_R_ADDR 0x2fe00000
e049fe28 HG	77	#define CONFIG_SPL_BSS_START_ADDR 0x2ff80000
	78	#else
	79	#define SDRAM_OFFSET(x) 0x4##x
cba69eee	80	#define CONFIG_SYS_SDRAM_BASE 0x40000000
e049fe28 HG	81	#define CONFIG_SYS_LOAD_ADDR 0x42000000 /* default load address */
	82	#define CONFIG_SYS_TEXT_BASE 0x4a000000
	83	#define CONFIG_PRE_CON_BUF_ADDR 0x4f000000
ff42d107 HG	84	/* Note SPL_STACK_R_ADDR is set through Kconfig, we include it here
	85	* since it needs to fit in with the other values. By also #defining it
	86	* we get warnings if the Kconfig value mismatches. */
	87	#define CONFIG_SPL_STACK_R_ADDR 0x4fe00000
e049fe28 HG	88	#define CONFIG_SPL_BSS_START_ADDR 0x4ff80000
	89	#endif
	90
	91	#define CONFIG_SPL_BSS_MAX_SIZE 0x00080000 /* 512 KiB */
e049fe28	92
d96ebc46	93	#if defined(CONFIG_MACH_SUN9I) \|\| defined(CONFIG_MACH_SUN50I)
77fe9887 HG	94	/*
	95	* The A80's A1 sram starts at 0x00010000 rather then at 0x00000000 and is
	96	* slightly bigger. Note that it is possible to map the first 32 KiB of the
	97	* A1 at 0x00000000 like with older SoCs by writing 0x16aa0001 to the
	98	* undocumented 0x008000e0 SYS_CTRL register. Where the 16aa is a key and
	99	* the 1 actually activates the mapping of the first 32 KiB to 0x00000000.
	100	*/
	101	#define CONFIG_SYS_INIT_RAM_ADDR 0x10000
eb504fa1	102	#define CONFIG_SYS_INIT_RAM_SIZE 0x08000 /* FIXME: 40 KiB ? */
77fe9887	103	#else
cba69eee IC	104	#define CONFIG_SYS_INIT_RAM_ADDR 0x0
cba69eee IC	105	#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */
77fe9887	106	#endif
cba69eee IC	107
	108	#define CONFIG_SYS_INIT_SP_OFFSET \
	109	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	110	#define CONFIG_SYS_INIT_SP_ADDR \
	111	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
	112
	113	#define CONFIG_NR_DRAM_BANKS 1
	114	#define PHYS_SDRAM_0 CONFIG_SYS_SDRAM_BASE
	115	#define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */
	116
a6e50a88 IC	117	#ifdef CONFIG_AHCI
	118	#define CONFIG_LIBATA
	119	#define CONFIG_SCSI_AHCI
	120	#define CONFIG_SCSI_AHCI_PLAT
	121	#define CONFIG_SUNXI_AHCI
0751b138	122	#define CONFIG_SYS_64BIT_LBA
a6e50a88 IC	123	#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
	124	#define CONFIG_SYS_SCSI_MAX_LUN 1
	125	#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
	126	CONFIG_SYS_SCSI_MAX_LUN)
c649e3c9	127	#define CONFIG_SCSI
a6e50a88 IC	128	#endif
a6e50a88 IC	129
cba69eee IC	130	#define CONFIG_SETUP_MEMORY_TAGS
	131	#define CONFIG_CMDLINE_TAG
	132	#define CONFIG_INITRD_TAG
9f852211	133	#define CONFIG_SERIAL_TAG
cba69eee	134
e5268616	135	#ifdef CONFIG_NAND_SUNXI
a0dfa88b	136	#define CONFIG_SYS_NAND_MAX_ECCPOS 1664
4ccae81c BB	137	#define CONFIG_SYS_NAND_ONFI_DETECTION
4ccae81c BB	138	#define CONFIG_SYS_MAX_NAND_DEVICE 8
960caeba PZ	139	#endif
960caeba PZ	140
19e99fb4	141	#ifdef CONFIG_SPL_SPI_SUNXI
19e99fb4 SS	142	#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
	143	#endif
	144
e24ea55c	145	/* mmc config */
44c79879	146	#ifdef CONFIG_MMC
e24ea55c	147	#define CONFIG_GENERIC_MMC
e24ea55c IC	148	#define CONFIG_MMC_SUNXI
e24ea55c IC	149	#define CONFIG_MMC_SUNXI_SLOT 0
e24ea55c IC	150	#define CONFIG_ENV_IS_IN_MMC
e24ea55c IC	151	#define CONFIG_SYS_MMC_ENV_DEV 0 /* first detected MMC controller */
ff2b47f6	152	#endif
e24ea55c	153
5c965ed9 HG	154	/* 64MB of malloc() pool */
5c965ed9 HG	155	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (64 << 20))
cba69eee IC	156
	157	/*
	158	* Miscellaneous configurable options
	159	*/
06beadb0 IC	160	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
06beadb0 IC	161	#define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */
cba69eee	162	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
cba69eee IC	163
	164	/* Boot Argument Buffer Size */
	165	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	166
cba69eee	167	/* standalone support */
e049fe28	168	#define CONFIG_STANDALONE_LOAD_ADDR CONFIG_SYS_LOAD_ADDR
cba69eee	169
cba69eee IC	170	/* baudrate */
	171	#define CONFIG_BAUDRATE 115200
	172
	173	/* The stack sizes are set up in start.S using the settings below */
	174	#define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */
	175
	176	/* FLASH and environment organization */
	177
	178	#define CONFIG_SYS_NO_FLASH
	179
fa5e1020	180	#define CONFIG_SYS_MONITOR_LEN (768 << 10) /* 768 KiB */
2af25b74	181	#define CONFIG_DISPLAY_BOARDINFO
cba69eee	182
e24ea55c	183	#define CONFIG_ENV_OFFSET (544 << 10) /* (8 + 24 + 512) KiB */
cba69eee IC	184	#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
cba69eee IC	185
cba69eee IC	186	#define CONFIG_FAT_WRITE /* enable write access */
	187
	188	#define CONFIG_SPL_FRAMEWORK
cba69eee	189
942cb0b6 SG	190	#define CONFIG_SPL_BOARD_LOAD_IMAGE
942cb0b6 SG	191
d96ebc46	192	#if defined(CONFIG_MACH_SUN9I)
b19236fd SS	193	#define CONFIG_SPL_TEXT_BASE 0x10040 /* sram start+header */
b19236fd SS	194	#define CONFIG_SPL_MAX_SIZE 0x5fc0 /* ? KiB on sun9i */
d96ebc46	195	#elif defined(CONFIG_MACH_SUN50I)
b19236fd SS	196	#define CONFIG_SPL_TEXT_BASE 0x10040 /* sram start+header */
b19236fd SS	197	#define CONFIG_SPL_MAX_SIZE 0x7fc0 /* 32 KiB on sun50i */
d96ebc46	198	#else
b19236fd SS	199	#define CONFIG_SPL_TEXT_BASE 0x40 /* sram start+header */
b19236fd SS	200	#define CONFIG_SPL_MAX_SIZE 0x5fc0 /* 24KB on sun4i/sun7i */
d96ebc46	201	#endif
50827a59	202
d96ebc46	203	#ifndef CONFIG_ARM64
50827a59	204	#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
d96ebc46	205	#endif
50827a59 IC	206
	207	#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 80 /* 40KiB */
	208	#define CONFIG_SPL_PAD_TO 32768 /* decimal for 'dd' */
	209
d96ebc46	210	#if defined(CONFIG_MACH_SUN9I) \|\| defined(CONFIG_MACH_SUN50I)
eb504fa1 AP	211	/* FIXME: 40 KiB instead of 32 KiB ? */
eb504fa1 AP	212	#define LOW_LEVEL_SRAM_STACK 0x00018000
d96ebc46 SS	213	#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
d96ebc46 SS	214	#else
cba69eee IC	215	/* end of 32 KiB in sram */
	216	#define LOW_LEVEL_SRAM_STACK 0x00008000 /* End of sram */
	217	#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
d96ebc46	218	#endif
cba69eee	219
6620377e	220	/* I2C */
0d8382ae JW	221	#if defined CONFIG_AXP152_POWER \|\| defined CONFIG_AXP209_POWER \|\| \
0d8382ae JW	222	defined CONFIG_SY8106A_POWER
ad40610b HG	223	#endif
ad40610b HG	224
6c739c5d PK	225	#if defined CONFIG_I2C0_ENABLE \|\| defined CONFIG_I2C1_ENABLE \|\| \
6c739c5d PK	226	defined CONFIG_I2C2_ENABLE \|\| defined CONFIG_I2C3_ENABLE \|\| \
9d082687	227	defined CONFIG_I2C4_ENABLE \|\| defined CONFIG_R_I2C_ENABLE
8b2db32a	228	#define CONFIG_SYS_I2C
6620377e HG	229	#define CONFIG_SYS_I2C_MVTWSI
	230	#define CONFIG_SYS_I2C_SPEED 400000
	231	#define CONFIG_SYS_I2C_SLAVE 0x7f
8b2db32a	232	#endif
55410089 HG	233
	234	#if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
	235	#define CONFIG_SYS_I2C_SOFT
	236	#define CONFIG_SYS_I2C_SOFT_SPEED 50000
	237	#define CONFIG_SYS_I2C_SOFT_SLAVE 0x00
55410089 HG	238	/* We use pin names in Kconfig and sunxi_name_to_gpio() */
	239	#define CONFIG_SOFT_I2C_GPIO_SDA soft_i2c_gpio_sda
	240	#define CONFIG_SOFT_I2C_GPIO_SCL soft_i2c_gpio_scl
	241	#ifndef __ASSEMBLY__
	242	extern int soft_i2c_gpio_sda;
	243	extern int soft_i2c_gpio_scl;
	244	#endif
1fc42018 HG	245	#define CONFIG_VIDEO_LCD_I2C_BUS 0 /* The lcd panel soft i2c is bus 0 */
	246	#define CONFIG_SYS_SPD_BUS_NUM 1 /* And the axp209 i2c bus is bus 1 */
	247	#else
	248	#define CONFIG_SYS_SPD_BUS_NUM 0 /* The axp209 i2c bus is bus 0 */
	249	#define CONFIG_VIDEO_LCD_I2C_BUS -1 /* NA, but necessary to compile */
55410089 HG	250	#endif
55410089 HG	251
14bc66bd	252	/* PMU */
95ab8fee	253	#if defined CONFIG_AXP152_POWER \|\| defined CONFIG_AXP209_POWER \|\| \
0d8382ae JW	254	defined CONFIG_AXP221_POWER \|\| defined CONFIG_AXP818_POWER \|\| \
0d8382ae JW	255	defined CONFIG_SY8106A_POWER
14bc66bd HN	256	#endif
14bc66bd HN	257
f84269c5	258	#ifndef CONFIG_CONS_INDEX
cba69eee	259	#define CONFIG_CONS_INDEX 1 /* UART0 */
f84269c5	260	#endif
cba69eee	261
a5da3c83	262	#ifdef CONFIG_REQUIRE_SERIAL_CONSOLE
f3133962 HG	263	#if CONFIG_CONS_INDEX == 1
	264	#ifdef CONFIG_MACH_SUN9I
	265	#define OF_STDOUT_PATH "/soc/serial@07000000:115200"
	266	#else
	267	#define OF_STDOUT_PATH "/soc@01c00000/serial@01c28000:115200"
	268	#endif
	269	#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
	270	#define OF_STDOUT_PATH "/soc@01c00000/serial@01c28400:115200"
5cd83b11 LI	271	#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
5cd83b11 LI	272	#define OF_STDOUT_PATH "/soc@01c00000/serial@01c28800:115200"
f3133962 HG	273	#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
	274	#define OF_STDOUT_PATH "/soc@01c00000/serial@01f02800:115200"
	275	#else
	276	#error Unsupported console port nr. Please fix stdout-path in sunxi-common.h.
	277	#endif
a5da3c83	278	#endif /* ifdef CONFIG_REQUIRE_SERIAL_CONSOLE */
f3133962	279
abce2c62 IC	280	/* GPIO */
abce2c62 IC	281	#define CONFIG_SUNXI_GPIO
abce2c62	282
7f2c521f LV	283	#ifdef CONFIG_VIDEO
7f2c521f LV	284	/*
5633a296 HG	285	* The amount of RAM to keep free at the top of RAM when relocating u-boot,
5633a296 HG	286	* to use as framebuffer. This must be a multiple of 4096.
7f2c521f	287	*/
5c965ed9	288	#define CONFIG_SUNXI_MAX_FB_SIZE (16 << 20)
7f2c521f	289
2d7a084b LV	290	/* Do we want to initialize a simple FB? */
	291	#define CONFIG_VIDEO_DT_SIMPLEFB
	292
7f2c521f LV	293	#define CONFIG_VIDEO_SUNXI
	294
	295	#define CONFIG_CFB_CONSOLE
	296	#define CONFIG_VIDEO_SW_CURSOR
	297	#define CONFIG_VIDEO_LOGO
be8ec633	298	#define CONFIG_VIDEO_STD_TIMINGS
75481607	299	#define CONFIG_I2C_EDID
58332f89	300	#define VIDEO_LINE_LEN (pGD->plnSizeX)
7f2c521f LV	301
	302	/* allow both serial and cfb console. */
	303	#define CONFIG_CONSOLE_MUX
	304	/* stop x86 thinking in cfbconsole from trying to init a pc keyboard */
	305	#define CONFIG_VGA_AS_SINGLE_DEVICE
	306
7f2c521f LV	307	#endif /* CONFIG_VIDEO */
7f2c521f LV	308
c26fb9db HG	309	/* Ethernet support */
c26fb9db HG	310	#ifdef CONFIG_SUNXI_EMAC
8145dea4	311	#define CONFIG_PHY_ADDR 1
c26fb9db	312	#define CONFIG_MII /* MII PHY management */
8145dea4	313	#define CONFIG_PHYLIB
c26fb9db HG	314	#endif
c26fb9db HG	315
5835823d	316	#ifdef CONFIG_SUNXI_GMAC
5835823d IC	317	#define CONFIG_PHY_GIGE /* GMAC can use gigabit PHY */
	318	#define CONFIG_PHY_ADDR 1
	319	#define CONFIG_MII /* MII PHY management */
1eae8f66	320	#define CONFIG_PHY_REALTEK
5835823d IC	321	#endif
5835823d IC	322
2582ca0d	323	#ifdef CONFIG_USB_EHCI_HCD
6a72e804 HG	324	#define CONFIG_USB_OHCI_NEW
	325	#define CONFIG_USB_OHCI_SUNXI
	326	#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
3584f30c	327	#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
1a800f7a HG	328	#endif
	329
	330	#ifdef CONFIG_USB_MUSB_SUNXI
95de1e2f	331	#define CONFIG_USB_MUSB_PIO_ONLY
1a800f7a HG	332	#endif
1a800f7a HG	333
b21144eb	334	#ifdef CONFIG_USB_MUSB_GADGET
aaa4a9e3 SP	335	#define CONFIG_USB_FUNCTION_DFU
	336	#define CONFIG_USB_FUNCTION_FASTBOOT
	337	#define CONFIG_USB_FUNCTION_MASS_STORAGE
b21144eb PK	338	#endif
b21144eb PK	339
2a909c5f	340	#ifdef CONFIG_USB_FUNCTION_DFU
2a909c5f SS	341	#define CONFIG_DFU_RAM
	342	#endif
	343
b21144eb PK	344	#ifdef CONFIG_USB_FUNCTION_FASTBOOT
	345	#define CONFIG_CMD_FASTBOOT
	346	#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR
	347	#define CONFIG_FASTBOOT_BUF_SIZE 0x2000000
bac83fb0	348	#define CONFIG_ANDROID_BOOT_IMAGE
b21144eb PK	349
b21144eb PK	350	#define CONFIG_FASTBOOT_FLASH
44c79879 MR	351
44c79879 MR	352	#ifdef CONFIG_MMC
b21144eb PK	353	#define CONFIG_FASTBOOT_FLASH_MMC_DEV 0
	354	#define CONFIG_EFI_PARTITION
	355	#endif
44c79879	356	#endif
b21144eb PK	357
b21144eb PK	358	#ifdef CONFIG_USB_FUNCTION_MASS_STORAGE
b21144eb PK	359	#endif
b21144eb PK	360
86b49093 HG	361	#ifdef CONFIG_USB_KEYBOARD
	362	#define CONFIG_CONSOLE_MUX
	363	#define CONFIG_PREBOOT
	364	#define CONFIG_SYS_STDIO_DEREGISTER
eab9433a	365	#define CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE
86b49093 HG	366	#endif
86b49093 HG	367
cba69eee IC	368	#if !defined CONFIG_ENV_IS_IN_MMC && \
	369	!defined CONFIG_ENV_IS_IN_NAND && \
	370	!defined CONFIG_ENV_IS_IN_FAT && \
	371	!defined CONFIG_ENV_IS_IN_SPI_FLASH
	372	#define CONFIG_ENV_IS_NOWHERE
	373	#endif
	374
b41d7d05	375	#define CONFIG_MISC_INIT_R
7f2c521f	376	#define CONFIG_SYS_CONSOLE_IS_IN_ENV
b41d7d05	377
cba69eee IC	378	#ifndef CONFIG_SPL_BUILD
cba69eee IC	379	#include <config_distro_defaults.h>
2ec3a612	380
a7925078 SS	381	/* Enable pre-console buffer to get complete log on the VGA console */
a7925078 SS	382	#define CONFIG_PRE_CONSOLE_BUFFER
a8552c7c	383	#define CONFIG_PRE_CON_BUF_SZ 4096 /* Aprox 2 8025 screens /
a7925078	384
671f9ad8 AP	385	#ifdef CONFIG_ARM64
	386	/*
	387	* Boards seem to come with at least 512MB of DRAM.
	388	* The kernel should go at 512K, which is the default text offset (that will
	389	* be adjusted at runtime if needed).
	390	* There is no compression for arm64 kernels (yet), so leave some space
	391	* for really big kernels, say 256MB for now.
	392	* Scripts, PXE and DTBs should go afterwards, leaving the rest for the initrd.
	393	* Align the initrd to a 2MB page.
	394	*/
	395	#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(0080000))
	396	#define FDT_ADDR_R __stringify(SDRAM_OFFSET(FA00000))
	397	#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(FC00000))
	398	#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(FD00000))
	399	#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(FE00000))
	400
	401	#else
8c95c556	402	/*
5c965ed9	403	* 160M RAM (256M minimum minus 64MB heap + 32MB for u-boot, stack, fb, etc.
8c95c556 HG	404	* 32M uncompressed kernel, 16M compressed kernel, 1M fdt,
	405	* 1M script, 1M pxe and the ramdisk at the end.
	406	*/
2a909c5f SS	407
	408	#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(2000000))
	409	#define FDT_ADDR_R __stringify(SDRAM_OFFSET(3000000))
	410	#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(3100000))
	411	#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(3200000))
	412	#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(3300000))
671f9ad8	413	#endif
2a909c5f	414
846e3254	415	#define MEM_LAYOUT_ENV_SETTINGS \
5c965ed9	416	"bootm_size=0xa000000\0" \
2a909c5f SS	417	"kernel_addr_r=" KERNEL_ADDR_R "\0" \
	418	"fdt_addr_r=" FDT_ADDR_R "\0" \
	419	"scriptaddr=" SCRIPT_ADDR_R "\0" \
	420	"pxefile_addr_r=" PXEFILE_ADDR_R "\0" \
	421	"ramdisk_addr_r=" RAMDISK_ADDR_R "\0"
	422
	423	#define DFU_ALT_INFO_RAM \
	424	"dfu_alt_info_ram=" \
	425	"kernel ram " KERNEL_ADDR_R " 0x1000000;" \
	426	"fdt ram " FDT_ADDR_R " 0x100000;" \
	427	"ramdisk ram " RAMDISK_ADDR_R " 0x4000000\0"
846e3254	428
41f8e9f5 CYT	429	#ifdef CONFIG_MMC
41f8e9f5 CYT	430	#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
5a37a400 KM	431	#if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
	432	#define BOOT_TARGET_DEVICES_MMC_EXTRA(func) func(MMC, mmc, 1)
	433	#else
	434	#define BOOT_TARGET_DEVICES_MMC_EXTRA(func)
	435	#endif
41f8e9f5 CYT	436	#else
41f8e9f5 CYT	437	#define BOOT_TARGET_DEVICES_MMC(func)
5a37a400	438	#define BOOT_TARGET_DEVICES_MMC_EXTRA(func)
41f8e9f5 CYT	439	#endif
41f8e9f5 CYT	440
2ec3a612 HG	441	#ifdef CONFIG_AHCI
	442	#define BOOT_TARGET_DEVICES_SCSI(func) func(SCSI, scsi, 0)
	443	#else
	444	#define BOOT_TARGET_DEVICES_SCSI(func)
	445	#endif
	446
2582ca0d	447	#ifdef CONFIG_USB_STORAGE
859b3f14 CYT	448	#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0)
	449	#else
	450	#define BOOT_TARGET_DEVICES_USB(func)
	451	#endif
	452
f3b589c0 BN	453	/* FEL boot support, auto-execute boot.scr if a script address was provided */
	454	#define BOOTENV_DEV_FEL(devtypeu, devtypel, instance) \
	455	"bootcmd_fel=" \
	456	"if test -n ${fel_booted} && test -n ${fel_scriptaddr}; then " \
	457	"echo '(FEL boot)'; " \
	458	"source ${fel_scriptaddr}; " \
	459	"fi\0"
	460	#define BOOTENV_DEV_NAME_FEL(devtypeu, devtypel, instance) \
	461	"fel "
	462
2ec3a612	463	#define BOOT_TARGET_DEVICES(func) \
f3b589c0	464	func(FEL, fel, na) \
41f8e9f5	465	BOOT_TARGET_DEVICES_MMC(func) \
5a37a400	466	BOOT_TARGET_DEVICES_MMC_EXTRA(func) \
2ec3a612	467	BOOT_TARGET_DEVICES_SCSI(func) \
859b3f14	468	BOOT_TARGET_DEVICES_USB(func) \
2ec3a612 HG	469	func(PXE, pxe, na) \
	470	func(DHCP, dhcp, na)
	471
3b824025 HG	472	#ifdef CONFIG_OLD_SUNXI_KERNEL_COMPAT
	473	#define BOOTCMD_SUNXI_COMPAT \
	474	"bootcmd_sunxi_compat=" \
	475	"setenv root /dev/mmcblk0p3 rootwait; " \
	476	"if ext2load mmc 0 0x44000000 uEnv.txt; then " \
	477	"echo Loaded environment from uEnv.txt; " \
	478	"env import -t 0x44000000 ${filesize}; " \
	479	"fi; " \
	480	"setenv bootargs console=${console} root=${root} ${extraargs}; " \
	481	"ext2load mmc 0 0x43000000 script.bin && " \
	482	"ext2load mmc 0 0x48000000 uImage && " \
	483	"bootm 0x48000000\0"
	484	#else
	485	#define BOOTCMD_SUNXI_COMPAT
	486	#endif
	487
2ec3a612 HG	488	#include <config_distro_bootcmd.h>
2ec3a612 HG	489
86b49093 HG	490	#ifdef CONFIG_USB_KEYBOARD
	491	#define CONSOLE_STDIN_SETTINGS \
	492	"preboot=usb start\0" \
	493	"stdin=serial,usbkbd\0"
	494	#else
7f2c521f LV	495	#define CONSOLE_STDIN_SETTINGS \
7f2c521f LV	496	"stdin=serial\0"
86b49093	497	#endif
7f2c521f LV	498
	499	#ifdef CONFIG_VIDEO
	500	#define CONSOLE_STDOUT_SETTINGS \
	501	"stdout=serial,vga\0" \
	502	"stderr=serial,vga\0"
	503	#else
	504	#define CONSOLE_STDOUT_SETTINGS \
	505	"stdout=serial\0" \
	506	"stderr=serial\0"
	507	#endif
	508
	509	#define CONSOLE_ENV_SETTINGS \
	510	CONSOLE_STDIN_SETTINGS \
	511	CONSOLE_STDOUT_SETTINGS
	512
2ec3a612	513	#define CONFIG_EXTRA_ENV_SETTINGS \
7f2c521f	514	CONSOLE_ENV_SETTINGS \
846e3254	515	MEM_LAYOUT_ENV_SETTINGS \
2a909c5f	516	DFU_ALT_INFO_RAM \
25acd33f	517	"fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
846e3254	518	"console=ttyS0,115200\0" \
3b824025	519	BOOTCMD_SUNXI_COMPAT \
2ec3a612 HG	520	BOOTENV
	521
	522	#else /* ifndef CONFIG_SPL_BUILD */
	523	#define CONFIG_EXTRA_ENV_SETTINGS
cba69eee IC	524	#endif
	525
	526	#endif /* _SUNXI_COMMON_CONFIG_H */