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f9c6fac4 SB |
1 | /* |
2 | * Copyright (C) 2011 | |
3 | * Stefano Babic, DENX Software Engineering, sbabic@denx.de. | |
4 | * | |
5 | * Copyright (C) 2009 TechNexion Ltd. | |
6 | * | |
1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
f9c6fac4 SB |
8 | */ |
9 | ||
10 | #ifndef __TAM3517_H | |
11 | #define __TAM3517_H | |
12 | ||
13 | /* | |
14 | * High Level Configuration Options | |
15 | */ | |
16 | #define CONFIG_OMAP /* in a TI OMAP core */ | |
17 | #define CONFIG_OMAP34XX /* which is a 34XX */ | |
308252ad | 18 | #define CONFIG_OMAP_GPIO |
806d2792 | 19 | #define CONFIG_OMAP_COMMON |
f9c6fac4 SB |
20 | |
21 | #define CONFIG_SYS_TEXT_BASE 0x80008000 | |
22 | ||
23 | #define CONFIG_SYS_CACHELINE_SIZE 64 | |
24 | ||
25 | #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ | |
26 | ||
27 | #include <asm/arch/cpu.h> /* get chip and board defs */ | |
28 | #include <asm/arch/omap3.h> | |
29 | ||
30 | /* | |
31 | * Display CPU and Board information | |
32 | */ | |
33 | #define CONFIG_DISPLAY_CPUINFO | |
34 | #define CONFIG_DISPLAY_BOARDINFO | |
35 | ||
36 | /* Clock Defines */ | |
37 | #define V_OSCK 26000000 /* Clock output from T2 */ | |
38 | #define V_SCLK (V_OSCK >> 1) | |
39 | ||
f9c6fac4 SB |
40 | #define CONFIG_MISC_INIT_R |
41 | ||
42 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ | |
43 | #define CONFIG_SETUP_MEMORY_TAGS | |
44 | #define CONFIG_INITRD_TAG | |
45 | #define CONFIG_REVISION_TAG | |
46 | ||
47 | /* | |
48 | * Size of malloc() pool | |
49 | */ | |
50 | #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ | |
51 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10) + \ | |
52 | 2 * 1024 * 1024) | |
53 | /* | |
54 | * DDR related | |
55 | */ | |
56 | #define CONFIG_OMAP3_MICRON_DDR /* Micron DDR */ | |
57 | #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) | |
58 | ||
59 | /* | |
60 | * Hardware drivers | |
61 | */ | |
62 | ||
63 | /* | |
64 | * NS16550 Configuration | |
65 | */ | |
66 | #define CONFIG_SYS_NS16550 | |
67 | #define CONFIG_SYS_NS16550_SERIAL | |
68 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) | |
69 | #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ | |
70 | ||
71 | /* | |
72 | * select serial console configuration | |
73 | */ | |
74 | #define CONFIG_CONS_INDEX 1 | |
75 | #define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 | |
76 | #define CONFIG_SERIAL1 /* UART1 */ | |
77 | ||
78 | /* allow to overwrite serial and ethaddr */ | |
79 | #define CONFIG_ENV_OVERWRITE | |
80 | #define CONFIG_BAUDRATE 115200 | |
81 | #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ | |
82 | 115200} | |
83 | #define CONFIG_MMC | |
84 | #define CONFIG_OMAP_HSMMC | |
85 | #define CONFIG_GENERIC_MMC | |
86 | #define CONFIG_DOS_PARTITION | |
87 | ||
88 | /* EHCI */ | |
89 | #define CONFIG_OMAP3_GPIO_5 | |
90 | #define CONFIG_USB_EHCI | |
91 | #define CONFIG_USB_EHCI_OMAP | |
8c589d6f SB |
92 | #define CONFIG_USB_ULPI |
93 | #define CONFIG_USB_ULPI_VIEWPORT_OMAP | |
f9c6fac4 SB |
94 | #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 25 |
95 | #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 | |
96 | #define CONFIG_USB_STORAGE | |
97 | ||
f9c6fac4 SB |
98 | /* commands to include */ |
99 | #include <config_cmd_default.h> | |
100 | ||
101 | #define CONFIG_CMD_CACHE | |
102 | #define CONFIG_CMD_DHCP | |
103 | #define CONFIG_CMD_EXT2 /* EXT2 Support */ | |
104 | #define CONFIG_CMD_FAT /* FAT support */ | |
105 | #define CONFIG_CMD_GPIO | |
106 | #define CONFIG_CMD_I2C /* I2C serial bus support */ | |
107 | #define CONFIG_CMD_MII | |
108 | #define CONFIG_CMD_MMC /* MMC support */ | |
109 | #define CONFIG_CMD_NET | |
110 | #define CONFIG_CMD_NFS | |
111 | #define CONFIG_CMD_NAND /* NAND support */ | |
112 | #define CONFIG_CMD_PING | |
113 | #define CONFIG_CMD_USB | |
8103c6f0 | 114 | #define CONFIG_CMD_EEPROM |
f9c6fac4 SB |
115 | |
116 | #undef CONFIG_CMD_FLASH /* only NAND on the SOM */ | |
117 | #undef CONFIG_CMD_IMLS | |
118 | ||
119 | #define CONFIG_SYS_NO_FLASH | |
120 | #define CONFIG_HARD_I2C | |
121 | #define CONFIG_SYS_I2C_SPEED 400000 | |
122 | #define CONFIG_SYS_I2C_SLAVE 1 | |
8103c6f0 SB |
123 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */ |
124 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ | |
125 | #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 | |
f9c6fac4 SB |
126 | #define CONFIG_DRIVER_OMAP34XX_I2C |
127 | ||
128 | ||
129 | /* | |
130 | * Board NAND Info. | |
131 | */ | |
132 | #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ | |
133 | /* to access */ | |
134 | /* nand at CS0 */ | |
135 | ||
136 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ | |
137 | /* NAND devices */ | |
f9c6fac4 SB |
138 | |
139 | #define CONFIG_AUTO_COMPLETE | |
140 | ||
141 | /* | |
142 | * Miscellaneous configurable options | |
143 | */ | |
144 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
145 | #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ | |
f9c6fac4 SB |
146 | #define CONFIG_CMDLINE_EDITING |
147 | #define CONFIG_AUTO_COMPLETE | |
148 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ | |
149 | ||
150 | /* Print Buffer Size */ | |
151 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
152 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
153 | #define CONFIG_SYS_MAXARGS 32 /* max number of command */ | |
154 | /* args */ | |
155 | /* Boot Argument Buffer Size */ | |
156 | #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) | |
157 | /* memtest works on */ | |
158 | #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) | |
159 | #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ | |
160 | 0x01F00000) /* 31MB */ | |
161 | ||
162 | #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ | |
163 | /* address */ | |
164 | ||
165 | /* | |
166 | * AM3517 has 12 GP timers, they can be driven by the system clock | |
167 | * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). | |
168 | * This rate is divided by a local divisor. | |
169 | */ | |
170 | #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 | |
171 | #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ | |
f9c6fac4 | 172 | |
f9c6fac4 SB |
173 | /* |
174 | * Physical Memory Map | |
175 | */ | |
176 | #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ | |
177 | #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 | |
f9c6fac4 SB |
178 | #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 |
179 | ||
180 | /* | |
181 | * FLASH and environment organization | |
182 | */ | |
183 | ||
184 | /* **** PISMO SUPPORT *** */ | |
185 | ||
186 | /* Configure the PISMO */ | |
187 | #define PISMO1_NAND_SIZE GPMC_SIZE_128M | |
188 | ||
189 | #define CONFIG_NAND_OMAP_GPMC | |
190 | #define GPMC_NAND_ECC_LP_x16_LAYOUT | |
191 | #define CONFIG_ENV_IS_IN_NAND | |
192 | #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */ | |
193 | ||
194 | /* Redundant Environment */ | |
195 | #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ | |
196 | #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET | |
197 | #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET | |
198 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ | |
199 | 2 * CONFIG_SYS_ENV_SECT_SIZE) | |
200 | #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE | |
201 | ||
202 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 | |
203 | #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 | |
204 | #define CONFIG_SYS_INIT_RAM_SIZE 0x800 | |
205 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ | |
206 | CONFIG_SYS_INIT_RAM_SIZE - \ | |
207 | GENERATED_GBL_DATA_SIZE) | |
208 | ||
209 | /* | |
210 | * ethernet support, EMAC | |
211 | * | |
212 | */ | |
213 | #define CONFIG_DRIVER_TI_EMAC | |
214 | #define CONFIG_DRIVER_TI_EMAC_USE_RMII | |
215 | #define CONFIG_MII | |
216 | #define CONFIG_EMAC_MDIO_PHY_NUM 0 | |
f9c6fac4 SB |
217 | #define CONFIG_BOOTP_DNS |
218 | #define CONFIG_BOOTP_DNS2 | |
219 | #define CONFIG_BOOTP_SEND_HOSTNAME | |
220 | #define CONFIG_NET_RETRY_COUNT 10 | |
f9c6fac4 SB |
221 | |
222 | /* Defines for SPL */ | |
223 | #define CONFIG_SPL | |
47f7bcae | 224 | #define CONFIG_SPL_FRAMEWORK |
d7cb93b2 | 225 | #define CONFIG_SPL_BOARD_INIT |
f9c6fac4 SB |
226 | #define CONFIG_SPL_CONSOLE |
227 | #define CONFIG_SPL_NAND_SIMPLE | |
228 | #define CONFIG_SPL_NAND_SOFTECC | |
229 | #define CONFIG_SPL_NAND_WORKSPACE 0x8f07f000 /* below BSS */ | |
230 | ||
231 | #define CONFIG_SPL_LIBCOMMON_SUPPORT | |
232 | #define CONFIG_SPL_LIBDISK_SUPPORT | |
233 | #define CONFIG_SPL_I2C_SUPPORT | |
234 | #define CONFIG_SPL_LIBGENERIC_SUPPORT | |
235 | #define CONFIG_SPL_SERIAL_SUPPORT | |
16e41c85 | 236 | #define CONFIG_SPL_GPIO_SUPPORT |
f9c6fac4 SB |
237 | #define CONFIG_SPL_POWER_SUPPORT |
238 | #define CONFIG_SPL_NAND_SUPPORT | |
6f2f01b9 SW |
239 | #define CONFIG_SPL_NAND_BASE |
240 | #define CONFIG_SPL_NAND_DRIVERS | |
241 | #define CONFIG_SPL_NAND_ECC | |
f9c6fac4 SB |
242 | #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" |
243 | ||
244 | #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ | |
e0820ccc | 245 | #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ |
f9c6fac4 SB |
246 | #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK |
247 | ||
248 | #define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 | |
249 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 | |
250 | #define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ | |
251 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 | |
252 | ||
253 | /* NAND boot config */ | |
254 | #define CONFIG_SYS_NAND_PAGE_COUNT 64 | |
255 | #define CONFIG_SYS_NAND_PAGE_SIZE 2048 | |
256 | #define CONFIG_SYS_NAND_OOBSIZE 64 | |
257 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) | |
258 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE | |
259 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 | |
260 | #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\ | |
261 | 48, 49, 50, 51, 52, 53, 54, 55,\ | |
262 | 56, 57, 58, 59, 60, 61, 62, 63} | |
263 | #define CONFIG_SYS_NAND_ECCSIZE 256 | |
264 | #define CONFIG_SYS_NAND_ECCBYTES 3 | |
265 | ||
f9c6fac4 SB |
266 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE |
267 | ||
268 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 | |
269 | #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 | |
270 | ||
271 | #define CONFIG_OF_LIBFDT | |
272 | #define CONFIG_FIT | |
273 | #define CONFIG_CMD_UBI | |
274 | #define CONFIG_CMD_UBIFS | |
275 | #define CONFIG_RBTREE | |
276 | #define CONFIG_LZO | |
277 | #define CONFIG_MTD_PARTITIONS | |
278 | #define CONFIG_MTD_DEVICE | |
279 | #define CONFIG_CMD_MTDPARTS | |
280 | ||
281 | /* Setup MTD for NAND on the SOM */ | |
282 | #define MTDIDS_DEFAULT "nand0=omap2-nand.0" | |
283 | #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \ | |
1fdabedd SB |
284 | "1m(u-boot),256k(env1)," \ |
285 | "256k(env2),6m(kernel),-(rootfs)" | |
f9c6fac4 | 286 | |
f9c6fac4 SB |
287 | #define CONFIG_TAM3517_SETTINGS \ |
288 | "netdev=eth0\0" \ | |
289 | "nandargs=setenv bootargs root=${nandroot} " \ | |
290 | "rootfstype=${nandrootfstype}\0" \ | |
291 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
292 | "nfsroot=${serverip}:${rootpath}\0" \ | |
293 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
294 | "addip_sta=setenv bootargs ${bootargs} " \ | |
295 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
296 | ":${hostname}:${netdev}:off panic=1\0" \ | |
297 | "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ | |
298 | "addip=if test -n ${ipdyn};then run addip_dyn;" \ | |
299 | "else run addip_sta;fi\0" \ | |
300 | "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ | |
301 | "addtty=setenv bootargs ${bootargs}" \ | |
302 | " console=ttyO0,${baudrate}\0" \ | |
303 | "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ | |
304 | "loadaddr=82000000\0" \ | |
305 | "kernel_addr_r=82000000\0" \ | |
93ea89f0 MV |
306 | "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \ |
307 | "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \ | |
f9c6fac4 SB |
308 | "flash_self=run ramargs addip addtty addmtd addmisc;" \ |
309 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ | |
310 | "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ | |
311 | "bootm ${kernel_addr}\0" \ | |
312 | "nandboot=run nandargs addip addtty addmtd addmisc;" \ | |
313 | "nand read ${kernel_addr_r} kernel\0" \ | |
314 | "bootm ${kernel_addr_r}\0" \ | |
315 | "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ | |
316 | "run nfsargs addip addtty addmtd addmisc;" \ | |
317 | "bootm ${kernel_addr_r}\0" \ | |
318 | "net_self=if run net_self_load;then " \ | |
319 | "run ramargs addip addtty addmtd addmisc;" \ | |
320 | "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \ | |
321 | "else echo Images not loades;fi\0" \ | |
93ea89f0 | 322 | "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0" \ |
f9c6fac4 SB |
323 | "load=tftp ${loadaddr} ${u-boot}\0" \ |
324 | "loadmlo=tftp ${loadaddr} ${mlo}\0" \ | |
93ea89f0 | 325 | "mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0" \ |
f9c6fac4 SB |
326 | "uboot_addr=0x80000\0" \ |
327 | "update=nandecc sw;nand erase ${uboot_addr} 100000;" \ | |
328 | "nand write ${loadaddr} ${uboot_addr} 80000\0" \ | |
329 | "updatemlo=nandecc hw;nand erase 0 20000;" \ | |
330 | "nand write ${loadaddr} 0 20000\0" \ | |
331 | "upd=if run load;then echo Updating u-boot;if run update;" \ | |
332 | "then echo U-Boot updated;" \ | |
333 | "else echo Error updating u-boot !;" \ | |
334 | "echo Board without bootloader !!;" \ | |
335 | "fi;" \ | |
336 | "else echo U-Boot not downloaded..exiting;fi\0" \ | |
337 | ||
8103c6f0 SB |
338 | |
339 | /* | |
340 | * this is common code for all TAM3517 boards. | |
341 | * MAC address is stored from manufacturer in | |
342 | * I2C EEPROM | |
343 | */ | |
344 | #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) | |
8103c6f0 SB |
345 | /* |
346 | * The I2C EEPROM on the TAM3517 contains | |
347 | * mac address and production data | |
348 | */ | |
349 | struct tam3517_module_info { | |
350 | char customer[48]; | |
351 | char product[48]; | |
352 | ||
353 | /* | |
354 | * bit 0~47 : sequence number | |
355 | * bit 48~55 : week of year, from 0. | |
356 | * bit 56~63 : year | |
357 | */ | |
358 | unsigned long long sequence_number; | |
359 | ||
360 | /* | |
361 | * bit 0~7 : revision fixed | |
362 | * bit 8~15 : revision major | |
363 | * bit 16~31 : TNxxx | |
364 | */ | |
365 | unsigned int revision; | |
366 | unsigned char eth_addr[4][8]; | |
367 | unsigned char _rev[100]; | |
368 | }; | |
369 | ||
31f5b651 SB |
370 | #define TAM3517_READ_EEPROM(info, ret) \ |
371 | do { \ | |
8103c6f0 SB |
372 | i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); \ |
373 | if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, \ | |
31f5b651 SB |
374 | (void *)info, sizeof(*info))) \ |
375 | ret = 1; \ | |
376 | else \ | |
377 | ret = 0; \ | |
378 | } while (0) | |
379 | ||
380 | #define TAM3517_READ_MAC_FROM_EEPROM(info) \ | |
381 | do { \ | |
382 | char buf[80], ethname[20]; \ | |
383 | int i; \ | |
8103c6f0 | 384 | memset(buf, 0, sizeof(buf)); \ |
31f5b651 | 385 | for (i = 0 ; i < ARRAY_SIZE((info)->eth_addr); i++) { \ |
8103c6f0 | 386 | sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X", \ |
31f5b651 SB |
387 | (info)->eth_addr[i][5], \ |
388 | (info)->eth_addr[i][4], \ | |
389 | (info)->eth_addr[i][3], \ | |
390 | (info)->eth_addr[i][2], \ | |
391 | (info)->eth_addr[i][1], \ | |
392 | (info)->eth_addr[i][0]); \ | |
8103c6f0 SB |
393 | \ |
394 | if (i) \ | |
395 | sprintf(ethname, "eth%daddr", i); \ | |
396 | else \ | |
397 | sprintf(ethname, "ethaddr"); \ | |
398 | printf("Setting %s from EEPROM with %s\n", ethname, buf);\ | |
399 | setenv(ethname, buf); \ | |
400 | } \ | |
401 | } while (0) | |
31f5b651 SB |
402 | |
403 | /* The following macros are taken from Technexion's documentation */ | |
404 | #define TAM3517_sequence_number(info) \ | |
405 | ((info)->sequence_number % 0x1000000000000LL) | |
406 | #define TAM3517_week_of_year(info) (((info)->sequence_number >> 48) % 0x100) | |
407 | #define TAM3517_year(info) ((info)->sequence_number >> 56) | |
408 | #define TAM3517_revision_fixed(info) ((info)->revision % 0x100) | |
409 | #define TAM3517_revision_major(info) (((info)->revision >> 8) % 0x100) | |
410 | #define TAM3517_revision_tn(info) ((info)->revision >> 16) | |
411 | ||
412 | #define TAM3517_PRINT_SOM_INFO(info) \ | |
413 | do { \ | |
414 | printf("Vendor:%s\n", (info)->customer); \ | |
415 | printf("SOM: %s\n", (info)->product); \ | |
416 | printf("SeqNr: %02llu%02llu%012llu\n", \ | |
417 | TAM3517_year(info), \ | |
418 | TAM3517_week_of_year(info), \ | |
419 | TAM3517_sequence_number(info)); \ | |
420 | printf("Rev: TN%u %u.%u\n", \ | |
421 | TAM3517_revision_tn(info), \ | |
422 | TAM3517_revision_major(info), \ | |
423 | TAM3517_revision_fixed(info)); \ | |
424 | } while (0) | |
425 | ||
8103c6f0 SB |
426 | #endif |
427 | ||
f9c6fac4 | 428 | #endif /* __TAM3517_H */ |