[people/ms/u-boot.git] / include / configs / trats2.h

/*
 * Copyright (C) 2013 Samsung Electronics
 * Sanghee Kim <sh0130.kim@samsung.com>
 * Piotr Wilczek <p.wilczek@samsung.com>
 *
 * Configuation settings for the SAMSUNG TRATS2 (EXYNOS4412) board.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_TRATS2_H
#define __CONFIG_TRATS2_H

#include <configs/exynos4-common.h>

#define CONFIG_TIZEN			/* TIZEN lib */

#define CONFIG_SYS_L2CACHE_OFF
#ifndef CONFIG_SYS_L2CACHE_OFF
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE	0x10502000
#endif

/* TRATS2 has 4 banks of DRAM */
#define CONFIG_NR_DRAM_BANKS		4
#define CONFIG_SYS_SDRAM_BASE		0x40000000
#define PHYS_SDRAM_1			CONFIG_SYS_SDRAM_BASE
#define SDRAM_BANK_SIZE			(256 << 20)	/* 256 MB */
/* memtest works on */
#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5E00000)
#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x3E00000)

#define CONFIG_SYS_TEXT_BASE		0x43e00000

/* select serial console configuration */
#define CONFIG_SERIAL2
#define CONFIG_BAUDRATE			115200

/* Console configuration */
#define CONFIG_SYS_CONSOLE_INFO_QUIET
#define CONFIG_SYS_CONSOLE_IS_IN_ENV

#define CONFIG_BOOTARGS			"Please use defined boot"
#define CONFIG_BOOTCOMMAND		"run autoboot"
#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC2,115200n8\0"

#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_LOAD_ADDR \
					- GENERATED_GBL_DATA_SIZE)

#define CONFIG_SYS_MEM_TOP_HIDE	(1 << 20)	/* ram console */

#define CONFIG_SYS_MONITOR_BASE	0x00000000

#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV		CONFIG_MMC_DEFAULT_DEV
#define CONFIG_ENV_SIZE			4096
#define CONFIG_ENV_OFFSET		((32 - 4) << 10) /* 32KiB - 4KiB */

#define CONFIG_ENV_OVERWRITE

#define CONFIG_ENV_VARS_UBOOT_CONFIG
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG

/* Tizen - partitions definitions */
#define PARTS_CSA		"csa-mmc"
#define PARTS_BOOT		"boot"
#define PARTS_QBOOT		"qboot"
#define PARTS_CSC		"csc"
#define PARTS_ROOT		"platform"
#define PARTS_DATA		"data"
#define PARTS_UMS		"ums"

#define PARTS_DEFAULT \
	"uuid_disk=${uuid_gpt_disk};" \
	"name="PARTS_CSA",start=5MiB,size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \
	"name="PARTS_BOOT",size=60MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
	"name="PARTS_QBOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_QBOOT"};" \
	"name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \
	"name="PARTS_ROOT",size=1536MiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \
	"name="PARTS_DATA",size=3000MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
	"name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \

#define CONFIG_DFU_ALT \
	"u-boot raw 0x80 0x800;" \
	"/uImage ext4 0 2;" \
	"/modem.bin ext4 0 2;" \
	"/exynos4412-trats2.dtb ext4 0 2;" \
	""PARTS_CSA" part 0 1;" \
	""PARTS_BOOT" part 0 2;" \
	""PARTS_QBOOT" part 0 3;" \
	""PARTS_CSC" part 0 4;" \
	""PARTS_ROOT" part 0 5;" \
	""PARTS_DATA" part 0 6;" \
	""PARTS_UMS" part 0 7;" \
	"params.bin raw 0x38 0x8;" \
	"/Image.itb ext4 0 2\0"

#define CONFIG_EXTRA_ENV_SETTINGS \
	"bootk=" \
		"run loaduimage;" \
		"if run loaddtb; then " \
			"bootm 0x40007FC0 - ${fdtaddr};" \
		"fi;" \
		"bootm 0x40007FC0;\0" \
	"updatebackup=" \
		"mmc dev 0 2; mmc write 0x51000000 0 0x800;" \
		" mmc dev 0 0\0" \
	"updatebootb=" \
		"mmc read 0x51000000 0x80 0x800; run updatebackup\0" \
	"mmcboot=" \
		"setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
		"${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \
		"run bootk\0" \
	"bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \
	"boottrace=setenv opts initcall_debug; run bootcmd\0" \
	"verify=n\0" \
	"rootfstype=ext4\0" \
	"console=" CONFIG_DEFAULT_CONSOLE \
	"kernelname=uImage\0" \
	"loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 " \
		"${kernelname}\0" \
	"loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \
		"${fdtfile}\0" \
	"mmcdev=" __stringify(CONFIG_MMC_DEFAULT_DEV) "\0" \
	"mmcbootpart=2\0" \
	"mmcrootpart=5\0" \
	"opts=always_resume=1\0" \
	"partitions=" PARTS_DEFAULT \
	"dfu_alt_info=" CONFIG_DFU_ALT \
	"uartpath=ap\0" \
	"usbpath=ap\0" \
	"consoleon=set console console=ttySAC2,115200n8; save; reset\0" \
	"consoleoff=set console console=ram; save; reset\0" \
	"spladdr=0x40000100\0" \
	"splsize=0x200\0" \
	"splfile=falcon.bin\0" \
	"spl_export=" \
		   "setexpr spl_imgsize ${splsize} + 8 ;" \
		   "setenv spl_imgsize 0x${spl_imgsize};" \
		   "setexpr spl_imgaddr ${spladdr} - 8 ;" \
		   "setexpr spl_addr_tmp ${spladdr} - 4 ;" \
		   "mw.b ${spl_imgaddr} 0x00 ${spl_imgsize};run loaduimage;" \
		   "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
		   "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo};" \
		   "spl export atags 0x40007FC0;" \
		   "crc32 ${spladdr} ${splsize} ${spl_imgaddr};" \
		   "mw.l ${spl_addr_tmp} ${splsize};" \
		   "ext4write mmc ${mmcdev}:${mmcbootpart}" \
		   " /${splfile} ${spl_imgaddr} ${spl_imgsize};" \
		   "setenv spl_imgsize;" \
		   "setenv spl_imgaddr;" \
		   "setenv spl_addr_tmp;\0" \
	CONFIG_EXTRA_ENV_ITB \
	"fdtaddr=40800000\0" \

/* GPT */
#define CONFIG_RANDOM_UUID

/* I2C */
#include <asm/arch/gpio.h>

#define CONFIG_CMD_I2C

#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_S3C24X0
#define CONFIG_SYS_I2C_S3C24X0_SPEED	100000
#define CONFIG_SYS_I2C_S3C24X0_SLAVE	0
#define CONFIG_MAX_I2C_NUM		8
#define CONFIG_SYS_I2C_SOFT
#define CONFIG_SYS_I2C_SOFT_SPEED	50000
#define CONFIG_SYS_I2C_SOFT_SLAVE	0x00
#define I2C_SOFT_DECLARATIONS2
#define CONFIG_SYS_I2C_SOFT_SPEED_2     50000
#define CONFIG_SYS_I2C_SOFT_SLAVE_2     0x00
#define CONFIG_SOFT_I2C_READ_REPEATED_START
#define CONFIG_SYS_I2C_INIT_BOARD

#ifndef __ASSEMBLY__
int get_soft_i2c_scl_pin(void);
int get_soft_i2c_sda_pin(void);
#endif
#define CONFIG_SOFT_I2C_GPIO_SCL	get_soft_i2c_scl_pin()
#define CONFIG_SOFT_I2C_GPIO_SDA	get_soft_i2c_sda_pin()

/* POWER */
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_POWER_MAX77686
#define CONFIG_POWER_PMIC_MAX77693
#define CONFIG_POWER_MUIC_MAX77693
#define CONFIG_POWER_FG_MAX77693
#define CONFIG_POWER_BATTERY_TRATS2

/* Security subsystem - enable hw_rand() */
#define CONFIG_EXYNOS_ACE_SHA
#define CONFIG_LIB_HW_RAND

/* Common misc for Samsung */
#define CONFIG_MISC_COMMON

#define CONFIG_MISC_INIT_R

/* Download menu - Samsung common */
#define CONFIG_LCD_MENU
#define CONFIG_LCD_MENU_BOARD

/* Download menu - definitions for check keys */
#ifndef __ASSEMBLY__
#include <power/max77686_pmic.h>

#define KEY_PWR_PMIC_NAME		"MAX77686_PMIC"
#define KEY_PWR_STATUS_REG		MAX77686_REG_PMIC_STATUS1
#define KEY_PWR_STATUS_MASK		(1 << 0)
#define KEY_PWR_INTERRUPT_REG		MAX77686_REG_PMIC_INT1
#define KEY_PWR_INTERRUPT_MASK		(1 << 1)

#define KEY_VOL_UP_GPIO			EXYNOS4X12_GPIO_X22
#define KEY_VOL_DOWN_GPIO		EXYNOS4X12_GPIO_X33
#endif /* __ASSEMBLY__ */

/* LCD console */
#define LCD_BPP                 LCD_COLOR16
#define CONFIG_SYS_WHITE_ON_BLACK

/* LCD */
#define CONFIG_EXYNOS_FB
#define CONFIG_LCD
#define CONFIG_CMD_BMP
#define CONFIG_BMP_16BPP
#define CONFIG_FB_ADDR		0x52504000
#define CONFIG_S6E8AX0
#define CONFIG_EXYNOS_MIPI_DSIM
#define CONFIG_VIDEO_BMP_GZIP
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54)

#endif	/* __CONFIG_H */
Commit	Line	Data
4d6c9671 PW	1	/*
	2	* Copyright (C) 2013 Samsung Electronics
	3	* Sanghee Kim <sh0130.kim@samsung.com>
	4	* Piotr Wilczek <p.wilczek@samsung.com>
	5	*
	6	* Configuation settings for the SAMSUNG TRATS2 (EXYNOS4412) board.
	7	*
	8	* SPDX-License-Identifier: GPL-2.0+
	9	*/
	10
1ecab0f3 PW	11	#ifndef __CONFIG_TRATS2_H
1ecab0f3 PW	12	#define __CONFIG_TRATS2_H
4d6c9671	13
4c7bb1d2	14	#include <configs/exynos4-common.h>
4d6c9671	15
1ecab0f3	16	#define CONFIG_TIZEN /* TIZEN lib */
4d6c9671	17
c4e96dbf	18	#define CONFIG_SYS_L2CACHE_OFF
4d6c9671 PW	19	#ifndef CONFIG_SYS_L2CACHE_OFF
	20	#define CONFIG_SYS_L2_PL310
	21	#define CONFIG_SYS_PL310_BASE 0x10502000
	22	#endif
	23
1ecab0f3 PW	24	/* TRATS2 has 4 banks of DRAM */
	25	#define CONFIG_NR_DRAM_BANKS 4
	26	#define CONFIG_SYS_SDRAM_BASE 0x40000000
	27	#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
	28	#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */
	29	/* memtest works on */
	30	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
	31	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
	32	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
4d6c9671	33
00b132bf	34	#define CONFIG_SYS_TEXT_BASE 0x43e00000
4d6c9671	35
4d6c9671 PW	36	/* select serial console configuration */
4d6c9671 PW	37	#define CONFIG_SERIAL2
1ecab0f3	38	#define CONFIG_BAUDRATE 115200
4d6c9671	39
1ecab0f3 PW	40	/* Console configuration */
	41	#define CONFIG_SYS_CONSOLE_INFO_QUIET
	42	#define CONFIG_SYS_CONSOLE_IS_IN_ENV
4d6c9671	43
1ecab0f3	44	#define CONFIG_BOOTARGS "Please use defined boot"
1018b0a5	45	#define CONFIG_BOOTCOMMAND "run autoboot"
2ee93246	46	#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
4d6c9671	47
1ecab0f3 PW	48	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \
1ecab0f3 PW	49	- GENERATED_GBL_DATA_SIZE)
4d6c9671	50
1ecab0f3 PW	51	#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */
	52
	53	#define CONFIG_SYS_MONITOR_BASE 0x00000000
	54
	55	#define CONFIG_ENV_IS_IN_MMC
	56	#define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV
	57	#define CONFIG_ENV_SIZE 4096
	58	#define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */
4d6c9671 PW	59
4d6c9671 PW	60	#define CONFIG_ENV_OVERWRITE
4d6c9671	61
8c57fb7d PW	62	#define CONFIG_ENV_VARS_UBOOT_CONFIG
	63	#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
	64
4d6c9671	65	/* Tizen - partitions definitions */
18f3e0eb	66	#define PARTS_CSA "csa-mmc"
4d6c9671	67	#define PARTS_BOOT "boot"
18f3e0eb	68	#define PARTS_QBOOT "qboot"
dca36684	69	#define PARTS_CSC "csc"
4d6c9671 PW	70	#define PARTS_ROOT "platform"
4d6c9671 PW	71	#define PARTS_DATA "data"
4d6c9671 PW	72	#define PARTS_UMS "ums"
	73
	74	#define PARTS_DEFAULT \
a5e15bbb	75	"uuid_disk=${uuid_gpt_disk};" \
dca36684	76	"name="PARTS_CSA",start=5MiB,size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \
18f3e0eb PM	77	"name="PARTS_BOOT",size=60MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
18f3e0eb PM	78	"name="PARTS_QBOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_QBOOT"};" \
4d6c9671	79	"name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \
dca36684	80	"name="PARTS_ROOT",size=1536MiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \
18f3e0eb	81	"name="PARTS_DATA",size=3000MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
4d6c9671 PW	82	"name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \
4d6c9671 PW	83
09f98010	84	#define CONFIG_DFU_ALT \
b7d4259a	85	"u-boot raw 0x80 0x800;" \
dcb7eb66 ŁM	86	"/uImage ext4 0 2;" \
	87	"/modem.bin ext4 0 2;" \
	88	"/exynos4412-trats2.dtb ext4 0 2;" \
18f3e0eb	89	""PARTS_CSA" part 0 1;" \
cdd15bce	90	""PARTS_BOOT" part 0 2;" \
18f3e0eb PM	91	""PARTS_QBOOT" part 0 3;" \
18f3e0eb PM	92	""PARTS_CSC" part 0 4;" \
cdd15bce ŁM	93	""PARTS_ROOT" part 0 5;" \
cdd15bce ŁM	94	""PARTS_DATA" part 0 6;" \
a0afc6f3	95	""PARTS_UMS" part 0 7;" \
1018b0a5 ŁM	96	"params.bin raw 0x38 0x8;" \
1018b0a5 ŁM	97	"/Image.itb ext4 0 2\0"
09f98010	98
4d6c9671 PW	99	#define CONFIG_EXTRA_ENV_SETTINGS \
4d6c9671 PW	100	"bootk=" \
425e26de PW	101	"run loaduimage;" \
	102	"if run loaddtb; then " \
	103	"bootm 0x40007FC0 - ${fdtaddr};" \
	104	"fi;" \
	105	"bootm 0x40007FC0;\0" \
4d6c9671	106	"updatebackup=" \
188c42b3 JC	107	"mmc dev 0 2; mmc write 0x51000000 0 0x800;" \
188c42b3 JC	108	" mmc dev 0 0\0" \
4d6c9671	109	"updatebootb=" \
188c42b3	110	"mmc read 0x51000000 0x80 0x800; run updatebackup\0" \
4d6c9671 PW	111	"mmcboot=" \
	112	"setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
	113	"${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \
425e26de	114	"run bootk\0" \
4d6c9671 PW	115	"bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \
	116	"boottrace=setenv opts initcall_debug; run bootcmd\0" \
	117	"verify=n\0" \
	118	"rootfstype=ext4\0" \
	119	"console=" CONFIG_DEFAULT_CONSOLE \
	120	"kernelname=uImage\0" \
2c8043c9 PW	121	"loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 " \
2c8043c9 PW	122	"${kernelname}\0" \
4d6c9671 PW	123	"loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \
4d6c9671 PW	124	"${fdtfile}\0" \
a5e15bbb	125	"mmcdev=" __stringify(CONFIG_MMC_DEFAULT_DEV) "\0" \
4d6c9671 PW	126	"mmcbootpart=2\0" \
	127	"mmcrootpart=5\0" \
	128	"opts=always_resume=1\0" \
	129	"partitions=" PARTS_DEFAULT \
09f98010	130	"dfu_alt_info=" CONFIG_DFU_ALT \
4d6c9671 PW	131	"uartpath=ap\0" \
	132	"usbpath=ap\0" \
	133	"consoleon=set console console=ttySAC2,115200n8; save; reset\0" \
	134	"consoleoff=set console console=ram; save; reset\0" \
	135	"spladdr=0x40000100\0" \
	136	"splsize=0x200\0" \
	137	"splfile=falcon.bin\0" \
	138	"spl_export=" \
	139	"setexpr spl_imgsize ${splsize} + 8 ;" \
	140	"setenv spl_imgsize 0x${spl_imgsize};" \
	141	"setexpr spl_imgaddr ${spladdr} - 8 ;" \
	142	"setexpr spl_addr_tmp ${spladdr} - 4 ;" \
	143	"mw.b ${spl_imgaddr} 0x00 ${spl_imgsize};run loaduimage;" \
	144	"setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
	145	"${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo};" \
	146	"spl export atags 0x40007FC0;" \
	147	"crc32 ${spladdr} ${splsize} ${spl_imgaddr};" \
	148	"mw.l ${spl_addr_tmp} ${splsize};" \
	149	"ext4write mmc ${mmcdev}:${mmcbootpart}" \
	150	" /${splfile} ${spl_imgaddr} ${spl_imgsize};" \
	151	"setenv spl_imgsize;" \
	152	"setenv spl_imgaddr;" \
	153	"setenv spl_addr_tmp;\0" \
1018b0a5	154	CONFIG_EXTRA_ENV_ITB \
4d6c9671	155	"fdtaddr=40800000\0" \
4d6c9671	156
519fdde9	157	/* GPT */
aafd2c5d	158	#define CONFIG_RANDOM_UUID
4d6c9671	159
4d6c9671 PW	160	/* I2C */
	161	#include <asm/arch/gpio.h>
	162
1ecab0f3 PW	163	#define CONFIG_CMD_I2C
1ecab0f3 PW	164
4d6c9671	165	#define CONFIG_SYS_I2C
2d8f1e27 PW	166	#define CONFIG_SYS_I2C_S3C24X0
	167	#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000
	168	#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0
	169	#define CONFIG_MAX_I2C_NUM 8
	170	#define CONFIG_SYS_I2C_SOFT
4d6c9671 PW	171	#define CONFIG_SYS_I2C_SOFT_SPEED 50000
	172	#define CONFIG_SYS_I2C_SOFT_SLAVE 0x00
	173	#define I2C_SOFT_DECLARATIONS2
	174	#define CONFIG_SYS_I2C_SOFT_SPEED_2 50000
	175	#define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x00
4d6c9671 PW	176	#define CONFIG_SOFT_I2C_READ_REPEATED_START
4d6c9671 PW	177	#define CONFIG_SYS_I2C_INIT_BOARD
2d8f1e27 PW	178
	179	#ifndef __ASSEMBLY__
	180	int get_soft_i2c_scl_pin(void);
	181	int get_soft_i2c_sda_pin(void);
	182	#endif
	183	#define CONFIG_SOFT_I2C_GPIO_SCL get_soft_i2c_scl_pin()
	184	#define CONFIG_SOFT_I2C_GPIO_SDA get_soft_i2c_sda_pin()
4d6c9671 PW	185
	186	/* POWER */
	187	#define CONFIG_POWER
	188	#define CONFIG_POWER_I2C
	189	#define CONFIG_POWER_MAX77686
	190	#define CONFIG_POWER_PMIC_MAX77693
	191	#define CONFIG_POWER_MUIC_MAX77693
	192	#define CONFIG_POWER_FG_MAX77693
	193	#define CONFIG_POWER_BATTERY_TRATS2
	194
e0021706 PM	195	/* Security subsystem - enable hw_rand() */
	196	#define CONFIG_EXYNOS_ACE_SHA
	197	#define CONFIG_LIB_HW_RAND
	198
679549d1 PM	199	/* Common misc for Samsung */
	200	#define CONFIG_MISC_COMMON
	201
	202	#define CONFIG_MISC_INIT_R
	203
f64236a9 PM	204	/* Download menu - Samsung common */
	205	#define CONFIG_LCD_MENU
	206	#define CONFIG_LCD_MENU_BOARD
	207
	208	/* Download menu - definitions for check keys */
	209	#ifndef __ASSEMBLY__
	210	#include <power/max77686_pmic.h>
	211
	212	#define KEY_PWR_PMIC_NAME "MAX77686_PMIC"
	213	#define KEY_PWR_STATUS_REG MAX77686_REG_PMIC_STATUS1
	214	#define KEY_PWR_STATUS_MASK (1 << 0)
	215	#define KEY_PWR_INTERRUPT_REG MAX77686_REG_PMIC_INT1
	216	#define KEY_PWR_INTERRUPT_MASK (1 << 1)
	217
9b97b727 AS	218	#define KEY_VOL_UP_GPIO EXYNOS4X12_GPIO_X22
9b97b727 AS	219	#define KEY_VOL_DOWN_GPIO EXYNOS4X12_GPIO_X33
f64236a9 PM	220	#endif /* __ASSEMBLY__ */
	221
	222	/* LCD console */
	223	#define LCD_BPP LCD_COLOR16
	224	#define CONFIG_SYS_WHITE_ON_BLACK
	225
4d6c9671 PW	226	/* LCD */
	227	#define CONFIG_EXYNOS_FB
	228	#define CONFIG_LCD
	229	#define CONFIG_CMD_BMP
2df21cb3	230	#define CONFIG_BMP_16BPP
4d6c9671 PW	231	#define CONFIG_FB_ADDR 0x52504000
	232	#define CONFIG_S6E8AX0
	233	#define CONFIG_EXYNOS_MIPI_DSIM
	234	#define CONFIG_VIDEO_BMP_GZIP
903afe18	235	#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54)
4d6c9671	236
4d6c9671	237	#endif /* __CONFIG_H */