[people/ms/u-boot.git] / include / configs / tricorder.h

/*
 * (C) Copyright 2006-2008
 * Texas Instruments.
 * Richard Woodruff <r-woodruff2@ti.com>
 * Syed Mohammed Khasim <x0khasim@ti.com>
 *
 * (C) Copyright 2012
 * Corscience GmbH & Co. KG
 * Thomas Weber <weber@corscience.de>
 *
 * Configuration settings for the Tricorder board.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* High Level Configuration Options */
#define CONFIG_OMAP			/* in a TI OMAP core */
#define CONFIG_OMAP34XX			/* which is a 34XX */
#define CONFIG_OMAP_COMMON

#define CONFIG_MACH_TYPE		MACH_TYPE_TRICORDER
/*
 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
 * 64 bytes before this address should be set aside for u-boot.img's
 * header. That is 0x800FFFC0--0x80100000 should not be used for any
 * other needs.
 */
#define CONFIG_SYS_TEXT_BASE		0x80100000

#define CONFIG_SDRC			/* The chip has SDRC controller */

#include <asm/arch/cpu.h>		/* get chip and board defs */
#include <asm/arch/omap3.h>

/* Display CPU and Board information */
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO

/* Clock Defines */
#define V_OSCK				26000000 /* Clock output from T2 */
#define V_SCLK				(V_OSCK >> 1)

#define CONFIG_MISC_INIT_R

#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG

#define CONFIG_OF_LIBFDT

/* Size of malloc() pool */
#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
						/* Sector */
#define CONFIG_SYS_MALLOC_LEN		(1024*1024)

/* Hardware drivers */

/* NS16550 Configuration */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		48000000 /* 48MHz (APLL96/2) */

/* select serial console configuration */
#define CONFIG_CONS_INDEX		3
#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
#define CONFIG_SERIAL3			3
#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
					115200}

/* MMC */
#define CONFIG_GENERIC_MMC
#define CONFIG_MMC
#define CONFIG_OMAP_HSMMC
#define CONFIG_DOS_PARTITION

/* I2C */
#define CONFIG_HARD_I2C
#define CONFIG_SYS_I2C_SPEED		100000
#define CONFIG_SYS_I2C_SLAVE		1
#define CONFIG_DRIVER_OMAP34XX_I2C	1

/* TWL4030 */
#define CONFIG_TWL4030_POWER
#define CONFIG_TWL4030_LED

/* Board NAND Info */
#define CONFIG_SYS_NO_FLASH		/* no NOR flash */
#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
#define MTDIDS_DEFAULT			"nand0=nand"
#define MTDPARTS_DEFAULT		"mtdparts=nand:" \
						"512k(u-boot-spl)," \
						"1920k(u-boot)," \
						"128k(u-boot-env)," \
						"4m(kernel)," \
						"-(fs)"

#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
							/* to access nand */
#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
							/* to access nand at */
							/* CS0 */
#define GPMC_NAND_ECC_LP_x16_LAYOUT	1

#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
							/* devices */
#define CONFIG_NAND_OMAP_BCH8
#define CONFIG_BCH

/* commands to include */
#include <config_cmd_default.h>

#define CONFIG_CMD_EXT2			/* EXT2 Support */
#define CONFIG_CMD_FAT			/* FAT support */
#define CONFIG_CMD_I2C			/* I2C serial bus support */
#define CONFIG_CMD_MMC			/* MMC support */
#define CONFIG_CMD_MTDPARTS		/* Enable MTD parts commands */
#define CONFIG_CMD_NAND			/* NAND support */
#define CONFIG_CMD_NAND_LOCK_UNLOCK	/* nand (un)lock commands */
#define CONFIG_CMD_UBI			/* UBI commands */
#define CONFIG_CMD_UBIFS		/* UBIFS commands */
#define CONFIG_LZO			/* LZO is needed for UBIFS */

#undef CONFIG_CMD_NET
#undef CONFIG_CMD_NFS
#undef CONFIG_CMD_FPGA			/* FPGA configuration Support */
#undef CONFIG_CMD_IMI			/* iminfo */
#undef CONFIG_CMD_JFFS2			/* JFFS2 Support */

/* needed for ubi */
#define CONFIG_RBTREE
#define CONFIG_MTD_DEVICE       /* needed for mtdparts commands */
#define CONFIG_MTD_PARTITIONS

/* Environment information */
#define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */

#define CONFIG_BOOTDELAY		3

#define CONFIG_EXTRA_ENV_SETTINGS \
	"loadaddr=0x82000000\0" \
	"console=ttyO2,115200n8\0" \
	"mmcdev=0\0" \
	"vram=12M\0" \
	"lcdmode=800x600\0" \
	"defaultdisplay=lcd\0" \
	"kernelopts=rw rootwait\0" \
	"commonargs=" \
		"setenv bootargs console=${console} " \
		"vram=${vram} " \
		"omapfb.mode=lcd:${lcdmode} " \
		"omapdss.def_disp=${defaultdisplay}\0" \
	"mmcargs=" \
		"run commonargs; " \
		"setenv bootargs ${bootargs} " \
		"root=/dev/mmcblk0p2 " \
		"${kernelopts}\0" \
	"nandargs=" \
		"run commonargs; " \
		"setenv bootargs ${bootargs} " \
		"omapfb.mode=lcd:${lcdmode} " \
		"omapdss.def_disp=${defaultdisplay} " \
		"root=ubi0:root " \
		"ubi.mtd=4 " \
		"rootfstype=ubifs " \
		"${kernelopts}\0" \
	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
	"bootscript=echo Running bootscript from mmc ...; " \
		"source ${loadaddr}\0" \
	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
	"eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \
	"mmcboot=echo Booting from mmc ...; " \
		"run mmcargs; " \
		"bootm ${loadaddr}\0" \
	"loaduimage_ubi=mtd default; " \
		"ubi part fs; " \
		"ubifsmount ubi:root; " \
		"ubifsload ${loadaddr} /boot/uImage\0" \
	"nandboot=echo Booting from nand ...; " \
		"run nandargs; " \
		"run loaduimage_ubi; " \
		"bootm ${loadaddr}\0" \
	"autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
			"if run loadbootscript; then " \
				"run bootscript; " \
			"else " \
				"if run loaduimage; then " \
					"run mmcboot; " \
				"else run nandboot; " \
				"fi; " \
			"fi; " \
		"else run nandboot; fi\0"


#define CONFIG_BOOTCOMMAND "run autoboot"

/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_PROMPT		"OMAP3 Tricorder # "
#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		16	/* max number of command args */

/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)

#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0 + 0x07000000)
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
					0x01000000) /* 16MB */

#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0 + 0x02000000)

/*
 * OMAP3 has 12 GP timers, they can be driven by the system clock
 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 * This rate is divided by a local divisor.
 */
#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
#define CONFIG_SYS_PTV			2 /* Divisor: 2^(PTV+1) => 8 */

/*  Physical Memory Map  */
#define CONFIG_NR_DRAM_BANKS		2 /* CS1 may or may not be populated */
#define PHYS_SDRAM_1			OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_2			OMAP34XX_SDRC_CS1

/* NAND and environment organization  */
#define PISMO1_NAND_SIZE		GPMC_SIZE_128M

#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */

#define CONFIG_ENV_IS_IN_NAND		1
#define CONFIG_ENV_OFFSET		0x260000 /* environment starts here */

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE	0x800
#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_INIT_RAM_ADDR + \
						CONFIG_SYS_INIT_RAM_SIZE - \
						GENERATED_GBL_DATA_SIZE)

/* SRAM config */
#define CONFIG_SYS_SRAM_START		0x40200000
#define CONFIG_SYS_SRAM_SIZE		0x10000

/* Defines for SPL */
#define CONFIG_SPL
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_NAND_SIMPLE

#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBDISK_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_POWER_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME        "u-boot.img"
#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION    1
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */

#define CONFIG_SPL_TEXT_BASE		0x40200000 /*CONFIG_SYS_SRAM_START*/
#define CONFIG_SPL_MAX_SIZE		(55 * 1024)	/* 7 KB for stack */
#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK

#define CONFIG_SPL_BSS_START_ADDR	0x80000000 /*CONFIG_SYS_SDRAM_BASE*/
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000

/* NAND boot config */
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT	64
#define CONFIG_SYS_NAND_PAGE_SIZE	2048
#define CONFIG_SYS_NAND_OOBSIZE		64
#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS		{12, 13, 14, 15, 16, 17, 18, 19, 20,\
			21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,\
			34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46,\
			47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59,\
			60, 61, 62, 63}

#define CONFIG_SYS_NAND_ECCSIZE		512
#define CONFIG_SYS_NAND_ECCBYTES	13

#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE

#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x200000

#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000	/* 1 MB */

#endif /* __CONFIG_H */
Commit	Line	Data
8167af14 TW	1	/*
	2	* (C) Copyright 2006-2008
	3	* Texas Instruments.
	4	* Richard Woodruff <r-woodruff2@ti.com>
	5	* Syed Mohammed Khasim <x0khasim@ti.com>
	6	*
	7	* (C) Copyright 2012
	8	* Corscience GmbH & Co. KG
	9	* Thomas Weber <weber@corscience.de>
	10	*
	11	* Configuration settings for the Tricorder board.
	12	*
3765b3e7	13	* SPDX-License-Identifier: GPL-2.0+
8167af14 TW	14	*/
	15
	16	#ifndef __CONFIG_H
	17	#define __CONFIG_H
	18
	19	/* High Level Configuration Options */
	20	#define CONFIG_OMAP /* in a TI OMAP core */
	21	#define CONFIG_OMAP34XX /* which is a 34XX */
806d2792	22	#define CONFIG_OMAP_COMMON
8167af14 TW	23
	24	#define CONFIG_MACH_TYPE MACH_TYPE_TRICORDER
	25	/*
	26	* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
	27	* 64 bytes before this address should be set aside for u-boot.img's
	28	* header. That is 0x800FFFC0--0x80100000 should not be used for any
	29	* other needs.
	30	*/
	31	#define CONFIG_SYS_TEXT_BASE 0x80100000
	32
	33	#define CONFIG_SDRC /* The chip has SDRC controller */
	34
	35	#include <asm/arch/cpu.h> /* get chip and board defs */
	36	#include <asm/arch/omap3.h>
	37
	38	/* Display CPU and Board information */
	39	#define CONFIG_DISPLAY_CPUINFO
	40	#define CONFIG_DISPLAY_BOARDINFO
	41
	42	/* Clock Defines */
	43	#define V_OSCK 26000000 /* Clock output from T2 */
	44	#define V_SCLK (V_OSCK >> 1)
	45
8167af14 TW	46	#define CONFIG_MISC_INIT_R
	47
	48	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
	49	#define CONFIG_SETUP_MEMORY_TAGS
	50	#define CONFIG_INITRD_TAG
	51	#define CONFIG_REVISION_TAG
	52
	53	#define CONFIG_OF_LIBFDT
	54
	55	/* Size of malloc() pool */
	56	#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
	57	/* Sector */
36f3aab2	58	#define CONFIG_SYS_MALLOC_LEN (1024*1024)
8167af14 TW	59
	60	/* Hardware drivers */
	61
	62	/* NS16550 Configuration */
	63	#define CONFIG_SYS_NS16550
	64	#define CONFIG_SYS_NS16550_SERIAL
	65	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	66	#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
	67
	68	/* select serial console configuration */
	69	#define CONFIG_CONS_INDEX 3
	70	#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
	71	#define CONFIG_SERIAL3 3
	72	#define CONFIG_BAUDRATE 115200
	73	#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
	74	115200}
	75
	76	/* MMC */
	77	#define CONFIG_GENERIC_MMC
	78	#define CONFIG_MMC
	79	#define CONFIG_OMAP_HSMMC
	80	#define CONFIG_DOS_PARTITION
	81
	82	/* I2C */
	83	#define CONFIG_HARD_I2C
	84	#define CONFIG_SYS_I2C_SPEED 100000
	85	#define CONFIG_SYS_I2C_SLAVE 1
8167af14 TW	86	#define CONFIG_DRIVER_OMAP34XX_I2C 1
	87
	88	/* TWL4030 */
	89	#define CONFIG_TWL4030_POWER
	90	#define CONFIG_TWL4030_LED
	91
	92	/* Board NAND Info */
	93	#define CONFIG_SYS_NO_FLASH /* no NOR flash */
	94	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
	95	#define MTDIDS_DEFAULT "nand0=nand"
	96	#define MTDPARTS_DEFAULT "mtdparts=nand:" \
	97	"512k(u-boot-spl)," \
	98	"1920k(u-boot)," \
	99	"128k(u-boot-env)," \
	100	"4m(kernel)," \
	101	"-(fs)"
	102
	103	#define CONFIG_NAND_OMAP_GPMC
	104	#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
	105	/* to access nand */
	106	#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
	107	/* to access nand at */
	108	/* CS0 */
	109	#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
	110
	111	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
	112	/* devices */
616cf60e AB	113	#define CONFIG_NAND_OMAP_BCH8
616cf60e AB	114	#define CONFIG_BCH
8167af14 TW	115
	116	/* commands to include */
	117	#include <config_cmd_default.h>
	118
	119	#define CONFIG_CMD_EXT2 /* EXT2 Support */
	120	#define CONFIG_CMD_FAT /* FAT support */
	121	#define CONFIG_CMD_I2C /* I2C serial bus support */
	122	#define CONFIG_CMD_MMC /* MMC support */
	123	#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
	124	#define CONFIG_CMD_NAND /* NAND support */
	125	#define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */
36f3aab2 BW	126	#define CONFIG_CMD_UBI /* UBI commands */
	127	#define CONFIG_CMD_UBIFS /* UBIFS commands */
	128	#define CONFIG_LZO /* LZO is needed for UBIFS */
8167af14 TW	129
	130	#undef CONFIG_CMD_NET
	131	#undef CONFIG_CMD_NFS
	132	#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
	133	#undef CONFIG_CMD_IMI /* iminfo */
	134	#undef CONFIG_CMD_JFFS2 /* JFFS2 Support */
	135
	136	/* needed for ubi */
	137	#define CONFIG_RBTREE
	138	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
	139	#define CONFIG_MTD_PARTITIONS
	140
	141	/* Environment information */
	142	#define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */
	143
	144	#define CONFIG_BOOTDELAY 3
	145
	146	#define CONFIG_EXTRA_ENV_SETTINGS \
	147	"loadaddr=0x82000000\0" \
	148	"console=ttyO2,115200n8\0" \
5605979a	149	"mmcdev=0\0" \
8167af14 TW	150	"vram=12M\0" \
	151	"lcdmode=800x600\0" \
	152	"defaultdisplay=lcd\0" \
	153	"kernelopts=rw rootwait\0" \
	154	"commonargs=" \
	155	"setenv bootargs console=${console} " \
	156	"vram=${vram} " \
	157	"omapfb.mode=lcd:${lcdmode} " \
	158	"omapdss.def_disp=${defaultdisplay}\0" \
	159	"mmcargs=" \
	160	"run commonargs; " \
	161	"setenv bootargs ${bootargs} " \
	162	"root=/dev/mmcblk0p2 " \
	163	"${kernelopts}\0" \
	164	"nandargs=" \
	165	"run commonargs; " \
	166	"setenv bootargs ${bootargs} " \
	167	"omapfb.mode=lcd:${lcdmode} " \
	168	"omapdss.def_disp=${defaultdisplay} " \
008ec950 BW	169	"root=ubi0:root " \
008ec950 BW	170	"ubi.mtd=4 " \
8167af14 TW	171	"rootfstype=ubifs " \
8167af14 TW	172	"${kernelopts}\0" \
5605979a	173	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
8167af14 TW	174	"bootscript=echo Running bootscript from mmc ...; " \
8167af14 TW	175	"source ${loadaddr}\0" \
5605979a	176	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
8167af14 TW	177	"eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \
	178	"mmcboot=echo Booting from mmc ...; " \
	179	"run mmcargs; " \
	180	"bootm ${loadaddr}\0" \
008ec950 BW	181	"loaduimage_ubi=mtd default; " \
008ec950 BW	182	"ubi part fs; " \
949a7710	183	"ubifsmount ubi:root; " \
008ec950	184	"ubifsload ${loadaddr} /boot/uImage\0" \
8167af14 TW	185	"nandboot=echo Booting from nand ...; " \
8167af14 TW	186	"run nandargs; " \
008ec950	187	"run loaduimage_ubi; " \
8167af14	188	"bootm ${loadaddr}\0" \
66968110	189	"autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
8167af14 TW	190	"if run loadbootscript; then " \
	191	"run bootscript; " \
	192	"else " \
	193	"if run loaduimage; then " \
	194	"run mmcboot; " \
	195	"else run nandboot; " \
	196	"fi; " \
	197	"fi; " \
	198	"else run nandboot; fi\0"
	199
	200
	201	#define CONFIG_BOOTCOMMAND "run autoboot"
	202
	203	/* Miscellaneous configurable options */
	204	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	205	#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
	206	#define CONFIG_AUTO_COMPLETE
8167af14 TW	207	#define CONFIG_SYS_PROMPT "OMAP3 Tricorder # "
	208	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
	209	/* Print Buffer Size */
	210	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	211	sizeof(CONFIG_SYS_PROMPT) + 16)
	212	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	213
	214	/* Boot Argument Buffer Size */
	215	#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
	216
	217	#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x07000000)
	218	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
	219	0x01000000) /* 16MB */
	220
	221	#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000)
	222
	223	/*
	224	* OMAP3 has 12 GP timers, they can be driven by the system clock
	225	* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
	226	* This rate is divided by a local divisor.
	227	*/
	228	#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
	229	#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
8167af14	230
8167af14 TW	231	/* Physical Memory Map */
	232	#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
	233	#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
8167af14 TW	234	#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
	235
	236	/* NAND and environment organization */
	237	#define PISMO1_NAND_SIZE GPMC_SIZE_128M
	238
	239	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
	240
	241	#define CONFIG_ENV_IS_IN_NAND 1
	242	#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */
	243
	244	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	245	#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
	246	#define CONFIG_SYS_INIT_RAM_SIZE 0x800
	247	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
	248	CONFIG_SYS_INIT_RAM_SIZE - \
	249	GENERATED_GBL_DATA_SIZE)
	250
	251	/* SRAM config */
	252	#define CONFIG_SYS_SRAM_START 0x40200000
	253	#define CONFIG_SYS_SRAM_SIZE 0x10000
	254
	255	/* Defines for SPL */
	256	#define CONFIG_SPL
47f7bcae	257	#define CONFIG_SPL_FRAMEWORK
8167af14 TW	258	#define CONFIG_SPL_NAND_SIMPLE
8167af14 TW	259
49175c49	260	#define CONFIG_SPL_BOARD_INIT
8167af14 TW	261	#define CONFIG_SPL_LIBCOMMON_SUPPORT
	262	#define CONFIG_SPL_LIBDISK_SUPPORT
	263	#define CONFIG_SPL_I2C_SUPPORT
	264	#define CONFIG_SPL_LIBGENERIC_SUPPORT
	265	#define CONFIG_SPL_SERIAL_SUPPORT
	266	#define CONFIG_SPL_POWER_SUPPORT
	267	#define CONFIG_SPL_NAND_SUPPORT
6f2f01b9 SW	268	#define CONFIG_SPL_NAND_BASE
	269	#define CONFIG_SPL_NAND_DRIVERS
	270	#define CONFIG_SPL_NAND_ECC
8167af14 TW	271	#define CONFIG_SPL_MMC_SUPPORT
	272	#define CONFIG_SPL_FAT_SUPPORT
	273	#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
	274	#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
	275	#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
	276	#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
	277
	278	#define CONFIG_SPL_TEXT_BASE 0x40200000 /CONFIG_SYS_SRAM_START/
616cf60e	279	#define CONFIG_SPL_MAX_SIZE (55 * 1024) /* 7 KB for stack */
8167af14 TW	280	#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
	281
	282	#define CONFIG_SPL_BSS_START_ADDR 0x80000000 /CONFIG_SYS_SDRAM_BASE/
	283	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
	284
	285	/* NAND boot config */
	286	#define CONFIG_SYS_NAND_5_ADDR_CYCLE
	287	#define CONFIG_SYS_NAND_PAGE_COUNT 64
	288	#define CONFIG_SYS_NAND_PAGE_SIZE 2048
	289	#define CONFIG_SYS_NAND_OOBSIZE 64
	290	#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
	291	#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
616cf60e AB	292	#define CONFIG_SYS_NAND_ECCPOS {12, 13, 14, 15, 16, 17, 18, 19, 20,\
	293	21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,\
	294	34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46,\
	295	47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59,\
	296	60, 61, 62, 63}
8167af14 TW	297
8167af14 TW	298	#define CONFIG_SYS_NAND_ECCSIZE 512
616cf60e	299	#define CONFIG_SYS_NAND_ECCBYTES 13
8167af14	300
8167af14 TW	301	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
	302
	303	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
	304	#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x200000
	305
	306	#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
	307	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
	308
	309	#endif /* __CONFIG_H */