[people/ms/u-boot.git] / include / configs / vexpress_aemv8a.h

/*
 * Configuration for Versatile Express. Parts were derived from other ARM
 *   configurations.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __VEXPRESS_AEMV8A_H
#define __VEXPRESS_AEMV8A_H

/* We use generic board and device manager for v8 Versatile Express */
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_DM

#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
#ifndef CONFIG_SEMIHOSTING
#error CONFIG_TARGET_VEXPRESS64_BASE_FVP requires CONFIG_SEMIHOSTING
#endif
#define CONFIG_ARMV8_SWITCH_TO_EL1
#endif

#define CONFIG_REMAKE_ELF

#define CONFIG_SUPPORT_RAW_INITRD

/* Cache Definitions */
#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_SYS_ICACHE_OFF

#define CONFIG_IDENT_STRING		" vexpress_aemv8a"
#define CONFIG_BOOTP_VCI_STRING		"U-boot.armv8.vexpress_aemv8a"

/* Link Definitions */
#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
/* ATF loads u-boot here for BASE_FVP model */
#define CONFIG_SYS_TEXT_BASE		0x88000000
#define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x03f00000)
#elif CONFIG_TARGET_VEXPRESS64_JUNO
#define CONFIG_SYS_TEXT_BASE		0xe0000000
#define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
#else
#error "Unknown board variant"
#endif

/* Flat Device Tree Definitions */
#define CONFIG_OF_LIBFDT

/* CS register bases for the original memory map. */
#define V2M_PA_CS0			0x00000000
#define V2M_PA_CS1			0x14000000
#define V2M_PA_CS2			0x18000000
#define V2M_PA_CS3			0x1c000000
#define V2M_PA_CS4			0x0c000000
#define V2M_PA_CS5			0x10000000

#define V2M_PERIPH_OFFSET(x)		(x << 16)
#define V2M_SYSREGS			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(1))
#define V2M_SYSCTL			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(2))
#define V2M_SERIAL_BUS_PCI		(V2M_PA_CS3 + V2M_PERIPH_OFFSET(3))

#define V2M_BASE			0x80000000

/* Common peripherals relative to CS7. */
#define V2M_AACI			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(4))
#define V2M_MMCI			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(5))
#define V2M_KMI0			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(6))
#define V2M_KMI1			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(7))

#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
#define V2M_UART0			0x7ff80000
#define V2M_UART1			0x7ff70000
#else /* Not Juno */
#define V2M_UART0			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(9))
#define V2M_UART1			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(10))
#define V2M_UART2			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(11))
#define V2M_UART3			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(12))
#endif

#define V2M_WDT				(V2M_PA_CS3 + V2M_PERIPH_OFFSET(15))

#define V2M_TIMER01			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(17))
#define V2M_TIMER23			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(18))

#define V2M_SERIAL_BUS_DVI		(V2M_PA_CS3 + V2M_PERIPH_OFFSET(22))
#define V2M_RTC				(V2M_PA_CS3 + V2M_PERIPH_OFFSET(23))

#define V2M_CF				(V2M_PA_CS3 + V2M_PERIPH_OFFSET(26))

#define V2M_CLCD			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(31))

/* System register offsets. */
#define V2M_SYS_CFGDATA			(V2M_SYSREGS + 0x0a0)
#define V2M_SYS_CFGCTRL			(V2M_SYSREGS + 0x0a4)
#define V2M_SYS_CFGSTAT			(V2M_SYSREGS + 0x0a8)

/* Generic Timer Definitions */
#define COUNTER_FREQUENCY		(0x1800000)	/* 24MHz */

/* Generic Interrupt Controller Definitions */
#ifdef CONFIG_GICV3
#define GICD_BASE			(0x2f000000)
#define GICR_BASE			(0x2f100000)
#else

#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
#define GICD_BASE			(0x2f000000)
#define GICC_BASE			(0x2c000000)
#elif CONFIG_TARGET_VEXPRESS64_JUNO
#define GICD_BASE			(0x2C010000)
#define GICC_BASE			(0x2C02f000)
#else
#error "Unknown board variant"
#endif
#endif /* !CONFIG_GICV3 */

/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_F_LEN		0x2000
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (8 << 20))

/* Ethernet Configuration */
#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
/* The real hardware Versatile express uses SMSC9118 */
#define CONFIG_SMC911X			1
#define CONFIG_SMC911X_32_BIT		1
#define CONFIG_SMC911X_BASE		(0x018000000)
#else
/* The Vexpress64 simulators use SMSC91C111 */
#define CONFIG_SMC91111			1
#define CONFIG_SMC91111_BASE		(0x01A000000)
#endif

/* PL011 Serial Configuration */
#define CONFIG_DM_SERIAL
#define CONFIG_BAUDRATE			115200
#define CONFIG_CONS_INDEX		0
#define CONFIG_PL01X_SERIAL
#define CONFIG_PL011_SERIAL
#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
#define CONFIG_PL011_CLOCK		7273800
#else
#define CONFIG_PL011_CLOCK		24000000
#endif

/* Command line configuration */
#define CONFIG_MENU
/*#define CONFIG_MENU_SHOW*/
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_BDI
#define CONFIG_CMD_BOOTI
#define CONFIG_CMD_UNZIP
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PXE
#define CONFIG_CMD_ENV
#define CONFIG_CMD_IMI
#define CONFIG_CMD_LOADB
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_RUN
#define CONFIG_CMD_BOOTD
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_SOURCE
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION

/* BOOTP options */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_PXE
#define CONFIG_BOOTP_PXE_CLIENTARCH	0x100

/* Miscellaneous configurable options */
#define CONFIG_SYS_LOAD_ADDR		(V2M_BASE + 0x10000000)

/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS		1
#define PHYS_SDRAM_1			(V2M_BASE)	/* SDRAM Bank #1 */
/* Top 16MB reserved for secure world use */
#define DRAM_SEC_SIZE		0x01000000
#define PHYS_SDRAM_1_SIZE	0x80000000 - DRAM_SEC_SIZE
#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM_1

/* Enable memtest */
#define CONFIG_CMD_MEMTEST
#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)

/* Initial environment variables */
#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
/*
 * Defines where the kernel and FDT exist in NOR flash and where it will
 * be copied into DRAM
 */
#define CONFIG_EXTRA_ENV_SETTINGS	\
				"kernel_name=Image\0"	\
				"kernel_addr=0x80000000\0" \
				"fdt_name=juno\0" \
				"fdt_addr=0x83000000\0" \
				"fdt_high=0xffffffffffffffff\0" \
				"initrd_high=0xffffffffffffffff\0" \

/* Assume we boot with root on the first partition of a USB stick */
#define CONFIG_BOOTARGS		"console=ttyAMA0,115200n8 " \
				"root=/dev/sda1 rw " \
				"rootwait "\
				"earlyprintk=pl011,0x7ff80000 debug user_debug=31 "\
				"loglevel=9"

/* Copy the kernel and FDT to DRAM memory and boot */
#define CONFIG_BOOTCOMMAND	"afs load ${kernel_name} ${kernel_addr} ; " \
				"afs load  ${fdt_name} ${fdt_addr} ; " \
				"fdt addr ${fdt_addr}; fdt resize; " \
				"booti ${kernel_addr} - ${fdt_addr}"

#define CONFIG_BOOTDELAY		1

#elif CONFIG_TARGET_VEXPRESS64_BASE_FVP
#define CONFIG_EXTRA_ENV_SETTINGS	\
				"kernel_name=uImage\0"		\
				"kernel_addr=0x80000000\0"	\
				"initrd_name=ramdisk.img\0"	\
				"initrd_addr=0x88000000\0"	\
				"fdt_name=devtree.dtb\0"	\
				"fdt_addr=0x83000000\0"		\
				"fdt_high=0xffffffffffffffff\0"	\
				"initrd_high=0xffffffffffffffff\0"

#define CONFIG_BOOTARGS		"console=ttyAMA0 earlyprintk=pl011,"\
				"0x1c090000 debug user_debug=31 "\
				"loglevel=9"

#define CONFIG_BOOTCOMMAND	"smhload ${kernel_name} ${kernel_addr}; " \
				"smhload ${fdt_name} $fdt_addr; " \
				"smhload ${initrd_name} $initrd_addr initrd_end; " \
				"fdt addr $fdt_addr; fdt resize; " \
				"fdt chosen $initrd_addr $initrd_end; " \
				"bootm $kernel_addr - $fdt_addr"

#define CONFIG_BOOTDELAY		1

#else
#error "Unknown board variant"
#endif

/* Do not preserve environment */
#define CONFIG_ENV_IS_NOWHERE		1
#define CONFIG_ENV_SIZE			0x1000

/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
#define CONFIG_SYS_PROMPT		"VExpress64# "
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
#define CONFIG_SYS_LONGHELP
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_MAXARGS		64	/* max command args */

/* Flash memory is available on the Juno board only */
#ifndef CONFIG_TARGET_VEXPRESS64_JUNO
#define CONFIG_SYS_NO_FLASH
#else
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_ARMFLASH
#define CONFIG_SYS_FLASH_CFI		1
#define CONFIG_FLASH_CFI_DRIVER		1
#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_32BIT
#define CONFIG_SYS_FLASH_BASE		0x08000000
#define CONFIG_SYS_FLASH_SIZE		0x04000000 /* 64 MiB */
#define CONFIG_SYS_MAX_FLASH_BANKS	2

/* Timeout values in ticks */
#define CONFIG_SYS_FLASH_ERASE_TOUT	(2 * CONFIG_SYS_HZ) /* Erase Timeout */
#define CONFIG_SYS_FLASH_WRITE_TOUT	(2 * CONFIG_SYS_HZ) /* Write Timeout */

/* 255 0x40000 sectors + first or last sector may have 4 erase regions = 259 */
#define CONFIG_SYS_MAX_FLASH_SECT	259		/* Max sectors */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */
#define CONFIG_SYS_FLASH_PROTECTION	/* The devices have real protection */
#define CONFIG_SYS_FLASH_EMPTY_INFO	/* flinfo indicates empty blocks */

#endif

#endif /* __VEXPRESS_AEMV8A_H */
Commit	Line	Data
12916829 DF	1	/*
	2	* Configuration for Versatile Express. Parts were derived from other ARM
	3	* configurations.
	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
	8	#ifndef __VEXPRESS_AEMV8A_H
	9	#define __VEXPRESS_AEMV8A_H
	10
d280ea00	11	/* We use generic board and device manager for v8 Versatile Express */
03ca6a39	12	#define CONFIG_SYS_GENERIC_BOARD
d280ea00	13	#define CONFIG_DM
03ca6a39	14
f91afc4d	15	#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
261d2760	16	#ifndef CONFIG_SEMIHOSTING
f91afc4d	17	#error CONFIG_TARGET_VEXPRESS64_BASE_FVP requires CONFIG_SEMIHOSTING
261d2760	18	#endif
261d2760 DR	19	#define CONFIG_ARMV8_SWITCH_TO_EL1
	20	#endif
	21
12916829 DF	22	#define CONFIG_REMAKE_ELF
12916829 DF	23
12916829 DF	24	#define CONFIG_SUPPORT_RAW_INITRD
	25
	26	/* Cache Definitions */
	27	#define CONFIG_SYS_DCACHE_OFF
	28	#define CONFIG_SYS_ICACHE_OFF
	29
	30	#define CONFIG_IDENT_STRING " vexpress_aemv8a"
	31	#define CONFIG_BOOTP_VCI_STRING "U-boot.armv8.vexpress_aemv8a"
	32
	33	/* Link Definitions */
f91afc4d	34	#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
261d2760 DR	35	/* ATF loads u-boot here for BASE_FVP model */
	36	#define CONFIG_SYS_TEXT_BASE 0x88000000
	37	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000)
ffc10373 LW	38	#elif CONFIG_TARGET_VEXPRESS64_JUNO
	39	#define CONFIG_SYS_TEXT_BASE 0xe0000000
	40	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
261d2760	41	#else
03314f0e	42	#error "Unknown board variant"
261d2760	43	#endif
12916829 DF	44
	45	/* Flat Device Tree Definitions */
	46	#define CONFIG_OF_LIBFDT
	47
12916829 DF	48	/* CS register bases for the original memory map. */
	49	#define V2M_PA_CS0 0x00000000
	50	#define V2M_PA_CS1 0x14000000
	51	#define V2M_PA_CS2 0x18000000
	52	#define V2M_PA_CS3 0x1c000000
	53	#define V2M_PA_CS4 0x0c000000
	54	#define V2M_PA_CS5 0x10000000
	55
	56	#define V2M_PERIPH_OFFSET(x) (x << 16)
	57	#define V2M_SYSREGS (V2M_PA_CS3 + V2M_PERIPH_OFFSET(1))
	58	#define V2M_SYSCTL (V2M_PA_CS3 + V2M_PERIPH_OFFSET(2))
	59	#define V2M_SERIAL_BUS_PCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(3))
	60
	61	#define V2M_BASE 0x80000000
	62
12916829 DF	63	/* Common peripherals relative to CS7. */
	64	#define V2M_AACI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4))
	65	#define V2M_MMCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5))
	66	#define V2M_KMI0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(6))
	67	#define V2M_KMI1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(7))
	68
ffc10373 LW	69	#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
	70	#define V2M_UART0 0x7ff80000
	71	#define V2M_UART1 0x7ff70000
	72	#else /* Not Juno */
12916829 DF	73	#define V2M_UART0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(9))
	74	#define V2M_UART1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(10))
	75	#define V2M_UART2 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(11))
	76	#define V2M_UART3 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(12))
ffc10373	77	#endif
12916829 DF	78
	79	#define V2M_WDT (V2M_PA_CS3 + V2M_PERIPH_OFFSET(15))
	80
	81	#define V2M_TIMER01 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(17))
	82	#define V2M_TIMER23 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(18))
	83
	84	#define V2M_SERIAL_BUS_DVI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(22))
	85	#define V2M_RTC (V2M_PA_CS3 + V2M_PERIPH_OFFSET(23))
	86
	87	#define V2M_CF (V2M_PA_CS3 + V2M_PERIPH_OFFSET(26))
	88
	89	#define V2M_CLCD (V2M_PA_CS3 + V2M_PERIPH_OFFSET(31))
	90
	91	/* System register offsets. */
	92	#define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0)
	93	#define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4)
	94	#define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8)
	95
	96	/* Generic Timer Definitions */
	97	#define COUNTER_FREQUENCY (0x1800000) /* 24MHz */
	98
	99	/* Generic Interrupt Controller Definitions */
c71645ad DF	100	#ifdef CONFIG_GICV3
	101	#define GICD_BASE (0x2f000000)
	102	#define GICR_BASE (0x2f100000)
	103	#else
261d2760	104
f91afc4d	105	#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
261d2760 DR	106	#define GICD_BASE (0x2f000000)
261d2760 DR	107	#define GICC_BASE (0x2c000000)
ffc10373 LW	108	#elif CONFIG_TARGET_VEXPRESS64_JUNO
	109	#define GICD_BASE (0x2C010000)
	110	#define GICC_BASE (0x2C02f000)
261d2760	111	#else
03314f0e	112	#error "Unknown board variant"
261d2760	113	#endif
03314f0e	114	#endif /* !CONFIG_GICV3 */
12916829	115
12916829	116	/* Size of malloc() pool */
d8bafe13	117	#define CONFIG_SYS_MALLOC_F_LEN 0x2000
5bcae13e	118	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20))
12916829	119
b31f9d7a LW	120	/* Ethernet Configuration */
	121	#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
	122	/* The real hardware Versatile express uses SMSC9118 */
	123	#define CONFIG_SMC911X 1
	124	#define CONFIG_SMC911X_32_BIT 1
	125	#define CONFIG_SMC911X_BASE (0x018000000)
	126	#else
	127	/* The Vexpress64 simulators use SMSC91C111 */
3865ceb7 BS	128	#define CONFIG_SMC91111 1
3865ceb7 BS	129	#define CONFIG_SMC91111_BASE (0x01A000000)
b31f9d7a	130	#endif
12916829 DF	131
12916829 DF	132	/* PL011 Serial Configuration */
d8bafe13	133	#define CONFIG_DM_SERIAL
d280ea00	134	#define CONFIG_BAUDRATE 115200
d8bafe13	135	#define CONFIG_CONS_INDEX 0
d280ea00	136	#define CONFIG_PL01X_SERIAL
12916829	137	#define CONFIG_PL011_SERIAL
ffc10373 LW	138	#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
	139	#define CONFIG_PL011_CLOCK 7273800
	140	#else
12916829	141	#define CONFIG_PL011_CLOCK 24000000
ffc10373	142	#endif
12916829 DF	143
	144	/* Command line configuration */
	145	#define CONFIG_MENU
	146	/#define CONFIG_MENU_SHOW/
	147	#define CONFIG_CMD_CACHE
	148	#define CONFIG_CMD_BDI
67172528 TR	149	#define CONFIG_CMD_BOOTI
67172528 TR	150	#define CONFIG_CMD_UNZIP
12916829 DF	151	#define CONFIG_CMD_DHCP
	152	#define CONFIG_CMD_PXE
	153	#define CONFIG_CMD_ENV
12916829	154	#define CONFIG_CMD_IMI
ffc10373	155	#define CONFIG_CMD_LOADB
12916829 DF	156	#define CONFIG_CMD_MEMORY
	157	#define CONFIG_CMD_MII
	158	#define CONFIG_CMD_NET
	159	#define CONFIG_CMD_PING
	160	#define CONFIG_CMD_SAVEENV
	161	#define CONFIG_CMD_RUN
	162	#define CONFIG_CMD_BOOTD
	163	#define CONFIG_CMD_ECHO
	164	#define CONFIG_CMD_SOURCE
	165	#define CONFIG_CMD_FAT
	166	#define CONFIG_DOS_PARTITION
	167
	168	/* BOOTP options */
	169	#define CONFIG_BOOTP_BOOTFILESIZE
	170	#define CONFIG_BOOTP_BOOTPATH
	171	#define CONFIG_BOOTP_GATEWAY
	172	#define CONFIG_BOOTP_HOSTNAME
	173	#define CONFIG_BOOTP_PXE
	174	#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100
	175
	176	/* Miscellaneous configurable options */
	177	#define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x10000000)
	178
	179	/* Physical Memory Map */
	180	#define CONFIG_NR_DRAM_BANKS 1
	181	#define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */
30355708 LW	182	/* Top 16MB reserved for secure world use */
	183	#define DRAM_SEC_SIZE 0x01000000
	184	#define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE
	185	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	186
	187	/* Enable memtest */
	188	#define CONFIG_CMD_MEMTEST
	189	#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
	190	#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
12916829 DF	191
12916829 DF	192	/* Initial environment variables */
10d1491b LW	193	#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
	194	/*
	195	* Defines where the kernel and FDT exist in NOR flash and where it will
	196	* be copied into DRAM
	197	*/
	198	#define CONFIG_EXTRA_ENV_SETTINGS \
	199	"kernel_name=Image\0" \
	200	"kernel_addr=0x80000000\0" \
	201	"fdt_name=juno\0" \
	202	"fdt_addr=0x83000000\0" \
	203	"fdt_high=0xffffffffffffffff\0" \
	204	"initrd_high=0xffffffffffffffff\0" \
	205
	206	/* Assume we boot with root on the first partition of a USB stick */
	207	#define CONFIG_BOOTARGS "console=ttyAMA0,115200n8 " \
	208	"root=/dev/sda1 rw " \
33665f7c	209	"rootwait "\
10d1491b LW	210	"earlyprintk=pl011,0x7ff80000 debug user_debug=31 "\
	211	"loglevel=9"
	212
	213	/* Copy the kernel and FDT to DRAM memory and boot */
	214	#define CONFIG_BOOTCOMMAND "afs load ${kernel_name} ${kernel_addr} ; " \
	215	"afs load ${fdt_name} ${fdt_addr} ; " \
	216	"fdt addr ${fdt_addr}; fdt resize; " \
	217	"booti ${kernel_addr} - ${fdt_addr}"
	218
	219	#define CONFIG_BOOTDELAY 1
	220
	221	#elif CONFIG_TARGET_VEXPRESS64_BASE_FVP
261d2760	222	#define CONFIG_EXTRA_ENV_SETTINGS \
49995ffe LW	223	"kernel_name=uImage\0" \
49995ffe LW	224	"kernel_addr=0x80000000\0" \
261d2760	225	"initrd_name=ramdisk.img\0" \
49995ffe LW	226	"initrd_addr=0x88000000\0" \
	227	"fdt_name=devtree.dtb\0" \
	228	"fdt_addr=0x83000000\0" \
261d2760 DR	229	"fdt_high=0xffffffffffffffff\0" \
	230	"initrd_high=0xffffffffffffffff\0"
	231
	232	#define CONFIG_BOOTARGS "console=ttyAMA0 earlyprintk=pl011,"\
	233	"0x1c090000 debug user_debug=31 "\
	234	"loglevel=9"
	235
49995ffe LW	236	#define CONFIG_BOOTCOMMAND "smhload ${kernel_name} ${kernel_addr}; " \
	237	"smhload ${fdt_name} $fdt_addr; " \
	238	"smhload ${initrd_name} $initrd_addr initrd_end; " \
	239	"fdt addr $fdt_addr; fdt resize; " \
	240	"fdt chosen $initrd_addr $initrd_end; " \
	241	"bootm $kernel_addr - $fdt_addr"
261d2760 DR	242
	243	#define CONFIG_BOOTDELAY 1
	244
	245	#else
03314f0e	246	#error "Unknown board variant"
261d2760	247	#endif
12916829 DF	248
	249	/* Do not preserve environment */
	250	#define CONFIG_ENV_IS_NOWHERE 1
	251	#define CONFIG_ENV_SIZE 0x1000
	252
	253	/* Monitor Command Prompt */
	254	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
	255	#define CONFIG_SYS_PROMPT "VExpress64# "
	256	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	257	sizeof(CONFIG_SYS_PROMPT) + 16)
	258	#define CONFIG_SYS_HUSH_PARSER
12916829 DF	259	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
12916829 DF	260	#define CONFIG_SYS_LONGHELP
5bcae13e	261	#define CONFIG_CMDLINE_EDITING
12916829 DF	262	#define CONFIG_SYS_MAXARGS 64 /* max command args */
12916829 DF	263
14f264e6 LW	264	/* Flash memory is available on the Juno board only */
	265	#ifndef CONFIG_TARGET_VEXPRESS64_JUNO
	266	#define CONFIG_SYS_NO_FLASH
	267	#else
	268	#define CONFIG_CMD_FLASH
10d1491b	269	#define CONFIG_CMD_ARMFLASH
14f264e6 LW	270	#define CONFIG_SYS_FLASH_CFI 1
14f264e6 LW	271	#define CONFIG_FLASH_CFI_DRIVER 1
f19f389f	272	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
14f264e6 LW	273	#define CONFIG_SYS_FLASH_BASE 0x08000000
	274	#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MiB */
	275	#define CONFIG_SYS_MAX_FLASH_BANKS 2
	276
	277	/* Timeout values in ticks */
	278	#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */
	279	#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Write Timeout */
	280
	281	/* 255 0x40000 sectors + first or last sector may have 4 erase regions = 259 */
	282	#define CONFIG_SYS_MAX_FLASH_SECT 259 /* Max sectors */
	283	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */
	284	#define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */
	285	#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */
	286
	287	#endif
	288
12916829	289	#endif /* __VEXPRESS_AEMV8A_H */