[people/ms/u-boot.git] / include / configs / yosemite.h

/*
 * (C) Copyright 2005-2007
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/************************************************************************
 * yosemite.h - configuration for Yosemite & Yellowstone boards
 ***********************************************************************/
#ifndef __CONFIG_H
#define __CONFIG_H

/*-----------------------------------------------------------------------
 * High Level Configuration Options
 *----------------------------------------------------------------------*/
/* This config file is used for Yosemite (440EP) and Yellowstone (440GR)*/
#ifndef CONFIG_YELLOWSTONE
#define CONFIG_440EP		1	/* Specific PPC440EP support	*/
#define CONFIG_HOSTNAME		yosemite
#else
#define CONFIG_440GR		1	/* Specific PPC440GR support	*/
#define CONFIG_HOSTNAME		yellowstone
#endif
#define CONFIG_4xx		1	/* ... PPC4xx family		*/
#define CONFIG_SYS_CLK_FREQ	66666666    /* external freq to pll	*/

#define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f	*/
#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
#define CONFIG_BOARD_RESET	1	/* call board_reset()		*/

/*-----------------------------------------------------------------------
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 *----------------------------------------------------------------------*/
#define CFG_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Monitor	*/
#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
#define CFG_MONITOR_BASE	(-CFG_MONITOR_LEN)
#define CFG_SDRAM_BASE	        0x00000000	    /* _must_ be 0	*/
#define CFG_FLASH_BASE	        0xfc000000	    /* start of FLASH	*/
#define CFG_PCI_MEMBASE	        0xa0000000	    /* mapped pci memory*/
#define CFG_PCI_MEMBASE1        CFG_PCI_MEMBASE  + 0x10000000
#define CFG_PCI_MEMBASE2        CFG_PCI_MEMBASE1 + 0x10000000
#define CFG_PCI_MEMBASE3        CFG_PCI_MEMBASE2 + 0x10000000

/*Don't change either of these*/
#define CFG_PERIPHERAL_BASE     0xef600000	    /* internal peripherals*/
#define CFG_PCI_BASE	        0xe0000000	    /* internal PCI regs*/
/*Don't change either of these*/

#define CFG_USB_DEVICE          0x50000000
#define CFG_NVRAM_BASE_ADDR     0x80000000
#define CFG_BCSR_BASE	        (CFG_NVRAM_BASE_ADDR | 0x2000)
#define CFG_BOOT_BASE_ADDR      0xf0000000

/*-----------------------------------------------------------------------
 * Initial RAM & stack pointer (placed in SDRAM)
 *----------------------------------------------------------------------*/
#define CFG_INIT_RAM_DCACHE	1		/* d-cache as init ram	*/
#define CFG_INIT_RAM_ADDR	0x70000000		/* DCache       */
#define CFG_INIT_RAM_END	(8 << 10)
#define CFG_GBL_DATA_SIZE	256			/* num bytes initial data*/
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Serial Port
 *----------------------------------------------------------------------*/
#define CFG_EXT_SERIAL_CLOCK	11059200 /* use external 11.059MHz clk	*/
#define CONFIG_BAUDRATE		115200
#define CONFIG_SERIAL_MULTI     1
/*define this if you want console on UART1*/
#undef CONFIG_UART1_CONSOLE

#define CFG_BAUDRATE_TABLE  \
    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

/*-----------------------------------------------------------------------
 * Environment
 *----------------------------------------------------------------------*/
/*
 * Define here the location of the environment variables (FLASH or EEPROM).
 * Note: DENX encourages to use redundant environment in FLASH.
 */
#if 1
#define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
#else
#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars	*/
#endif

/*-----------------------------------------------------------------------
 * FLASH related
 *----------------------------------------------------------------------*/
#define CFG_FLASH_CFI				/* The flash is CFI compatible	*/
#define CFG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/
#define CFG_FLASH_CFI_AMD_RESET 1		/* AMD RESET for STM 29W320DB!	*/

#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/

#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */

#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE	0x20000 	/* size of one complete sector	*/
#define CFG_ENV_ADDR		(CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define	CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/

/* Address and size of Redundant Environment Sector	*/
#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
#endif /* CFG_ENV_IS_IN_FLASH */

/*-----------------------------------------------------------------------
 * DDR SDRAM
 *----------------------------------------------------------------------*/
#undef CONFIG_SPD_EEPROM	       /* Don't use SPD EEPROM for setup    */
#define CFG_KBYTES_SDRAM        (128 * 1024)    /* 128MB		    */
#define CFG_SDRAM_BANKS	        (2)


/*-----------------------------------------------------------------------
 * I2C
 *----------------------------------------------------------------------*/
#define CONFIG_HARD_I2C		1	    /* I2C with hardware support	*/
#undef	CONFIG_SOFT_I2C			    /* I2C bit-banged		*/
#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
#define CFG_I2C_SLAVE		0x7F

#define CFG_I2C_MULTI_EEPROMS
#define CFG_I2C_EEPROM_ADDR	(0xa8>>1)
#define CFG_I2C_EEPROM_ADDR_LEN 1
#define CFG_EEPROM_PAGE_WRITE_ENABLE
#define CFG_EEPROM_PAGE_WRITE_BITS 3
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10

#ifdef CFG_ENV_IS_IN_EEPROM
#define CFG_ENV_SIZE		0x200	    /* Size of Environment vars */
#define CFG_ENV_OFFSET		0x0
#endif /* CFG_ENV_IS_IN_EEPROM */

#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

/* Setup some board specific values for the default environment variables */
#ifndef CONFIG_YELLOWSTONE
#define CONFIG_HOSTNAME		yosemite
#define CFG_BOOTFILE		"bootfile=/tftpboot/yosemite/uImage\0"
#define CFG_ROOTPATH		"rootpath=/opt/eldk/ppc_4xxFP\0"
#else
#define CONFIG_HOSTNAME		yellowstone
#define CFG_BOOTFILE		"bootfile=/tftpboot/yellowstone/uImage\0"
#define CFG_ROOTPATH		"rootpath=/opt/eldk/ppc_4xx\0"
#endif

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	CFG_BOOTFILE							\
	CFG_ROOTPATH							\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
	"flash_nfs=run nfsargs addip addtty;"				\
		"bootm ${kernel_addr}\0"				\
	"flash_self=run ramargs addip addtty;"				\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
	        "bootm\0"						\
	"bootfile=/tftpboot/${hostname}/uImage\0"			\
	"kernel_addr=fc000000\0"					\
	"ramdisk_addr=fc180000\0"					\
	"load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0"		\
	"update=protect off fff80000 ffffffff;era fff80000 ffffffff;"	\
		"cp.b 200000 fff80000 80000;"			        \
		"setenv filesize;saveenv\0"				\
	"upd=run load;run update\0"					\
	""
#define CONFIG_BOOTCOMMAND	"run flash_self"

#if 0
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
#else
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
#endif

#define CONFIG_BAUDRATE		115200

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#define CONFIG_MII		1	/* MII PHY management		*/
#define CONFIG_NET_MULTI        1	/* required for netconsole      */
#define CONFIG_PHY1_ADDR        3
#define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
#define CONFIG_PHY_ADDR		1	/* PHY address, See schematics	*/

#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */

#define CONFIG_NETCONSOLE		/* include NetConsole support	*/

/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION

#ifdef CONFIG_440EP
/* USB */
#define CONFIG_USB_OHCI
#define CONFIG_USB_STORAGE

/* Comment this out to enable USB 1.1 device */
#define USB_2_0_DEVICE

#define CMD_USB			(CFG_CMD_USB | CFG_CMD_FAT | CFG_CMD_EXT2)

#define CONFIG_SUPPORT_VFAT
#else
#define CMD_USB			0	/* no USB on 440GR		*/
#endif /* CONFIG_440EP */

#ifdef DEBUG
#define CONFIG_PANIC_HANG
#else
#define CONFIG_HW_WATCHDOG			/* watchdog */
#endif

#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
				CFG_CMD_ASKENV	| \
				CFG_CMD_DHCP	| \
				CFG_CMD_DIAG	| \
				CFG_CMD_ELF	| \
				CFG_CMD_EEPROM	| \
				CFG_CMD_I2C	| \
				CFG_CMD_IRQ	| \
				CFG_CMD_MII	| \
				CFG_CMD_NET	| \
				CFG_CMD_NFS	| \
				CFG_CMD_PCI	| \
				CFG_CMD_PING	| \
				CFG_CMD_REGINFO	| \
				CFG_CMD_SDRAM	| \
				CMD_USB)

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT	        "=> "	/* Monitor Command Prompt	*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE	        1024	/* Console I/O Buffer Size	*/
#else
#define CFG_CBSIZE	        256	/* Console I/O Buffer Size	*/
#endif
#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	        16	/* max number of command args	*/
#define CFG_BARGSIZE	        CFG_CBSIZE /* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x0400000 /* memtest works on	        */
#define CFG_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/

#define CFG_LOAD_ADDR		0x100000	/* default load address */
#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
#define CONFIG_LYNXKDI          1       /* support kdi files            */

#define CFG_HZ		        1000	/* decrementer freq: 1 ms ticks */

#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
#define CONFIG_LOOPW            1       /* enable loopw command         */
#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
/* General PCI */
#define CONFIG_PCI			/* include pci support	        */
#undef  CONFIG_PCI_PNP			/* do (not) pci plug-and-play   */
#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
#define CFG_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/

/* Board-specific PCI */
#define CFG_PCI_PRE_INIT                /* enable board pci_pre_init()  */
#define CFG_PCI_TARGET_INIT
#define CFG_PCI_MASTER_INIT

#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
#define CFG_PCI_SUBSYS_ID       0xcafe	/* Whatever */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * External Bus Controller (EBC) Setup
 *----------------------------------------------------------------------*/
#define CFG_FLASH		CFG_FLASH_BASE
#define CFG_CPLD		0x80000000

/* Memory Bank 0 (NOR-FLASH) initialization					*/
#define CFG_EBC_PB0AP		0x03017300
#define CFG_EBC_PB0CR		(CFG_FLASH | 0xda000)

/* Memory Bank 2 (CPLD) initialization						*/
#define CFG_EBC_PB2AP		0x04814500
#define CFG_EBC_PB2CR		(CFG_CPLD | 0x18000)

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_DCACHE_SIZE		(32<<10) /* For AMCC 440 CPUs			*/
#define CFG_CACHELINE_SIZE	32	/* ...			*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
#endif

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
#endif

#endif	/* __CONFIG_H */
Commit	Line	Data
c157d8e2	1	/*
700200c6	2	* (C) Copyright 2005-2007
84286386	3	* Stefan Roese, DENX Software Engineering, sr@denx.de.
c157d8e2 SR	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/************************************************************************
700200c6	25	* yosemite.h - configuration for Yosemite & Yellowstone boards
c157d8e2 SR	26	***********************************************************************/
	27	#ifndef __CONFIG_H
	28	#define __CONFIG_H
	29
	30	/*-----------------------------------------------------------------------
	31	* High Level Configuration Options
	32	----------------------------------------------------------------------/
700200c6 SR	33	/* This config file is used for Yosemite (440EP) and Yellowstone (440GR)*/
700200c6 SR	34	#ifndef CONFIG_YELLOWSTONE
700200c6 SR	35	#define CONFIG_440EP 1 /* Specific PPC440EP support */
	36	#define CONFIG_HOSTNAME yosemite
	37	#else
	38	#define CONFIG_440GR 1 /* Specific PPC440GR support */
	39	#define CONFIG_HOSTNAME yellowstone
	40	#endif
	41	#define CONFIG_4xx 1 /* ... PPC4xx family */
c157d8e2 SR	42	#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
c157d8e2 SR	43
84286386 SR	44	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
84286386 SR	45	#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
f3443867	46	#define CONFIG_BOARD_RESET 1 /* call board_reset() */
84286386	47
c157d8e2 SR	48	/*-----------------------------------------------------------------------
	49	* Base addresses -- Note these are effective addresses where the
	50	* actual resources get mapped (not physical addresses)
	51	----------------------------------------------------------------------/
84286386 SR	52	#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
	53	#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
	54	#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
	55	#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
	56	#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */
	57	#define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/
	58	#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
	59	#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
	60	#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
c157d8e2 SR	61
c157d8e2 SR	62	/Don't change either of these/
84286386 SR	63	#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals*/
84286386 SR	64	#define CFG_PCI_BASE 0xe0000000 /* internal PCI regs*/
c157d8e2 SR	65	/Don't change either of these/
c157d8e2 SR	66
84286386 SR	67	#define CFG_USB_DEVICE 0x50000000
	68	#define CFG_NVRAM_BASE_ADDR 0x80000000
	69	#define CFG_BCSR_BASE (CFG_NVRAM_BASE_ADDR \| 0x2000)
	70	#define CFG_BOOT_BASE_ADDR 0xf0000000
c157d8e2 SR	71
	72	/*-----------------------------------------------------------------------
	73	* Initial RAM & stack pointer (placed in SDRAM)
	74	----------------------------------------------------------------------/
887e2ec9	75	#define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */
84286386 SR	76	#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */
	77	#define CFG_INIT_RAM_END (8 << 10)
	78	#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data*/
c157d8e2 SR	79	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	80	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	81
c157d8e2 SR	82	/*-----------------------------------------------------------------------
	83	* Serial Port
	84	----------------------------------------------------------------------/
c157d8e2	85	#define CFG_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */
84286386 SR	86	#define CONFIG_BAUDRATE 115200
84286386 SR	87	#define CONFIG_SERIAL_MULTI 1
c157d8e2 SR	88	/define this if you want console on UART1/
	89	#undef CONFIG_UART1_CONSOLE
	90
	91	#define CFG_BAUDRATE_TABLE \
	92	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
	93
	94	/*-----------------------------------------------------------------------
84286386	95	* Environment
c157d8e2	96	----------------------------------------------------------------------/
84286386 SR	97	/*
	98	* Define here the location of the environment variables (FLASH or EEPROM).
	99	* Note: DENX encourages to use redundant environment in FLASH.
	100	*/
	101	#if 1
	102	#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
	103	#else
	104	#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
	105	#endif
c157d8e2 SR	106
	107	/*-----------------------------------------------------------------------
	108	* FLASH related
	109	----------------------------------------------------------------------/
095b8a37 WD	110	#define CFG_FLASH_CFI /* The flash is CFI compatible */
	111	#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
	112	#define CFG_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */
c157d8e2 SR	113
	114	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
	115	#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
	116
	117	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	118	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
	119
278bc4b3 SR	120	#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
278bc4b3 SR	121
c157d8e2	122	#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
84286386 SR	123
	124	#ifdef CFG_ENV_IS_IN_FLASH
	125	#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
	126	#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
	127	#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
	128
	129	/* Address and size of Redundant Environment Sector */
	130	#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
	131	#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
	132	#endif /* CFG_ENV_IS_IN_FLASH */
c157d8e2 SR	133
	134	/*-----------------------------------------------------------------------
	135	* DDR SDRAM
	136	----------------------------------------------------------------------/
095b8a37	137	#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */
84286386 SR	138	#define CFG_KBYTES_SDRAM (128 * 1024) /* 128MB */
	139	#define CFG_SDRAM_BANKS (2)
	140
c157d8e2 SR	141
	142	/*-----------------------------------------------------------------------
	143	* I2C
	144	----------------------------------------------------------------------/
	145	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
	146	#undef CONFIG_SOFT_I2C /* I2C bit-banged */
	147	#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
	148	#define CFG_I2C_SLAVE 0x7F
	149
c157d8e2	150	#define CFG_I2C_MULTI_EEPROMS
c157d8e2 SR	151	#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
	152	#define CFG_I2C_EEPROM_ADDR_LEN 1
	153	#define CFG_EEPROM_PAGE_WRITE_ENABLE
	154	#define CFG_EEPROM_PAGE_WRITE_BITS 3
	155	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
	156
84286386 SR	157	#ifdef CFG_ENV_IS_IN_EEPROM
	158	#define CFG_ENV_SIZE 0x200 /* Size of Environment vars */
	159	#define CFG_ENV_OFFSET 0x0
	160	#endif /* CFG_ENV_IS_IN_EEPROM */
	161
	162	#define CONFIG_PREBOOT "echo;" \
	163	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	164	"echo"
	165
	166	#undef CONFIG_BOOTARGS
	167
700200c6 SR	168	/* Setup some board specific values for the default environment variables */
	169	#ifndef CONFIG_YELLOWSTONE
	170	#define CONFIG_HOSTNAME yosemite
	171	#define CFG_BOOTFILE "bootfile=/tftpboot/yosemite/uImage\0"
	172	#define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0"
	173	#else
	174	#define CONFIG_HOSTNAME yellowstone
	175	#define CFG_BOOTFILE "bootfile=/tftpboot/yellowstone/uImage\0"
	176	#define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xx\0"
	177	#endif
	178
84286386	179	#define CONFIG_EXTRA_ENV_SETTINGS \
700200c6 SR	180	CFG_BOOTFILE \
700200c6 SR	181	CFG_ROOTPATH \
84286386	182	"netdev=eth0\0" \
84286386	183	"nfsargs=setenv bootargs root=/dev/nfs rw " \
fe126d8b	184	"nfsroot=${serverip}:${rootpath}\0" \
84286386	185	"ramargs=setenv bootargs root=/dev/ram rw\0" \
fe126d8b WD	186	"addip=setenv bootargs ${bootargs} " \
	187	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	188	":${hostname}:${netdev}:off panic=1\0" \
	189	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
84286386	190	"flash_nfs=run nfsargs addip addtty;" \
fe126d8b	191	"bootm ${kernel_addr}\0" \
84286386	192	"flash_self=run ramargs addip addtty;" \
fe126d8b WD	193	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
fe126d8b WD	194	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
84286386	195	"bootm\0" \
700200c6	196	"bootfile=/tftpboot/${hostname}/uImage\0" \
84286386	197	"kernel_addr=fc000000\0" \
56ced709	198	"ramdisk_addr=fc180000\0" \
700200c6	199	"load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \
84286386	200	"update=protect off fff80000 ffffffff;era fff80000 ffffffff;" \
700200c6	201	"cp.b 200000 fff80000 80000;" \
84286386 SR	202	"setenv filesize;saveenv\0" \
	203	"upd=run load;run update\0" \
	204	""
	205	#define CONFIG_BOOTCOMMAND "run flash_self"
	206
	207	#if 0
	208	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
	209	#else
	210	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	211	#endif
c157d8e2	212
84286386 SR	213	#define CONFIG_BAUDRATE 115200
	214
	215	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
c157d8e2 SR	216	#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
c157d8e2 SR	217
84286386 SR	218	#define CONFIG_MII 1 /* MII PHY management */
	219	#define CONFIG_NET_MULTI 1 /* required for netconsole */
	220	#define CONFIG_PHY1_ADDR 3
c157d8e2 SR	221	#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
c157d8e2 SR	222	#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
c157d8e2	223
1e25f957 SR	224	#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
	225
	226	#define CONFIG_NETCONSOLE /* include NetConsole support */
c157d8e2 SR	227
	228	/* Partitions */
	229	#define CONFIG_MAC_PARTITION
	230	#define CONFIG_DOS_PARTITION
	231	#define CONFIG_ISO_PARTITION
	232
846b0dd2	233	#ifdef CONFIG_440EP
c157d8e2 SR	234	/* USB */
	235	#define CONFIG_USB_OHCI
	236	#define CONFIG_USB_STORAGE
	237
700200c6	238	/* Comment this out to enable USB 1.1 device */
c157d8e2	239	#define USB_2_0_DEVICE
700200c6 SR	240
	241	#define CMD_USB (CFG_CMD_USB \| CFG_CMD_FAT \| CFG_CMD_EXT2)
	242
	243	#define CONFIG_SUPPORT_VFAT
	244	#else
	245	#define CMD_USB 0 /* no USB on 440GR */
	246	#endif /* CONFIG_440EP */
c157d8e2 SR	247
	248	#ifdef DEBUG
	249	#define CONFIG_PANIC_HANG
	250	#else
	251	#define CONFIG_HW_WATCHDOG /* watchdog */
	252	#endif
	253
84286386 SR	254	#define CONFIG_COMMANDS (CONFIG_CMD_DFL \| \
	255	CFG_CMD_ASKENV \| \
	256	CFG_CMD_DHCP \| \
	257	CFG_CMD_DIAG \| \
	258	CFG_CMD_ELF \| \
4f92ed5f	259	CFG_CMD_EEPROM \| \
84286386 SR	260	CFG_CMD_I2C \| \
	261	CFG_CMD_IRQ \| \
	262	CFG_CMD_MII \| \
	263	CFG_CMD_NET \| \
	264	CFG_CMD_NFS \| \
	265	CFG_CMD_PCI \| \
	266	CFG_CMD_PING \| \
	267	CFG_CMD_REGINFO \| \
	268	CFG_CMD_SDRAM \| \
700200c6	269	CMD_USB)
3b6748ea	270
c157d8e2 SR	271	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
	272	#include <cmd_confdefs.h>
	273
	274	/*
	275	* Miscellaneous configurable options
	276	*/
	277	#define CFG_LONGHELP /* undef to save memory */
84286386	278	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
c157d8e2	279	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
84286386	280	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
c157d8e2	281	#else
84286386	282	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
c157d8e2	283	#endif
84286386 SR	284	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	285	#define CFG_MAXARGS 16 /* max number of command args */
	286	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
c157d8e2	287
84286386 SR	288	#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
84286386 SR	289	#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
c157d8e2 SR	290
c157d8e2 SR	291	#define CFG_LOAD_ADDR 0x100000 /* default load address */
84286386 SR	292	#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
84286386 SR	293	#define CONFIG_LYNXKDI 1 /* support kdi files */
c157d8e2	294
84286386	295	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
c157d8e2	296
4f92ed5f SR	297	#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
	298	#define CONFIG_LOOPW 1 /* enable loopw command */
	299	#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
	300	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
	301	#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
	302
c157d8e2 SR	303	/*-----------------------------------------------------------------------
	304	* PCI stuff
	305	*-----------------------------------------------------------------------
	306	*/
	307	/* General PCI */
84286386 SR	308	#define CONFIG_PCI /* include pci support */
	309	#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
	310	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
	311	#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
c157d8e2 SR	312
c157d8e2 SR	313	/* Board-specific PCI */
84286386	314	#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
c157d8e2 SR	315	#define CFG_PCI_TARGET_INIT
	316	#define CFG_PCI_MASTER_INIT
	317
84286386 SR	318	#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
84286386 SR	319	#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
c157d8e2 SR	320
	321	/*
	322	* For booting Linux, the board info and command line data
	323	* have to be in the first 8 MB of memory, since this is
	324	* the maximum mapped by the Linux kernel during initialization.
	325	*/
	326	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
84286386	327
36adff36 SR	328	/*-----------------------------------------------------------------------
	329	* External Bus Controller (EBC) Setup
	330	----------------------------------------------------------------------/
	331	#define CFG_FLASH CFG_FLASH_BASE
	332	#define CFG_CPLD 0x80000000
	333
	334	/* Memory Bank 0 (NOR-FLASH) initialization */
	335	#define CFG_EBC_PB0AP 0x03017300
	336	#define CFG_EBC_PB0CR (CFG_FLASH \| 0xda000)
	337
	338	/* Memory Bank 2 (CPLD) initialization */
	339	#define CFG_EBC_PB2AP 0x04814500
	340	#define CFG_EBC_PB2CR (CFG_CPLD \| 0x18000)
	341
c157d8e2 SR	342	/*-----------------------------------------------------------------------
	343	* Cache Configuration
	344	*/
0c8721a4	345	#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
c157d8e2 SR	346	#define CFG_CACHELINE_SIZE 32 /* ... */
	347	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	348	#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	349	#endif
	350
	351	/*
	352	* Internal Definitions
	353	*
	354	* Boot Flags
	355	*/
	356	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	357	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	358
	359	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	360	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
	361	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
	362	#endif
84286386	363
c157d8e2	364	#endif /* __CONFIG_H */