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1/*
2 * (C) Copyright 2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
3765b3e7 5 * SPDX-License-Identifier: GPL-2.0+
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6 */
7
8/************************************************************************
9 * zeus.h - configuration for Zeus board
10 ***********************************************************************/
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14/*-----------------------------------------------------------------------
15 * High Level Configuration Options
16 *----------------------------------------------------------------------*/
17#define CONFIG_ZEUS 1 /* Board is Zeus */
18#define CONFIG_4xx 1 /* ... PPC4xx family */
19#define CONFIG_405EP 1 /* Specifc 405EP support*/
20
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21#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
22
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23#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
24
25#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
26#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
27
28#define PLLMR0_DEFAULT PLLMR0_333_111_55_111
29#define PLLMR1_DEFAULT PLLMR1_333_111_55_111
30
5a1aceb0 31#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
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32
33#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
34
96e21f86 35#define CONFIG_PPC4xx_EMAC
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36#define CONFIG_MII 1 /* MII PHY management */
37#define CONFIG_PHY_ADDR 0x01 /* PHY address */
38#define CONFIG_HAS_ETH1 1
39#define CONFIG_PHY1_ADDR 0x11 /* EMAC1 PHY address */
6d0f6bcf 40#define CONFIG_SYS_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
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41#define CONFIG_PHY_RESET 1
42#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */
43
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44/*
45 * BOOTP options
46 */
47#define CONFIG_BOOTP_BOOTFILESIZE
48#define CONFIG_BOOTP_BOOTPATH
49#define CONFIG_BOOTP_GATEWAY
50#define CONFIG_BOOTP_HOSTNAME
51
52/*
53 * Command line configuration.
54 */
55#include <config_cmd_default.h>
56
57#define CONFIG_CMD_ASKENV
58#define CONFIG_CMD_CACHE
59#define CONFIG_CMD_DHCP
60#define CONFIG_CMD_DIAG
61#define CONFIG_CMD_EEPROM
62#define CONFIG_CMD_ELF
63#define CONFIG_CMD_I2C
64#define CONFIG_CMD_IRQ
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65#define CONFIG_CMD_MII
66#define CONFIG_CMD_NET
67#define CONFIG_CMD_NFS
68#define CONFIG_CMD_PING
69#define CONFIG_CMD_REGINFO
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70
71/* POST support */
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72#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
73 CONFIG_SYS_POST_CPU | \
74 CONFIG_SYS_POST_CACHE | \
75 CONFIG_SYS_POST_UART | \
76 CONFIG_SYS_POST_ETHER)
779e9751 77
6d0f6bcf 78#define CONFIG_SYS_POST_ETHER_EXT_LOOPBACK /* eth POST using ext loopack connector */
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79
80/* Define here the base-addresses of the UARTs to test in POST */
5d7c73e6 81#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1 }
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82
83#define CONFIG_LOGBUFFER
6d0f6bcf 84#define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */
779e9751 85
6d0f6bcf 86#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
779e9751 87
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88#undef CONFIG_WATCHDOG /* watchdog disabled */
89
90/*-----------------------------------------------------------------------
91 * SDRAM
92 *----------------------------------------------------------------------*/
93/*
94 * SDRAM configuration (please see cpu/ppc/sdram.[ch])
95 */
96#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
97#define CONFIG_SDRAM_BANK1 1 /* init onboard SDRAM bank 1 */
98
99/* SDRAM timings used in datasheet */
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100#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
101#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
102#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */
103#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
104#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
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105
106/*-----------------------------------------------------------------------
107 * Serial Port
108 *----------------------------------------------------------------------*/
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109#define CONFIG_CONS_INDEX 1
110#define CONFIG_SYS_NS16550
111#define CONFIG_SYS_NS16550_SERIAL
112#define CONFIG_SYS_NS16550_REG_SIZE 1
113#define CONFIG_SYS_NS16550_CLK get_serial_clock()
6d0f6bcf 114#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
550650dd 115#define CONFIG_SYS_BASE_BAUD 691200
779e9751 116#define CONFIG_BAUDRATE 115200
779e9751 117
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118#define CONFIG_SYS_BAUDRATE_TABLE \
119 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
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120
121/*-----------------------------------------------------------------------
122 * Miscellaneous configurable options
123 *----------------------------------------------------------------------*/
6d0f6bcf 124#define CONFIG_SYS_LONGHELP /* undef to save memory */
3b3bff4c 125#if defined(CONFIG_CMD_KGDB)
6d0f6bcf 126#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
779e9751 127#else
6d0f6bcf 128#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
779e9751 129#endif
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130#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
131#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
132#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
779e9751 133
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134#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
135#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
779e9751 136
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137#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
138#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
779e9751 139
779e9751 140#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf 141#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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142
143#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
144#define CONFIG_LOOPW 1 /* enable loopw command */
145#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
146#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
147#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
148
149/*-----------------------------------------------------------------------
150 * I2C
151 *----------------------------------------------------------------------*/
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152#define CONFIG_SYS_I2C
153#define CONFIG_SYS_I2C_PPC4XX
154#define CONFIG_SYS_I2C_PPC4XX_CH0
155#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
156#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
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157
158/* these are for the ST M24C02 2kbit serial i2c eeprom */
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159#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */
160#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
779e9751 161/* mask of address bits that overflow into the "EEPROM chip address" */
6d0f6bcf 162#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
779e9751 163
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164#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* 8 byte write page size */
165#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
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166
167/*
168 * The layout of the I2C EEPROM, used for bootstrap setup and for board-
169 * specific values, like ethaddr... that can be restored via the sw-reset
170 * button
171 */
172#define FACTORY_RESET_I2C_EEPROM 0x50
173#define FACTORY_RESET_ENV_OFFS 0x80
174#define FACTORY_RESET_ENV_SIZE 0x80
175
176/*-----------------------------------------------------------------------
177 * Start addresses for the final memory configuration
178 * (Set up by the startup code)
6d0f6bcf 179 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
779e9751 180 */
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181#define CONFIG_SYS_SDRAM_BASE 0x00000000
182#define CONFIG_SYS_FLASH_BASE 0xFF000000
183#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
184#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
185#define CONFIG_SYS_MONITOR_BASE (-CONFIG_SYS_MONITOR_LEN)
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186
187/*
188 * For booting Linux, the board info and command line data
189 * have to be in the first 8 MB of memory, since this is
190 * the maximum mapped by the Linux kernel during initialization.
191 */
6d0f6bcf 192#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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193
194/*-----------------------------------------------------------------------
195 * FLASH organization
196 */
6d0f6bcf 197#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
00b1883a 198#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
779e9751 199
6d0f6bcf 200#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
779e9751 201
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202#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
203#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
779e9751 204
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205#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
206#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
779e9751 207
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208#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
209#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
779e9751 210
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211#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
212#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
779e9751 213
5a1aceb0 214#ifdef CONFIG_ENV_IS_IN_FLASH
0e8d1586 215#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
6d0f6bcf 216#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
0e8d1586 217#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
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218
219/* Address and size of Redundant Environment Sector */
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220#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
221#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
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222#endif
223
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224/*-----------------------------------------------------------------------
225 * Definitions for initial stack pointer and data area (in data cache)
226 */
227/* use on chip memory (OCM) for temperary stack until sdram is tested */
6d0f6bcf 228#define CONFIG_SYS_TEMP_STACK_OCM 1
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229
230/* On Chip Memory location */
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231#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
232#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
233#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of OCM */
553f0982 234#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
779e9751 235
25ddd1fb 236#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
779e9751 237/* reserve some memory for POST and BOOT limit info */
6d0f6bcf 238#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 16)
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239
240/* extra data in OCM */
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241#define CONFIG_SYS_POST_MAGIC \
242 (CONFIG_SYS_OCM_DATA_ADDR + CONFIG_SYS_GBL_DATA_OFFSET - 8)
243#define CONFIG_SYS_POST_VAL \
244 (CONFIG_SYS_OCM_DATA_ADDR + CONFIG_SYS_GBL_DATA_OFFSET - 12)
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245
246/*-----------------------------------------------------------------------
247 * External Bus Controller (EBC) Setup
248 */
249
250/* Memory Bank 0 (Flash 16M) initialization */
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251#define CONFIG_SYS_EBC_PB0AP 0x05815600
252#define CONFIG_SYS_EBC_PB0CR 0xFF09A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit */
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253
254/*-----------------------------------------------------------------------
255 * Definitions for GPIO setup (PPC405EP specific)
256 *
257 * GPIO0[0] - External Bus Controller BLAST output
258 * GPIO0[1-9] - Instruction trace outputs
259 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
260 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
261 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
262 * GPIO0[24-27] - UART0 control signal inputs/outputs
263 * GPIO0[28-29] - UART1 data signal input/output
264 * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
265 */
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266#define CONFIG_SYS_GPIO0_OSRL 0x15555550 /* Chip selects */
267#define CONFIG_SYS_GPIO0_OSRH 0x00000110 /* UART_DTR-pin 27 alt out */
268#define CONFIG_SYS_GPIO0_ISR1L 0x10000041 /* Pin 2, 12 is input */
269#define CONFIG_SYS_GPIO0_ISR1H 0x15505440 /* OUT: LEDs 22/23; IN: pin12,2, NVALID# */
6d0f6bcf 270#define CONFIG_SYS_GPIO0_TSRL 0x00000000
afabb498 271#define CONFIG_SYS_GPIO0_TSRH 0x00000000
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272#define CONFIG_SYS_GPIO0_TCR 0xBFF68317 /* 3-state OUT: 22/23/29; 12,2 is not 3-state */
273#define CONFIG_SYS_GPIO0_ODR 0x00000000
274
275#define CONFIG_SYS_GPIO_SW_RESET 1
276#define CONFIG_SYS_GPIO_ZEUS_PE 12
277#define CONFIG_SYS_GPIO_LED_RED 22
278#define CONFIG_SYS_GPIO_LED_GREEN 23
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279
280/* Time in milli-seconds */
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281#define CONFIG_SYS_TIME_POST 5000
282#define CONFIG_SYS_TIME_FACTORY_RESET 10000
779e9751 283
3b3bff4c 284#if defined(CONFIG_CMD_KGDB)
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285#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
286#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
287#endif
288
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289/*
290 * Pass open firmware flat tree
291 */
292#define CONFIG_OF_LIBFDT
293#define CONFIG_OF_BOARD_SETUP
294
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295/* ENVIRONMENT VARS */
296
297#define CONFIG_PREBOOT "echo;echo Welcome to Bulletendpoints board v1.1;echo"
298#define CONFIG_IPADDR 192.168.1.10
299#define CONFIG_SERVERIP 192.168.1.100
300#define CONFIG_GATEWAYIP 192.168.1.100
301#define CONFIG_ETHADDR 50:00:00:00:06:00
302#define CONFIG_ETH1ADDR 50:00:00:00:06:01
303#if 0
304#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
305#else
306#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
307#endif
308
309#define CONFIG_EXTRA_ENV_SETTINGS \
310 "logversion=2\0" \
311 "hostname=zeus\0" \
312 "netdev=eth0\0" \
313 "ethact=ppc_4xx_eth0\0" \
314 "netmask=255.255.255.0\0" \
315 "ramdisk_size=50000\0" \
316 "nfsargs=setenv bootargs root=/dev/nfs rw" \
317 " nfsroot=${serverip}:${rootpath}\0" \
318 "ramargs=setenv bootargs root=/dev/ram rw" \
e5084af8 319 " ramdisk_size=${ramdisk_size}\0" \
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320 "addip=setenv bootargs ${bootargs} " \
321 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
93e14596 322 ":${hostname}:${netdev}:off panic=1\0" \
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323 "addtty=setenv bootargs ${bootargs} console=ttyS0," \
324 "${baudrate}\0" \
325 "net_nfs=tftp ${kernel_mem_addr} ${file_kernel};" \
326 "run nfsargs addip addtty;bootm\0" \
327 "net_ram=tftp ${kernel_mem_addr} ${file_kernel};" \
328 "tftp ${ramdisk_mem_addr} ${file_fs};" \
329 "run ramargs addip addtty;" \
330 "bootm ${kernel_mem_addr} ${ramdisk_mem_addr}\0" \
331 "rootpath=/target_fs/zeus\0" \
332 "kernel_fl_addr=ff000000\0" \
333 "kernel_mem_addr=200000\0" \
334 "ramdisk_fl_addr=ff300000\0" \
335 "ramdisk_mem_addr=4000000\0" \
336 "uboot_fl_addr=fffc0000\0" \
337 "uboot_mem_addr=100000\0" \
338 "file_uboot=/zeus/u-boot.bin\0" \
339 "tftp_uboot=tftp 100000 ${file_uboot}\0" \
340 "update_uboot=protect off fffc0000 ffffffff;" \
341 "era fffc0000 ffffffff;cp.b 100000 fffc0000 40000;" \
342 "protect on fffc0000 ffffffff\0" \
343 "upd_uboot=run tftp_uboot;run update_uboot\0" \
344 "file_kernel=/zeus/uImage_ba\0" \
345 "tftp_kernel=tftp 100000 ${file_kernel}\0" \
346 "update_kernel=protect off ff000000 ff17ffff;" \
347 "era ff000000 ff17ffff;cp.b 100000 ff000000 180000\0" \
348 "upd_kernel=run tftp_kernel;run update_kernel\0" \
349 "file_fs=/zeus/rootfs_ba.img\0" \
350 "tftp_fs=tftp 100000 ${file_fs}\0" \
351 "update_fs=protect off ff300000 ff87ffff;era ff300000 ff87ffff;"\
93e14596 352 "cp.b 100000 ff300000 580000\0" \
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353 "upd_fs=run tftp_fs;run update_fs\0" \
354 "bootcmd=chkreset;run ramargs addip addtty addmisc;" \
355 "bootm ${kernel_fl_addr} ${ramdisk_fl_addr}\0" \
356 ""
357
358#endif /* __CONFIG_H */