[people/ms/u-boot.git] / include / fsl_mmdc.h

/*
 * Copyright 2016 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef FSL_MMDC_H
#define FSL_MMDC_H

/* PHY Write Leveling Configuration and Error Status Register (MPWLGCR) */
#define MPWLGCR_HW_WL_EN		(1 << 0)

/* PHY Pre-defined Compare and CA delay-line Configuration (MPPDCMPR2) */
#define MPPDCMPR2_MPR_COMPARE_EN	(1 << 0)


/* MMDC PHY Read DQS gating control register 0 (MPDGCTRL0) */
#define AUTO_RD_DQS_GATING_CALIBRATION_EN	(1 << 28)

/* MMDC PHY Read Delay HW Calibration Control Register (MPRDDLHWCTL) */
#define MPRDDLHWCTL_AUTO_RD_CALIBRATION_EN	(1 << 4)

/* MMDC Core Power Saving Control and Status Register (MMDC_MAPSR) */
#define MMDC_MAPSR_PWR_SAV_CTRL_STAT	0x00001067

/* MMDC Core Refresh Control Register (MMDC_MDREF) */
#define MDREF_START_REFRESH	(1 << 0)

/* MMDC Core Special Command Register (MDSCR) */
#define CMD_ADDR_MSB_MR_OP(x)	(x << 24)
#define CMD_ADDR_LSB_MR_ADDR(x) (x << 16)
#define MDSCR_DISABLE_CFG_REQ   (0 << 15)
#define MDSCR_ENABLE_CON_REQ	(1 << 15)
#define MDSCR_CON_ACK		(1 << 14)
#define MDSCR_WL_EN		(1 << 9)
#define	CMD_NORMAL		(0 << 4)
#define	CMD_PRECHARGE		(1 << 4)
#define	CMD_AUTO_REFRESH	(2 << 4)
#define	CMD_LOAD_MODE_REG	(3 << 4)
#define	CMD_ZQ_CALIBRATION	(4 << 4)
#define	CMD_PRECHARGE_BANK_OPEN	(5 << 4)
#define	CMD_MRR			(6 << 4)
#define CMD_BANK_ADDR_0		0x0
#define CMD_BANK_ADDR_1		0x1
#define CMD_BANK_ADDR_2		0x2
#define CMD_BANK_ADDR_3		0x3
#define CMD_BANK_ADDR_4		0x4
#define CMD_BANK_ADDR_5		0x5
#define CMD_BANK_ADDR_6		0x6
#define CMD_BANK_ADDR_7		0x7

/* MMDC Core Control Register (MDCTL) */
#define MDCTL_SDE0		(1 << 31)
#define MDCTL_SDE1		(1 << 30)

/* MMDC PHY ZQ HW control register (MMDC_MPZQHWCTRL) */
#define MPZQHWCTRL_ZQ_HW_FORCE	(1 << 16)

/* MMDC PHY Measure Unit Register (MMDC_MPMUR0) */
#define MMDC_MPMUR0_FRC_MSR	(1 << 11)

/* MMDC PHY Read delay-lines Configuration Register (MMDC_MPRDDLCTL) */
/* default 64 for a quarter cycle delay */
#define MMDC_MPRDDLCTL_DEFAULT_DELAY	0x40404040

/* MMDC Registers */
struct mmdc_regs {
	u32 mdctl;
	u32 mdpdc;
	u32 mdotc;
	u32 mdcfg0;
	u32 mdcfg1;
	u32 mdcfg2;
	u32 mdmisc;
	u32 mdscr;
	u32 mdref;
	u32 res1[2];
	u32 mdrwd;
	u32 mdor;
	u32 mdmrr;
	u32 mdcfg3lp;
	u32 mdmr4;
	u32 mdasp;
	u32 res2[239];
	u32 maarcr;
	u32 mapsr;
	u32 maexidr0;
	u32 maexidr1;
	u32 madpcr0;
	u32 madpcr1;
	u32 madpsr0;
	u32 madpsr1;
	u32 madpsr2;
	u32 madpsr3;
	u32 madpsr4;
	u32 madpsr5;
	u32 masbs0;
	u32 masbs1;
	u32 res3[2];
	u32 magenp;
	u32 res4[239];
	u32 mpzqhwctrl;
	u32 mpzqswctrl;
	u32 mpwlgcr;
	u32 mpwldectrl0;
	u32 mpwldectrl1;
	u32 mpwldlst;
	u32 mpodtctrl;
	u32 mprddqby0dl;
	u32 mprddqby1dl;
	u32 mprddqby2dl;
	u32 mprddqby3dl;
	u32 mpwrdqby0dl;
	u32 mpwrdqby1dl;
	u32 mpwrdqby2dl;
	u32 mpwrdqby3dl;
	u32 mpdgctrl0;
	u32 mpdgctrl1;
	u32 mpdgdlst0;
	u32 mprddlctl;
	u32 mprddlst;
	u32 mpwrdlctl;
	u32 mpwrdlst;
	u32 mpsdctrl;
	u32 mpzqlp2ctl;
	u32 mprddlhwctl;
	u32 mpwrdlhwctl;
	u32 mprddlhwst0;
	u32 mprddlhwst1;
	u32 mpwrdlhwst0;
	u32 mpwrdlhwst1;
	u32 mpwlhwerr;
	u32 mpdghwst0;
	u32 mpdghwst1;
	u32 mpdghwst2;
	u32 mpdghwst3;
	u32 mppdcmpr1;
	u32 mppdcmpr2;
	u32 mpswdar0;
	u32 mpswdrdr0;
	u32 mpswdrdr1;
	u32 mpswdrdr2;
	u32 mpswdrdr3;
	u32 mpswdrdr4;
	u32 mpswdrdr5;
	u32 mpswdrdr6;
	u32 mpswdrdr7;
	u32 mpmur0;
	u32 mpwrcadl;
	u32 mpdccr;
};

struct fsl_mmdc_info {
	u32 mdctl;
	u32 mdpdc;
	u32 mdotc;
	u32 mdcfg0;
	u32 mdcfg1;
	u32 mdcfg2;
	u32 mdmisc;
	u32 mdref;
	u32 mdrwd;
	u32 mdor;
	u32 mdasp;
	u32 mpodtctrl;
	u32 mpzqhwctrl;
	u32 mprddlctl;
};

void mmdc_init(const struct fsl_mmdc_info *);

#endif /* FSL_MMDC_H */
Commit	Line	Data
b7f2bbff PK	1	/*
	2	* Copyright 2016 Freescale Semiconductor, Inc.
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#ifndef FSL_MMDC_H
	8	#define FSL_MMDC_H
	9
b9e745bb SL	10	/* PHY Write Leveling Configuration and Error Status Register (MPWLGCR) */
b9e745bb SL	11	#define MPWLGCR_HW_WL_EN (1 << 0)
b7f2bbff PK	12
b7f2bbff PK	13	/* PHY Pre-defined Compare and CA delay-line Configuration (MPPDCMPR2) */
b9e745bb	14	#define MPPDCMPR2_MPR_COMPARE_EN (1 << 0)
b7f2bbff	15
b7f2bbff PK	16
b7f2bbff PK	17	/* MMDC PHY Read DQS gating control register 0 (MPDGCTRL0) */
b9e745bb	18	#define AUTO_RD_DQS_GATING_CALIBRATION_EN (1 << 28)
b7f2bbff PK	19
b7f2bbff PK	20	/* MMDC PHY Read Delay HW Calibration Control Register (MPRDDLHWCTL) */
b9e745bb	21	#define MPRDDLHWCTL_AUTO_RD_CALIBRATION_EN (1 << 4)
b7f2bbff	22
b9e745bb SL	23	/* MMDC Core Power Saving Control and Status Register (MMDC_MAPSR) */
b9e745bb SL	24	#define MMDC_MAPSR_PWR_SAV_CTRL_STAT 0x00001067
b7f2bbff	25
b9e745bb SL	26	/* MMDC Core Refresh Control Register (MMDC_MDREF) */
b9e745bb SL	27	#define MDREF_START_REFRESH (1 << 0)
b7f2bbff PK	28
b7f2bbff PK	29	/* MMDC Core Special Command Register (MDSCR) */
b9e745bb SL	30	#define CMD_ADDR_MSB_MR_OP(x) (x << 24)
	31	#define CMD_ADDR_LSB_MR_ADDR(x) (x << 16)
	32	#define MDSCR_DISABLE_CFG_REQ (0 << 15)
	33	#define MDSCR_ENABLE_CON_REQ (1 << 15)
	34	#define MDSCR_CON_ACK (1 << 14)
	35	#define MDSCR_WL_EN (1 << 9)
	36	#define CMD_NORMAL (0 << 4)
	37	#define CMD_PRECHARGE (1 << 4)
	38	#define CMD_AUTO_REFRESH (2 << 4)
	39	#define CMD_LOAD_MODE_REG (3 << 4)
	40	#define CMD_ZQ_CALIBRATION (4 << 4)
	41	#define CMD_PRECHARGE_BANK_OPEN (5 << 4)
	42	#define CMD_MRR (6 << 4)
b7f2bbff PK	43	#define CMD_BANK_ADDR_0 0x0
	44	#define CMD_BANK_ADDR_1 0x1
	45	#define CMD_BANK_ADDR_2 0x2
	46	#define CMD_BANK_ADDR_3 0x3
	47	#define CMD_BANK_ADDR_4 0x4
	48	#define CMD_BANK_ADDR_5 0x5
	49	#define CMD_BANK_ADDR_6 0x6
	50	#define CMD_BANK_ADDR_7 0x7
	51
b9e745bb SL	52	/* MMDC Core Control Register (MDCTL) */
	53	#define MDCTL_SDE0 (1 << 31)
	54	#define MDCTL_SDE1 (1 << 30)
	55
	56	/* MMDC PHY ZQ HW control register (MMDC_MPZQHWCTRL) */
	57	#define MPZQHWCTRL_ZQ_HW_FORCE (1 << 16)
	58
	59	/* MMDC PHY Measure Unit Register (MMDC_MPMUR0) */
	60	#define MMDC_MPMUR0_FRC_MSR (1 << 11)
	61
	62	/* MMDC PHY Read delay-lines Configuration Register (MMDC_MPRDDLCTL) */
	63	/* default 64 for a quarter cycle delay */
	64	#define MMDC_MPRDDLCTL_DEFAULT_DELAY 0x40404040
	65
b7f2bbff	66	/* MMDC Registers */
b9e745bb	67	struct mmdc_regs {
b7f2bbff PK	68	u32 mdctl;
	69	u32 mdpdc;
	70	u32 mdotc;
	71	u32 mdcfg0;
	72	u32 mdcfg1;
	73	u32 mdcfg2;
	74	u32 mdmisc;
	75	u32 mdscr;
	76	u32 mdref;
	77	u32 res1[2];
	78	u32 mdrwd;
	79	u32 mdor;
	80	u32 mdmrr;
	81	u32 mdcfg3lp;
	82	u32 mdmr4;
	83	u32 mdasp;
	84	u32 res2[239];
	85	u32 maarcr;
	86	u32 mapsr;
	87	u32 maexidr0;
	88	u32 maexidr1;
	89	u32 madpcr0;
	90	u32 madpcr1;
	91	u32 madpsr0;
	92	u32 madpsr1;
	93	u32 madpsr2;
	94	u32 madpsr3;
	95	u32 madpsr4;
	96	u32 madpsr5;
	97	u32 masbs0;
	98	u32 masbs1;
	99	u32 res3[2];
	100	u32 magenp;
	101	u32 res4[239];
	102	u32 mpzqhwctrl;
	103	u32 mpzqswctrl;
	104	u32 mpwlgcr;
	105	u32 mpwldectrl0;
	106	u32 mpwldectrl1;
	107	u32 mpwldlst;
	108	u32 mpodtctrl;
	109	u32 mprddqby0dl;
	110	u32 mprddqby1dl;
	111	u32 mprddqby2dl;
	112	u32 mprddqby3dl;
b9e745bb SL	113	u32 mpwrdqby0dl;
	114	u32 mpwrdqby1dl;
	115	u32 mpwrdqby2dl;
	116	u32 mpwrdqby3dl;
b7f2bbff PK	117	u32 mpdgctrl0;
	118	u32 mpdgctrl1;
	119	u32 mpdgdlst0;
	120	u32 mprddlctl;
	121	u32 mprddlst;
	122	u32 mpwrdlctl;
	123	u32 mpwrdlst;
	124	u32 mpsdctrl;
	125	u32 mpzqlp2ctl;
	126	u32 mprddlhwctl;
	127	u32 mpwrdlhwctl;
	128	u32 mprddlhwst0;
	129	u32 mprddlhwst1;
	130	u32 mpwrdlhwst0;
	131	u32 mpwrdlhwst1;
	132	u32 mpwlhwerr;
	133	u32 mpdghwst0;
	134	u32 mpdghwst1;
	135	u32 mpdghwst2;
	136	u32 mpdghwst3;
	137	u32 mppdcmpr1;
	138	u32 mppdcmpr2;
	139	u32 mpswdar0;
	140	u32 mpswdrdr0;
	141	u32 mpswdrdr1;
	142	u32 mpswdrdr2;
	143	u32 mpswdrdr3;
	144	u32 mpswdrdr4;
	145	u32 mpswdrdr5;
	146	u32 mpswdrdr6;
	147	u32 mpswdrdr7;
	148	u32 mpmur0;
	149	u32 mpwrcadl;
	150	u32 mpdccr;
	151	};
	152
1fdcc8df YS	153	struct fsl_mmdc_info {
	154	u32 mdctl;
	155	u32 mdpdc;
	156	u32 mdotc;
	157	u32 mdcfg0;
	158	u32 mdcfg1;
	159	u32 mdcfg2;
	160	u32 mdmisc;
	161	u32 mdref;
	162	u32 mdrwd;
	163	u32 mdor;
	164	u32 mdasp;
	165	u32 mpodtctrl;
	166	u32 mpzqhwctrl;
	167	u32 mprddlctl;
	168	};
b9e745bb	169
1fdcc8df	170	void mmdc_init(const struct fsl_mmdc_info *);
b9e745bb	171
b7f2bbff	172	#endif /* FSL_MMDC_H */